DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitation "the present distance" in line 1. There is insufficient antecedent basis for this limitation in the claim.
It seems that “the present distance” refers to “a preset distance” as previously mentioned in claim 5 upon which it depends. Therefore, for the examination purpose, “a present distance” is assumed as a preset distance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 6, 10, 12, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP 2002-110902 (with English Translation attached).
Regarding claim 1, JP ‘902 (Figs. 1 and 2) discloses a semiconductor structure, comprising: a substrate 10, comprising an external circuit 10P2; a chip set, disposed at one side of the substrate and comprising a plurality of chip units 11-14 (page 11, paragraph 3 of translation) that are spaced in a direction perpendicular to the substrate, wherein the chip units 11-14 are electrically connected to each other (i.e., electrically connected to each other through solder balls 18b formed therebetween); a conductive structure (11P, 11M) (page 9, first line of translation), disposed on a surface of at least one of the chip units 11; and a wire 15A, wherein one end of the wire 15A is connected to the conductive structure, and another end extends outside of the chip units and is connected to the external circuit 10P2; wherein the conductive structure (11P, 11M) comprises: a redistribution layer 11M (page 9, first line of translation), disposed on the surface of the at least one of the chip units; a connection pad 11P, disposed on a surface of a chip unit on which the redistribution layer 11M is formed and connected to a side of the redistribution layer close to an edge of the chip unit 11, wherein the wire 15A is connected to the connection pad 11P in a contact manner; and a first conductive bump 11Q (i.e., pad forming as a bump, page 9, first line of translation), disposed on the surface of the chip unit 11 and connected to the redistribution layer 11M in a contact manner, wherein an orthographic projection of the first conductive bump 11Q on the substrate does not overlap with an orthographic projection of the connection pad 11P on the substrate.
Regarding claims 3 and 6, JP ‘902 (Figs. 1 and 2) further discloses: the conductive structure is located on a surface of a chip unit 11 closest to the substrate in the chip set; and an insulation filling layer 16 (page 11, paragraph 3 of translation), filling a gap between two adjacent ones of the chip units 11-14.
Regarding claim 10, JP ‘902 (Figs. 1 and 2) discloses a method for forming a semiconductor structure, comprising: providing a substrate 10, wherein the substrate comprises an external circuit 10P2; forming a chip set on one side of the substrate, wherein the chip set comprises a plurality of chip units 11-14 (page 11, paragraph 3 of translation) that are spaced in a direction perpendicular to the substrate, and the chip units 11-14 are electrically connected to each other (i.e., electrically connected to each other through solder balls 18b formed therebetween); forming a conductive structure (11P, 11M) (page 9, first line of translation) on a surface of at least one of the chip units 11; and forming a wire 15A, wherein one end of the wire 15A is connected to the conductive structure, and another end extends outside of the chip units 11 and is connected to the external circuit 10P2; wherein the forming a conductive structure on a surface of at least one of the chip units comprises: forming a redistribution layer 11M (page 9, first line of translation) on the surface of the at least one of the chip units 11; forming a connection pad 11P (page 9, first line of translation) on a surface of a chip unit 11 on which the redistribution layer is formed, wherein the connection pad 11P is connected to a side of the redistribution layer 11M close to an edge of the chip unit, and the wire 15A is connected to the connection pad 11P in a contact manner; and forming a first conductive bump 11Q (i.e., pad forming as a bump, page 9, first line of translation) on the surface of the chip unit 11 on which the redistribution layer is formed, wherein the first conductive bump 11Q is connected to the redistribution layer in a contact manner, and an orthographic projection of the first conductive bump 11Q on the substrate does not overlap with an orthographic projection of the connection pad 11P on the substrate.
Regarding claims 12 and 15, JP ‘902 (Figs. 1 and 2) further discloses: the conductive structure 11P is formed on a surface of a chip unit 11 that is closest to the substrate in the chip set; and forming an insulation filling layer 16 (page 11, paragraph 3 of translation), wherein the insulation filling layer 16 fills a gap between two adjacent ones of the chip units 11-14.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4, 6-9, 10, 12-13 and 15-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Baek (US 2023/0009850).
Regarding claim 1, Baek (Fig. 4A) discloses a semiconductor structure, comprising: a substrate 101, comprising an external circuit 120; a chip set 200f ([0067]), disposed at one side of the substrate and comprising a plurality of chip units 200f-1/200f-2 that are spaced in a direction perpendicular to the substrate, wherein the chip units are electrically connected to each other (i.e., electrically connected to each other by connecting to a common wiring line 126, [0042]); a conductive structure 210d-1, ([0067]), disposed on a surface of at least one of the chip units 200f-1; and a wire 220-1, wherein one end of the wire 220-1 is connected to the conductive structure, and another end extends outside of the chip units and is connected to the external circuit 120, wherein the conductive structure comprises: a redistribution layer 230-1 ([0067]), disposed on the surface of the at least one of the chip units 200f-1; a connection pad 210d-1, disposed on a surface of a chip unit 200f-1 on which the redistribution layer is formed and connected to a side of the redistribution layer 230-1 close to an edge of the chip unit, wherein the wire 220-1 is connected to the connection pad in a contact manner; and a first conductive bump 210-1 (i.e., pad forming as a bump), disposed on the surface of the chip unit and connected to the redistribution layer in a contact manner, wherein an orthographic projection of the first conductive bump 210-1 on the substrate does not overlap with an orthographic projection of the connection pad 210d-1 on the substrate.
Regarding claims 3-4 and 6-9, Baek (Fig. 4A) further discloses: the conductive structure 210d-1 is located on a surface of a chip unit 200f-1 closest to the substrate in the chip set; the chip set comprises a first chip unit 200f-1 and a second chip unit 200f-2 that are in mirror arrangement; the second chip unit 200f-2 is located at a side of the first chip unit away from the substrate; and the conductive structure 210d-1 is disposed on a surface of the first chip unit 200f-1 close to the second chip unit 200f-2; an insulation filling layer 250 ([0034]), filling a gap between two adjacent ones of the chip units; there are a plurality of chip sets (i.e., 2 chip sets, 200f-1/200f-2 and 200f-3/200f-4); the plurality of chip sets are distributed in a laminated manner in the direction perpendicular to the substrate; the chip sets are insulated from each other (i.e., insulated by insulating layer 250); and each of the chip sets has a corresponding conductive structure 210d and a corresponding wire 220; an adhesive layer 250 ([0034]), disposed between the substrate and a chip set closest to the substrate; and a plurality of packaging layers 250, disposed at gaps between the chip sets in a one-to-one correspondence and filling the gaps between the chip sets.
Regarding claim 10, Baek (Fig. 4A) discloses a method for forming a semiconductor structure, comprising: providing a substrate 101, wherein the substrate comprises an external circuit 120; forming a chip set 200f on one side of the substrate, wherein the chip set comprises a plurality of chip units 200f-1/200f-2 that are spaced in a direction perpendicular to the substrate, and the chip units 200f-1/200f-2 are electrically connected to each other (i.e., electrically connected to each other by connecting through a common wiring line 126, [0042]); forming a conductive structure 210d-1 on a surface of at least one of the chip units 200f-1; and forming a wire 220-1, wherein one end of the wire is connected to the conductive structure, and another end extends outside of the chip units and is connected to the external circuit 120; wherein the forming a conductive structure on a surface of at least one of the chip units comprises: forming a redistribution layer 230-1 on the surface of the at least one of the chip units 200f-1; forming a connection pad 210d-1 on a surface of a chip unit on which the redistribution layer is formed, wherein the connection pad 210d-1 is connected to a side of the redistribution layer close to an edge of the chip unit 200f-1, and the wire 220-1 is connected to the connection pad in a contact manner; and forming a first conductive bump 210-1 (i.e., pad forming as a bump) on the surface of the chip unit 200f-1 on which the redistribution layer is formed, wherein the first conductive bump 210-1 is connected to the redistribution layer 230-1 in a contact manner, and an orthographic projection of the first conductive bump 210-1 on the substrate does not overlap with an orthographic projection of the connection pad 210d-1 on the substrate.
Regarding claims 12-13 and 15-18, Baek (Fig. 4A) further discloses: the conductive structure 210d-1 is formed on a surface of a chip unit 200f-1 that is closest to the substrate in the chip set; the chip set comprises a first chip unit 200f-1 and a second chip unit 200f-2 that are in mirror arrangement; the second chip unit 200f-2 is formed on a side of the first chip unit 200f-1 away from the substrate; and the conductive structure 210d-1 is formed on a surface of the first chip unit 200f-1 close to the second chip unit 200f-2; forming an insulation filling layer 250, wherein the insulation filling layer 250 fills a gap between two adjacent ones of the chip units; there are a plurality of chip sets (i.e., 2 chip sets, 200f-1/200f-2 and 200f-3/200f-4) ; the plurality of chip sets are distributed in a laminated manner in the direction perpendicular to the substrate; the chip sets are insulated from each other (i.e., insulated by insulating layer 250); and each of the chip sets 200f has a corresponding conductive structure 210d and a corresponding wire 220; forming an adhesive layer 250 ([0034]) between the substrate and a chip set closest to the substrate; and forming a plurality of packaging layers 250, wherein the packaging layers are disposed at gaps between the chip sets in a one-to-one correspondence and fill the gaps between the chip sets.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over JP 2002-110902 in view of Baek (US 2023/0009850).
Regarding claims 4 and 13, JP ‘902 further discloses the chip set comprises a first chip unit 11 and a second chip unit 12, the second chip unit 12 is formed on a side of the first chip unit 11 away from the substrate; and the conductive structure 11P is formed on a surface of the first chip unit 11 close to the second chip unit 12.
JP ‘902 does not disclose the first chip unit and the second chip unit that are in mirror arrangement.
However, Baek (Fig. 4A) teaches a chip set 200f comprising a first chip unit 200f-1 and a second chip unit 200f-2 that are in mirror arrangement. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify JP ‘092 by forming the first chip unit and the second chip unit that are in mirror arrangement in order to provide a semiconductor package including a stack structure comprising the same desired type of the first chip unit and the second chip unit, as taught by Baek (i.e., same memory chips, [0039]).
Regarding claims 5 and 14, JP ‘902 (Figs. 1-2) further discloses: a surface of the second chip unit 12 close to the first chip unit 11 is provided with a second conductive bump 12G (i.e., pad forming as a bump); the second conductive bump 12G is disposed oppositely to the first conductive bump; and the chip set further comprises: a connection portion 18B, located between the first conductive bump and the second conductive bump, wherein the first conductive bump 11Q, the connection portion 18B and the second conductive bump 12G separate the first chip unit 11 and the second chip unit 12 by a preset distance.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over JP ‘902 and Baek as applied to claim 5 above, and further in view of Heo (US 6,555,917).
Neither JP ‘902 nor Baek disclose the preset distance (as assumed in 112-2nd rejection) is greater than longitudinal spacing required for a bending of the wire.
However, Heo (Fig. 1) teaches a semiconductor structure, comprising: a chip set, disposed at one side of the substrate and comprising a plurality of chip units 10-1 and 10-2; a connection structure (32, 34) located between the first chip unit and the second chip unit and separating the first chip unit and the second chip unit by a preset distance; and the preset distance is greater than longitudinal spacing required for a bending of the wire 30. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify JP ‘092 by forming the preset distance being greater than longitudinal spacing required for a bending of the wire because as is well known, such preset distance could be adjusted and optimized during routine experimentation for preventing the wire from being damaged by contacting with the second chip unit.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2023/0009850) in view of Park et al (US 2017/0098622).
Baek does not specifically disclose the first conductive bump 210-1 (i.e., pad) connects to a circuit module of the chip unit 200f-1.
However, Park (Fig. 4A and 13, especially Fig. 13) teaches a semiconductor structure comprising a first conductive bump 110 (i.e., pad, [0089]) connecting to a circuit module IC1 (Figs. 4A and 13, and [0089]) of the chip unit 20a. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the first conductive bump 210-1 of JP ‘092 to a circuit module of the chip unit 200f-1 in order to transmit/receive the data/signals from/to the circuit module.
Response to Arguments
Applicant's arguments filed 08/24/25 have been fully considered but they are not persuasive.
Claims rejection over JP 2002-110902
Applicant argues that Fig. 4 of JP ‘902 does not suggest “the chip units are
electrically connected to each other” as recited in independent claims 1 and 10 because the first chip unit 11 is not electrically connected to the second chip unit 12.
This argument is not persuasive because Fig. 4 of JP ‘902 clearly discloses the first chip 11 is electrically connected to the second chip 12 through the conductive solder balls 18B (see annotations of Fig. 4 reproduced below).
[AltContent: textbox (Solder ball 18b provided electrical contacts between first and second chips 11 and 12)]
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Claims rejection over Baek
Applicant argues that Fig. 4A of Beck does not suggest “the chip units are
electrically connected to each other” as recited in independent claims 1 and 10 because the first chip unit 200f-1 is not electrically connected to the second chip unit 200f-2.
This argument is not persuasive because Fig. 4A of Baek clearly discloses the
first chip unit 200f-1 is electrically connected to the second chip unit 200f-2 because they are both electrically connected to the same common wiring lines 126 (see annotations of Fig. 4A reproduced below and [0042]).
[AltContent: oval][AltContent: arrow][AltContent: textbox (both chips electrically connected to a common wiring line 126)]
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256
406
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Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PHAT X CAO/ Primary Examiner, Art Unit 2817
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