DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 11/27/2025. Claims 1-2, 4, and 6-17 are pending in this application. Claim 1 is amended. Claims 3, 5, and 18 are canceled. Claims 11-17 remain withdrawn.
Claims 1-2, 4, and 6-10 are presented in this Office Action.
Priority
Acknowledgment is made of applicant’s claim for foreign priority based on an application CN 202110289188.6 filed in the China National Intellectual Property Administration (CNIPA) on 3/18/2021 and receipt of a certified copy thereof.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2, 4, and 6-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 has been amended to recite limitation “a thickness of the first channel region is equal to a thickness of the second channel region, and equal to a sum of a thickness of the second doped layer and a thickness of the third doped layer” in lines 23-25.
The specification discloses a first channel region 221, a second doped layer 152, and a third doped layer 151 (see, paragraph [0042], [0045], and [0070]-[0073] and FIGS. 4C-4G). However, the specification does not disclose, either expressly or inherently, that the thickness of the first channel region is equal to the combined thickness of the second doped layer and the third doped layer, nor does it disclose that the thickness of the first channel region is defined by, bounded by, or otherwise directly related to the thicknesses of the second doped layer and third doped layer.
Paragraph [0073] describes forming the first doped layer (153), second doped layer (152), third doped layer (151), and channel regions (221 and 222) through doping processes. The specification indicates that these regions are formed through separate doping operations and does not describe any dimensional dependency or equality relationship between the thickness of the channel region and the thicknesses of the second and third doped layers.
Furthermore, the specification distinguishes between a first connection structure (112) and a second connection structure, wherein the second connection structure includes the first doped layer (153), second doped layer (152), and third doped layer (151) (see, paragraph [0042]). The first connection structure (112) is described separately from the doped layers (151-153), and the channel regions (221, 222) are disclosed as being formed on the first connection structure (112) (see, paragraphs [0026], [0065], and [0073]). Thus, the specification does not disclose that the thickness of the channel region is defined by or directly related to the thicknesses of the second and third doped layers of the second connection structure.
Paragraph [0076], cited by applicant in Remarks, describes forming gate dielectric layers, and drain electrodes, but does not disclose or suggest that the thickness of the channel region is equal to the combined thicknesses of the second doped layer and the third doped layer.
Additionally, the specification does not disclose any planarization, etch-back, or leveling process that would define or constrain the thickness of the channel region relative to the thicknesses of the second and third doped layers. The specification does not describe any process that would result in or ensure that the thickness of the channel region is equal to the combined thicknesses of the second and third doped layers.
Furthermore, the drawings (FIGS. 4C-4H) are schematic in nature and do not establish precise dimensional relationships. The specification does not state that the relative thicknesses illustrated in the drawings are to scale or that the thickness of the channel regions equals the sum of the thicknesses of the second and third doped layers.
Accordingly, the originally filed specification does not reasonably convey to one of ordinary skill in the art that the inventor had possession of the claimed dimensional relationship at the time of filing.
Claims 2, 4, and 6-10 are rejected due to their dependency.
Appropriate correction is required.
Allowable Subject Matter
Claims 1-2, 4, and 6-10, under BRI, would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112 (pre-AIA ), first paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The applied prior art neither anticipates nor renders the claimed subject matter obvious because it fails to teach the claimed semiconductor structure,
“a pair of second connection structures connecting the bottom structure and located on opposite sides of the first channel region and the second channel region; wherein each of the pair of second connection structures comprises a first doped layer on the bottom structure, a second doped layer on the first doped layer, and a third doped layer on the second doped layer; and
a doping concentration of the second doped layer is lower than that of the first doped layer and the third doped layer; and
wherein a thickness of the first channel region is equal to a thickness of the second channel region, and equal to a sum of a thickness of the second doped layer and a thickness of the third doped layer” in combination with all other limitations, as recited in claim 1 and
“the conductive feature of the first redistribution circuit structure is continuously extended on and in contact with the electrically conductive structure disposed on the bottom of the recess” in combination with all other limitations, as recited in claim 1.
Claims 2, 4, and 6-10 are rejected as being dependent from claim 1.
Ping et al. (CN 209658176U) discloses a semiconductor memory structure including a substrate, vertical transistors, and storage structures connected to the drain electrodes; however, Ping does not teach or suggest first and second vertical transistors sharing a common source electrode having a bottom structure with connection structures on opposite sides that included stacked doped layers with different doping concentrations, nor the claimed thickness relationship between the channel regions and the doped layers.
Zhu (US 2020/0357795) discloses a vertical transistor on a substrate with a gate stack surrounding a vertical channel and stacked source/drain regions; however, Zhu does not teach or suggest two vertical transistors sharing one source electrode with opposite-side connection structures that include a three-layer doped stack with a lower-doped middle layer, nor the claimed channel-thickness relationship.
Su et al. (US 2015/0069500) discloses a vertical transistor having source regions arranged as a pair on opposite sides of respective channel regions and having different doping concentrations; however, Su does not teach or suggest first and second vertical transistors sharing a common source electrode as claimed, nor the claimed thickness relationship between the channel regions and the doped layers.
Pillarisetty et al. (US 2019/0355726) discloses a vertical transistor having stacked diffusion regions and channel regions and provides example thickness values for such regions; however, Pillarisetty does not teach or suggest the claimed thickness relationship wherein a thickness of each channel region is equal to a sum of thicknesses of specific doped layers, as required by the claimed structure.
Hofmann et al. (US 2003/0117865) discloses a vertical transistor and teaches that channel thickness and doped region thickness are independently adjustable; however, Hofmann does not teach or suggest the claimed thickness relationship requiring the claimed thickness to equal a sum of thickness of specific doped layers.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/23/26
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