Detailed Action
This office action is in response to the amendment filed on February 17th, 2026. Claims 1-20 are pending. Claims 2, 5-6, 14, 16, and 20 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed February 17th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 11-15, “Remarks”) that Fang and Chien fail to teach the limitations in amended Claims 1 and 11.
However, as seen below, Claims 1 and 11 are rejected by the combination of Chen, Chien, and Wang.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Applicant argues (pgs. 15-16, “Remarks”) that one of ordinary skill in the art would not have made the alleged modification to Fang at least because there is no disclosure in either reference as to how Fang's BSPD structures would have been connected to the active sheets AS1-AS4 if the BSPD structures were at equal intervals. As discussed above, Fang's BSPDA and BSPDB structures connect to the active sheets AS1- AS4 using back-side via regions VR1-VR4 between the active sheets AS1-AS4, respectively, and one of the BSPD structures (see paras. 46-47). Moreover, as shown in FIG. 2B above, the BSPDA and BSPDB are at unequal intervals. Intervals between the BSPDA and BSPDB structures are smaller between the wider active sheets AS3 and AS4 than between the narrower active sheets AS 1 and AS2. Thus, Fang fails to disclose "the plurality of power lines extend parallel to each other at equal intervals." Moreover, Fang would not have been modified to include this language. For instance, as discussed above in connection with claim 1, connection between the BSPD structures and the active sheets AS1-AS4 is achieved by overlap between the BSPD structures, vias VR1-VR4, and active sheets AS1-AS4. Since the active sheets AS3 and AS4 have different widths from the active sheets AS 1 and AS2, overlap is achieved by having the BSPDA and BSPDB structures at unequal intervals corresponding to the difference in widths between the active sheets. If the BSPD structures were at equal intervals, the BSPD structures would not be aligned with the wider active sheets AS3 and AS4 or the intervening vias VR3 and VR4. But there is no disclosure in Fang or Chien as to how the BSPD structures would have been connected to the active sheets AS1-AS4 without such alignment. Thus, no such modification would have been made.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this instance, applicant is attacking Fang for failing to teach how power lines are connected active regions if the power lines are arranged at cell row boundaries. Fang is not required to teach a via structure to connect power lines to active regions when it is Chien that teaches the arrangement of power lines is an obvious variant. As such, Chien teaches that the power rails are configured to provide cells included in the integrated circuit 10 power voltages.
Therefore, applicant’s arguments are not persuasive.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1, 3-4, and 7-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (2023/0096645 A1; hereinafter Chen) in view of Chien et al. (2021/0407986 A1; hereinafter Chien) and Wang et al. (2021/0202465 A1; hereinafter Wang).
Regarding Claim 1, Chen (annotated fig. 4) teaches a semiconductor device ([0022], 10, see fig. 1) comprising:
first standard cells ([0039], Cell-B) arranged in a first row ([0039], first row, see annotated fig. 4) on a substrate ([0042], substrate, not shown) and respectively including a first base active region ([0040], 202);
second standard cells ([0039], Cell-A) arranged in a second row ([0039], second row, see annotated fig. 4) adjacent to the first row (first row) on the substrate (substrate) and respectively including a second base active region ([0040], 102);
a power line extending in a first direction along a boundary between the first standard cells and the second standard cells, the power line being offset, in a second direction perpendicular to the first direction, from the first base active region and the second base active region; and
a device isolation layer on side surfaces of the first and second base active regions, wherein,
in a plan view, the first standard cells (Cell-B) and the second standard cells (Cell-A) have a same cell height ([0039], H),
the first base active region (202) of each of the first standard cells (Cell-B) includes a first active line ([0040], 202 with width W2N, see annotated fig. 4) having a first conductivity-type ([0040], n-type) and a second active line ([0040], 202 with width W2P, see annotated fig. 4) having a second conductivity-type ([0040], p-type), different from the first conductivity-type (n-type),
the second base active region (102) of each of the second standard cells (Cell-A) includes a third active line ([0040], 102 with width W1N, see annotated fig. 4) having the first conductivity-type ([0040], n-type) and a fourth active line ([0040], 102 with width W1P, see annotated fig. 4) having the second conductivity-type ([0040], p-type),
the first active lines (202 with width W2N) of the first standard cells (Cell-B) arranged in the first row (first row) have a same first width (W2N),
the third active lines (102 with width W1N) of the second standard cells (Cell-A) arranged in the second row (second row) have a same second width (W1N), and
the first width (W2N) is narrower ([0040]) than the second width (W1N).
Chen doesn’t teach explicitly teach a power line extending in a first direction along a boundary between the first standard cells and the second standard cells, the power line being offset, in a second direction perpendicular to the first direction, from the first base active region and the second base active region.
However, Chien (figs. 1A-B) teaches a power line ([0024], 112) extending in a first direction ([0024], x) along a boundary between the first standard cells ([0020], cells in ROW1) and the second standard cells ([0020], cells in ROW2), the power line (112) being offset, in a second direction ([0021], y) perpendicular to the first direction ([0021], x), from the first base active region ([0025], 123) and the second base active region ([0025], 122). One of ordinary skill in the art would have found it obvious to try and arrange the power lines at the boundaries between cell rows and yielded the predictable results of providing power to the cells.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to arrange the power lines at the boundaries between cell rows since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Chen doesn’t teach a device isolation layer on side surfaces of the first and second base active regions.
However, Wang (fig. 1C) teaches a device isolation layer ([0019], 104) on side surfaces (see fig. 1C) of the first ([0019], 106) and second base active regions ([0019], 108). Wang also teaches that the isolation features define and electrically isolate the various active regions ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Chen to include the device isolation layer of Wang to define and electrically isolate the active regions.
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Annotated Figure 4
Regarding Claim 3, Chen (annotated fig. 4) teaches the semiconductor device of claim 1, wherein the second active line (202 with width W2P) has a third width (W2P), different ([0035]) from the first width (W2N), and the fourth active line (102 with width W1P) has a fourth width (W1P), different ([0027]) from the second width (W1N).
Regarding Claim 4, the combination of Chen (annotated fig. 4) and Chien (figs. 1A-B) teaches the semiconductor device of claim 3, wherein a distance between the first active line (Chen, [0040], distance D2 between 202 with width W2N and the boundary BN) and the power line (Chien, 112; Chien’s 112 may be considered to be placed at the position of Fang’s boundary BN) is less than a distance between the second active line (Chen, [0040], distance D1 between 102 with width W1N and the boundary BN) and the power line (Chien, 112), and a distance between the third active line (Chen, distance between 202 with width W2P and the boundary BN, see annotated fig. 4) and the power line (Chien, 112) is less than a distance between the fourth active line (Chen, distance between 102 with width W1P and the boundary BN, see fig. 2A) and the power line (Chien, 112).
Regarding Claim 7, Chen doesn’t teach the semiconductor device of claim 1, wherein each of the first standard cells further includes at least one first active fin extending in the first direction on the first active line, each of the second standard cells further includes at least one second active fin extending in the first direction on the third active line, and a number of first active fins is less than a number of second active fins.
However, Chien (figs. 1A-B) teaches each of the first standard cells ([0020], cells in ROW2) further includes at least one first active fin ([0025], 124) extending in the first direction ([0025], x) on the first active line (portion of substrate under 124), each of the second standard cells ([0020], cells in ROW1) further includes at least one second active fin ([0025], 121) extending in the first direction (x) on the third active line (portion of substrate under 121), and a number of first active fins (124) is less than a number of second active fins (121). One of ordinary skill in the art could have substituted the fins of Chien for the active structures of Fang and yielded the predictable results of forming functional transistors such as a finFET.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the fins of Chien for the active structures of Chen, since simple substitution of active structures is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 8, Chen doesn’t teach the semiconductor device of claim 1, wherein each of the first standard cells further includes first channel layers vertically spaced apart from each other on the first active line, each of the second standard cells further includes second channel layers vertically spaced apart from each other on the second active line, and a width of the first channel layers is smaller than a width of the second channel layers.
However, Wang (fig. 1C) teaches each of the first standard cells ([0027], 120, see fig. 1A) further includes first channel layers ([0028], 130 stacked in region 108) vertically spaced apart from each other on the first active line (108), each of the second standard cells ([0027], 122, see fig. 1A) further includes second channel layers ([0028], 130 stacked in region 106) vertically spaced apart from each other on the second active line (106), and a width of the first channel layers (130 in 108) is smaller (see fig. 1C) than a width of the second channel layers (130 in 106). One of ordinary skill in the art could have substituted the stacked channels of Wang for the active structures of Fang and yielded the predictable results of forming functional transistors such as a GAA FET.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the stacked channels of Wang for the active structures of Chen, since simple substitution of active structures is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 9, Chen (annotated fig. 5) teaches the semiconductor device of claim 1, further comprising: third standard cells ([0044], Cell-C) arranged in a third row (third row, see annotated fig. 5) on the substrate (substrate) and respectively including a third base active region ([0045], 302), and wherein in the plan view, the third standard cell (Cell-C) has a same cell height ([0044], H) as each of the first (Cell-B) and second standard cells (Cell-A).
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Annotated Figure 5
Regarding Claim 10, Chen (annotated fig. 4) teaches the semiconductor device of claim 9, wherein the third base active region (302) includes a fifth active line ([0046], 302 with width W4N) having the first conductivity-type ([0046], n-type) and a sixth active line ([0046], 302 with width W4P) having the second conductivity-type ([0046], p-type), the fifth active lines (302 with width W4N) of the third standard cells (302) arranged in the third row (Cell-C) have the same third width (W4N), and the third width (W4N) is different (see annotated figs. 4 and 5) from the first width (W2N) and the second width (W1N).
Regarding Claim 11, Chen (annotated fig. 4) teaches a semiconductor device ([0022], 10, see fig. 1) comprising:
a substrate ([0042], substrate, not shown) having base active regions ([0040], 102, 202) extending in a first direction ([0039], x);
a plurality of standard cells ([0039], Cell-A, Cell-B) respectively including a gate structure ([0040], 104, 204) extending in a second direction ([0039], Y), crossing the first direction (X), on the base active regions (102, 202), and
source/drain regions on the base active regions at both sides of the gate structure; and
a plurality of power lines respectively extending in the first direction along boundaries of the plurality of standard cells and configured to supply power to the plurality of standard cells the plurality of power lines having central axes respectively extending in the first direction and aligned with the boundaries, respectively, in a second direction that is perpendicular to the first direction, wherein
the plurality of standard cells (Cell-A, Cell-B) are arranged in a plurality of rows (first row, second row, see annotated fig. 4) having a same cell height ([0039], H) in the second direction (Y),
each of the base active regions (102, 202) includes a first active line ([0040], 202 with width W2N and 102 with width W1N, see annotated fig. 4) having a first conductivity-type ([0040], n-type) and a second active line ([0040], 202 with width W2P and 102 with width W1P) having a second conductivity-type ([0040], p-type), different from the first conductivity-type (n-type),
the base active regions (102, 202) include first groups (202) including first base active regions (202 with width W2N and W2P) and second groups (102) including second base active regions (102 with width W1N and W1P),
in each of the first groups (202), the first base active regions (202 with width W2N and W2P) include the first active lines (202 with width W2N) having a first width (W2N) and arranged in the first direction (X) in one of the plurality of rows (Cell-B), and
in each of the second groups (102), the second base active regions (102 with width W1N and W1P) include the first active lines (102 with width W1N) having a second width (W1N), different ([0040]) from the first width (W2N), and arranged in the first direction (X) in one of the plurality of rows (Cell-A), wherein
the first groups and the second groups are arranged at regular intervals in the second direction.
Chen doesn’t teach source/drain regions on the base active regions at both sides of the gate structure.
However, Wang (fig. 1B) teaches source/drain regions ([0033], 126) on the base active regions ([0019], 106, 108) at both sides of the gate structure ([0018], 112, see fig. 1B). One of ordinary skill in the art would have found it obvious to try and arrange source/drain features adjacent to the gate and yielded the predictable results of forming a functional transistor.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to arrange source/drain regions adjacent to the gate since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Chen doesn’t teach a plurality of power lines respectively extending in the first direction along boundaries of the plurality of standard cells and configured to supply power to the plurality of standard cells the plurality of power lines having central axes respectively extending in the first direction and aligned with the boundaries, respectively, in a second direction that is perpendicular to the first direction.
However, Chien (figs. 1A-B) teaches a plurality of power lines ([0024], 111-119) respectively extending in the first direction ([0024], x) along boundaries of the plurality of standard cells ([0020], cells in ROW1-ROW8) and configured to supply power ([0024]) to the plurality of standard cells (cells in ROW1-ROW8) the plurality of power lines (111-119) having central axes respectively extending in the first direction (x) and aligned with the boundaries, respectively, in a second direction ([0021], Y) that is perpendicular to the first direction (x). One of ordinary skill in the art would have found it obvious to try and arrange the power lines at the boundaries between cell rows and yielded the predictable results of providing power to the cells.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to arrange the power lines at the boundaries between cell rows since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Chen doesn’t teach the first groups and the second groups are arranged at regular intervals in the second direction.
However, Wang (figs. 3 and 9) teaches the first groups ([0019], 106, see fig. 3) and the second groups ([0019], 108, see fig. 3) are arranged at regular intervals ([0046], see fig. 9) in the second direction ([0024], X). Wang also teaches an alternatively placing first and second groups of cells improves fabrication uniformity ([0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Chen to include the cell arrangement of Wang to improve device uniformity.
Regarding Claim 12, the combination of Chen (annotated fig. 4) and Wang (fig. 9) teaches the semiconductor device of claim 11, wherein the first width (Chen, W2N) is narrower (Chen, [0040]) than the second width (Chen,W1N), and in the second direction (Wang, X), the first groups (Wang, 106) and the second groups (Wang, 108) are arranged at an interval ratio of 2n:2 (Wang, arranged alternatively, so a ratio of 1:1), respectively.
Regarding Claim 13, Wang (annotated fig. 4) teaches the semiconductor device of claim 12, wherein n is an integer in a range of 1 to 4 (arranged alternatively, so a ratio of 1:1, therefore n is 1).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Chien, and Wang as applied to Claim 11 above, and further in view of Fang et al. (2021/0357565 A1; hereinafter Fang).
Regarding Claim 15, Chen (annotated figs. 4 and 5) teaches the semiconductor device of claim 11, wherein the base active regions ([0045], 102, 202, may also include 302, see annotated fig. 5) further include third groups (302) including third base active regions ([0045], 3021, 3022, see annotated fig. 5), and in each of the third groups (302), the third base active regions (3021, 3022) include the first active lines (3021) having a third width ([0046], W4N, see annotated fig. 5) and arranged in the first direction (X) and in one of the plurality of rows ([0045], Cell-C), the third width (W4N) is different (see annotated figs. 4-5) from the first width (W2N) and the second width (W1N), and wherein the third groups are arranged at regular intervals from the first groups and the second groups in the second direction.
Chen doesn’t teach the third groups are arranged at regular intervals from the first groups and the second groups in the second direction.
However, Fang (fig. 4A) teaches the third groups ([0075], AS5, AS6) are arranged at regular intervals ([0079], AS1-AS6 are sequentially arranged at regular intervals from each other) from the first groups ([0075], AS1, AS2) and the second groups ([0075], AS3, AS4) in the second direction ([0072], Y). One of ordinary skill in the art would have found it obvious to try and arrange the three groups of active regions sequentially and yielded the predictable results of an integrated circuit.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to arrange three groups of active regions at regular intervals since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Fang in view of Chien.
Regarding Claim 17, Fang (figs. 2A-B) teaches a semiconductor device ([0018], 100A/B) comprising:
a substrate ([0019], 100S) having a base active region ([0022], AS1-4);
a plurality of standard cells ([0030]) arranged in a plurality of rows ([0019], RA, RB) on the substrate (100S); and
a plurality of power lines ([0045], BSPD, see fig. 2B) extending in a first direction along boundaries of the plurality of standard cells and configured to supply power to the plurality of standard cells ([0045]), wherein
each of the plurality of standard cells includes a gate structure ([0029], GS1-9, see fig. 1A) extending in a second direction ([0029], Y), crossing the first direction (X), on the base active region (AS1-8), and source/drain regions ([0030], S/D regions, not shown) on the base active region (AS1-8) at both sides of the gate structure ([0030], S/D regions are adjacent to the gate structures GS1-9),
the plurality of power lines extend parallel to each other at equal intervals, and
the base active region (AS1-8) includes first (AS1, AS2) and second base active regions (AS3, AS4) having different widths ([0048], WA1-WA4) in different rows (RA, RB) among the plurality of rows and arranged in the first direction (X).
Fang doesn’t teach a plurality of power lines extending in a first direction along boundaries of the plurality of standard cells and the plurality of power lines extend parallel to each other at equal intervals. Fang does teach that the different rows (RA, RB) have the same cell height ([0055], both RA and RB have cell heights of five times track pitch).
However, Chien (figs. 1A-B) teaches a plurality of power lines ([0024], 111-119) extending in a first direction ([0024], x) along boundaries of the plurality of standard cells ([0020], cells in ROW1-ROW8). One of ordinary skill in the art would have found it obvious to try and arrange the power lines at the boundaries between cell rows and yielded the predictable results of providing power to the cells.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to arrange the power lines at the boundaries between cell rows since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). The combination of Fang and Chien would then teach the plurality of power lines (Chien, 111-119) extend parallel to each other at equal intervals (Fang, equal cell height rows).
Regarding Claim 18, Fang (figs. 2A-B) teaches the semiconductor device of claim 17, wherein in a plan view (see fig. 2A), the plurality of standard cells in the plurality of rows (RA, RB) have a same cell height ([0055], both RA and RB have cell heights of five times track pitch), each of the first base active regions (AS1, AS2) has a same first width (WA1, WA2) as each other, and each of the second base active regions (AS3, AS4) has a same second width as each other (WA3, WA4).
Regarding Claim 19, Fang (figs. 2A-B) teaches the semiconductor device of claim 17, wherein the plurality of standard cells include first standard cells ([0030]-[0033], cells formed from AS1, AS2 and in row RA) on the first base active regions (AS1, AS2) and second standard cells ([0030]-[0033], cells formed from AS3, AS4 and in row RB) on the second base active regions (AS3, AS4), and in a plurality of adjacent rows (RA, RB), the first standard cells and the second standard cells are arranged at an interval ratio of 2n:2 ([0068], ratio of 2:1, therefore n is 2).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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