DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification Objections
Examiner withdraws the specification objections based upon Applicant’s amendment to the specification, and new figure 1 submittted.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-6, and 9-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1,
The limitation “such that the first and second conductive pillars are electrically isolated from each other” lacks written description support. This is because Applicant’s first and second pillars, figure 5A elements 42 and 41 are insulated in a y-direction by means of 43, but are not insulated from each other in an x-direction. They not insulated from each other because the semiconductor 50 surrounds and directly contacts 41 and 42. Therefore, 41 and 42 are not electrically insulated from each other. As such, Applicant does not have written description support for the above limitation based upon their disclosure.
Applicant may want to reconsider the use of the term insulated.
For purposes of examination, Examiner will treat the term “electrically isolated” as meaning there needs to be an insulator between the first and second pillars, but they can be electrically connected by other means.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou et al. (US 2023/0225130 A1) (“Liou”), in view of Lin et al. (US 2021/0375938 A1) (“Lin II”).
Regarding claim 1, Liou teaches at least in figures 17-18C:
a stacked body comprising (detailed below; hereinafter “A”)
a plurality of alternately provided conductor-including layers (72/90/92) and insulating films (52), provided one on top of another (they are so stacked) along a first direction (vertical direction); and
a plurality of pillar bodies, each pillar body being formed within the stacked body (as will be shown below all of the elements contained in the comprising language are in the stacked body) and comprising (detailed below; hereinafter “B”)
(i) first and second conductive pillars (106/108) each extending along the first direction (vertical direction) through the stacked body (A); and
(ii) an insulator pillar (98) provided between the first and second conductive pillars (106/108) to electrically isolate the first (106) and second (108) conductive pillars (106/108) in the pillar body (B),
wherein the conductor-including layers (72/90/92) each comprises (detailed below)
adjacent each pillar body (B), a semiconductor member (92) in contact with the first and second conductive pillars (106/108, as shown in figure 18A);
(iii) an electrode film (72) and
(iv) a ferroelectric layer (90) between the semiconductor member (92) and the electrode film (72), and also between each conductor-including layer (72) and the adjacent insulating film in the stacked body (98) and
wherein the semiconductor members (92) in the plurality of conductor-including layers (72/90/92) are separated from each other in the first direction (92 is so separated in the vertical direction).
Liou does not teach:
wherein each semiconductor member is in an annular or ring form and is provided only surrounding each respective pillar body and is asbsent between adacent pillar bodies
Lin II teaches at least in figures 9A-9C:
wherein each semiconductor member (116) is in an annular or ring form (figure 8C shows a square annular or ring shape) and is provided only surrounding each respective pillar body (118/120) and is absent between adjacent pillar bodies (figures 9A-9C show that 116 is absent between adjacent pillars as 108 is blocking this from happening).
It would have been obvious to one of ordinary skill in the art to modify Liou with the teachings of Lin II because Lin II teaches by making the semiconductor annular/ring form one can prevent adjacent memory cells from communicating with each other. ¶ 0033. This will reduce the interference between memory cells thereby leading to increased performance of the memory cells.
Regarding claim 3, Liou teaches at least in figures 17-18C:
wherein the first and second conductive pillars (106/108) each comprise a metallic material (¶ 0033) and
wherein the semiconductor member (92) comprises an oxide semiconductor (¶ 0027).
Regarding claim 4, Liou teaches at least in figures 17-18C:
wherein the oxide semiconductor comprises (92) one or more of: indium gallium zirconium oxide (IGZO), indium tungsten oxide (IWO), indium zinc oxide (IZO), indium tin oxide (ITO) and indium gallium zinc oxide (IGZTO) (¶ 0027).
Regarding claim 5, Liou teaches at least in figures 17-18C:
wherein the ferroelectric layer (90) comprises one or more of: hafnium zirconium oxide (HfZrO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), lead zirconate titanate(PZT), zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum zirconium-doped Hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO) and any hafnium oxide that includes zirconium impurities (¶ 0023).
Regarding claim 6, Liou teaches at least in figures 17-18C:
wherein the insulator pillar (98) comprises an insulating material of a single composition (¶¶ 0031-32, where 98 may comprise a single composition or a plurality of compositional materials).
Regarding claim 10, Liou teaches at least in figures 17-18C:
wherein, as seen in a cross section of the pillar body (B) that is normal to the first direction (vertical direction),
the first conductive pillar (106 or 108) and the insulator pillar (98) has a first interface (they have the claimed interface) and
the second conductive pillar (108 or 106) and the insulator pillar has a second interface (they have the claimed interface),
the first and second interfaces being substantially parallel lines (the interfaces are substantially parallel as shown in the figures).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou, in view of Lin II, in view of Lin et al. (US 2022/0293788 A1) (“Lin”).
Regarding claim 2 Liou and Lin II do not teach:
wherein the first and second conductive pillars each comprise a semiconductor material of a first conductivity and
wherein the semiconductor member comprises a semiconductor material of a second conductivity opposite the first conductivity.
This is because Liou teaches:
Using a metal as the source/drain of the device (i.e. the first and second conductive pillar), and IGZO as the channel.
And, because Lin II is silent with respect to the material of the first and second conductive pillars.
Lin teaches:
A similar stacked ferroelectric device to Liou.
Lin teaches:
That one can replace the source/drain of the device with doped polysilicon of n or p type, ¶ 0028, and one can replace the IGZO channel material with doped polysilicon of p or n type, ¶ 0022. Therefore, it would have been obvious to one of ordinary skill in the art to replace the source and drain (first and second conductive pillar) material of Liou with a first doped type of polysilicon, and the channel IGZO material with a second doped type of polysilicon as Lin teaches these are art recognized equivalents for the purpose of being source/drain and channel material, and are art recognized as being so functionally equivalent. MPEP 2144.06-07. Further, having the source/drain doped differently from the channel is a well-known means of forming a transistor. This is generally used to form n-type and p-type transistors. As such, it would only require routine skill in the art.
Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou, in view of Lin II, in view of Chia et al. (US 2022/0020774 A1) (“Chia”)
Regarding claim 11, Liou teaches at least in figures 17-18C:
The memory device (claim 1) being formed on a substrate (50).
Liou does not teach:
the memory device further comprising a plurality of interconnect conductors, wherein the first conductive pillar contacts the substrate, and the second conductive pillar is connected to one of the interconnect conductors.
Chia teaches at least in figures 2K-4:
the memory device (device of claim 1 and the main device of Chia ) further comprising (detailed below)
a plurality of interconnect conductors (194/196/SL/BL),
wherein the first conductive pillar (180) contacts the substrate (110), and
the second conductive pillar (170) is connected to one of the interconnect conductors (194).
It would have been obvious to one of ordinary skill in the art to combine Liou and Chia as Liou only teaches the memory-core structure and does not teach how to incorporate the memory-core structure into a more functioning device. This would lead one to other references to teach the more complete device. This search would have obviously lead to Chia as Chia is directed to the same subject matter as Liou. In ¶¶ 0048, Chia teaches the interconnect structure in figures 2K, 3, and 4 are all obvious variants of each other. Thus, it would have been obvious to one of ordinary skill in the art to choose any of these obvious variants to form a more complete device.
Regarding claim 12, Chia teaches at least in figures 1, and 2K-3:
a conductive plate (at least one of 124/125ss on the left or right) that has a substantially planar surface (top of 124/125 is planar) that extends in both the first direction and a second direction orthogonal to the first direction (at least one of the 124/125s is vertical)
an insulating plate (121) between the conductive plate (124/125s) and the stacked body (123), electrically isolating the conductive plate from the stacked body (124/125 is electrically isolated from 123).
Chia does not explicitly teach:
thereby dividing the stacked body along a third direction that is orthogonal to both the first and the second directions.
However, it would have been obvious to add more stacked structures to the device of Liou and Chia . This is because it would increase the memory capacity of the resulting device by means of duplicating the stacked structure of Liou. MPEP 2144.04(VI)(B).
Regarding claim 13, Chia teaches at least in figures 1, and 2K-3:
wherein the substrate (50) is conductive (50 comprises conductive elements) and the conductive plate (124/125) is electrically connected to the substrate (50).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou, in view of Lin II, in view of Lin, in view of Chia.
Regarding claim 14, the combination of prior art teaches:
wherein the interconnect conductors (Chia 194/196/SL/BL) each extend along the third direction (x or y direction),
wherein the pillar bodies are organized as columns arranged along the third direction (As shown in the prior art the pillar bodies are organized in an array as such they would be in a third direction),
the pillar bodies within each column being arranged along the second direction (as shown in the prior art the pillar bodies are organized in an array as such they would be organized in a second direction) and
wherein adjacent pillar bodies in adjacent columns are offset along the second direction, such that the adjacent pillars are positioned to be contacted by separate ones of the interconnect conductors (this is shown in Liou figure 18A).
Response to Arguments
Applicant’s arguments filed on March 9, 2026, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Liou, in view of Lin II.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
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