Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/9/2026 has been entered.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 10-20 and 24-27 rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (JP 2009088370) of record, in view of Kim (KR 20110024783) of record, in view of Yousef (U.S. Patent No. 6,365,991).
Regarding Claim 1
Suzuki discloses a chip, comprising: a spare cell (C2a, FIG. 6) including: a first active region; and a first gate (G) extending over the first active region in a first direction (vertical); a tie cell (C200, FIG. 7) including: a second active region; a second gate (G of T7) extending over the second active region in the first direction; a first drain contact (D) formed over the second active region; a first source contact (S) formed over the second active region, wherein the second gate is between the first drain contact and the first source contact, and the first source contact is coupled (via 77 and 79) to a first rail (VSS); and a metal routing extending in a second direction, wherein the second direction is perpendicular to the first direction, and a circuit (comprising elements that connect the second gate to VDD) configured to couple the second gate to a second rail (VDD).
Suzuki is silent with respect to “the circuit comprises: a first transistor, wherein a source of the first transistor is coupled to the second rail, and a drain of the first transistor is coupled to the second gate; and a second transistor, wherein a gate of the second transistor is coupled to the gate of the first transistor, a drain of the second transistor is coupled to the gate of the second transistor, and a source of the second transistor is coupled to the first rail” and “the metal routing is coupled to the first drain contact and the first gate”.
FIG. 2a of Kim discloses a similar chip, comprising a metal routing, wherein the circuit comprises: a first transistor (220), wherein a source (224) of the first transistor is coupled to the second rail (VDD), and a drain (226) of the first transistor is coupled to the second gate; and a second transistor (210), wherein a gate (212) of the second transistor is coupled to the gate (222) of the first transistor, a drain (214) of the second transistor is coupled to the gate of the second transistor, and a source (216) of the second transistor is coupled to the first rail (VSS).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Suzuki, as taught by Kim. The ordinary artisan would have been motivated to modify Suzuki in the above manner for purpose of increasing performance of IC (Abstract of Kim).
Suzuki as modified by Kim is silent with respect to “the metal routing is coupled to the first drain contact and the first gate”.
FIG. 1 of Yousef discloses a similar chip, comprising a metal routing (comprising n1), wherein the metal routing is coupled to the first drain contact (of 24) and the first gate (of 32).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Suzuki, as taught by Yousef. The ordinary artisan would have been motivated to modify Suzuki in the above manner for purpose of making multiple power source devices (Col. 1, Lines 14-33 of Yousef).
Regarding Claim 2
Suzuki discloses the first rail comprises a low rail, the second rail comprises a supply rail (VDD), and the low rail has a lower potential (VSS) than the supply rail.
Regarding Claim 3
Suzuki discloses the first rail comprises a supply rail, the second rail comprises a low rail, and the low rail has a lower potential than the supply rail.
Regarding Claim 4
Suzuki discloses the metal routing is formed from a metal layer.
Regarding Claim 5
Suzuki discloses the metal routing comprises a metal line formed from the metal layer.
Regarding Claim 10
FIG. 6 of Suzuki discloses the spare cell further comprises: a third active region, wherein the first gate extends over the third active region; a second drain contact (16) formed over the first active region and the third active region, wherein the second drain contact extends in the first direction.
Regarding Claim 11
FIG. 6 of Suzuki discloses the spare cell further comprises: a second source contact formed over the first active region, wherein the first gate is between the second source contact and the second drain contact, and the second source contact is coupled to the second rail (VDD); and a third source contact formed over the third active region, wherein the first gate is between the third source contact and the second drain contact, and the third source contact is coupled to the first rail.
Regarding Claim 12
FIG. 6 of Suzuki discloses the first active region is a p-type active region, and the third active region is an n-type active region.
Regarding Claim 13
Suzuki discloses the first rail comprises a low rail, the second rail comprises a supply rail, and the low rail has a lower potential than the supply rail.
Regarding Claim 14
Suzuki discloses a chip, comprising: a first spare cell (300a, FIG. 11) including: a first active region; and a first gate extending over the first active region in a first direction; a second spare cell (300b) including: a second active region; and a second gate extending over the second active region in the first direction; a tie cell (C200, FIG. 7) including: a third active region; a third gate extending over the third active region in the first direction; a first drain contact formed over the third active region; a first source contact formed over the third active region, wherein the third gate is between the first drain contact and the first source contact, and the first source contact is coupled to a first rail (VSS); and a circuit configured to couple the third gate to a second rail (VDD); and a metal routing extending in a second direction, wherein the second direction is perpendicular to the first direction.
Suzuki is silent with respect to “the circuit comprises: a first transistor, wherein a source of the first transistor is coupled to the second rail, and a drain of the first transistor is coupled to the second gate; and a second transistor, wherein a gate of the second transistor is coupled to the gate of the first transistor, a drain of the second transistor is coupled to the gate of the second transistor, and a source of the second transistor is coupled to the first rail” and “the first metal routing is coupled to the first drain contact and the first gate”.
FIG. 2a of Kim discloses a similar chip, comprising a metal routing, wherein the circuit comprises: a first transistor (220), wherein a source (224) of the first transistor is coupled to the second rail (VDD), and a drain of the first transistor is coupled to the second gate; and a second transistor (210), wherein a gate (212) of the second transistor is coupled to the gate (222) of the first transistor, a drain (214) of the second transistor is coupled to the gate of the second transistor, and a source of the second transistor is coupled to the first rail (VSS).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Suzuki, as taught by Kim. The ordinary artisan would have been motivated to modify Suzuki in the above manner for purpose of increasing performance of IC (Abstract of Kim).
Suzuki as modified by Kim is silent with respect to “the metal routing is coupled to the first drain contact and the first gate”.
FIG. 1 of Yousef discloses a similar chip, comprising a metal routing (comprising n1), wherein the metal routing is coupled to the first drain contact (of 24) and the first gate (of 32).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Suzuki, as taught by Yousef. The ordinary artisan would have been motivated to modify Suzuki in the above manner for purpose of making multiple power source devices (Col. 1, Lines 14-33 of Yousef).
Regarding Claim 15
Suzuki discloses the first rail comprises a low rail, the second rail comprises a supply rail (VDD), and the low rail has a lower potential (VSS) than the supply rail.
Regarding Claim 16
Suzuki discloses the first rail comprises a supply rail, the second rail comprises a low rail, and the low rail has a lower potential than the supply rail.
Regarding Claim 17
FIG. 1 of Tsai discloses the metal routing is formed from a metal layer M0.
Regarding Claim 18
FIG. 1 of Tsai discloses the metal routing comprises a metal line formed from the metal layer M0.
Regarding Claim 19
FIG. 1 of Tsai discloses a first via disposed on the first gate; a second via disposed on the second gate; and a third via disposed on the first drain contact, wherein the metal routing extends over the first via, the second via, and the third via.
Regarding Claim 20
FIG. 1 of Tsai discloses the first via, the second via, and the third via are aligned in the first direction.
Regarding Claim 24
FIG. 11 of Suzuki discloses the first spare cell further comprises: a fourth active region, wherein the first gate extends over the fourth active region; a second drain contact formed over the first active region and the fourth active region, wherein the second drain contact extends in the first direction.
Regarding Claim 25
FIG. 11 of Suzuki discloses the first spare cell further comprises: a second source contact formed over the first active region, wherein the first gate is between the second source contact and the second drain contact, and the second source contact is coupled to the second rail; and a third source contact formed over the fourth active region, wherein the first gate is between the third source contact and the second drain contact, and the third source contact is coupled to the first rail.
Regarding Claim 26
FIG. 11 of Suzuki discloses the first active region is a p-type active region, and the fourth active region is an n-type active region.
Regarding Claim 27
Suzuki discloses the first rail comprises a low rail, the second rail comprises a supply rail (VDD), and the low rail has a lower potential (VSS) than the supply rail.
Claims 6 and 7 rejected under 35 U.S.C. 103 as being unpatentable over Suzuki, Kim and Yousef, in view of Subramanian (U.S. Patent Pub. No. 2009/0195289) of record.
Regarding Claim 6
Suzuki as modified by Kim and Yousef discloses Claim 4.
Suzuki as modified by Kim and Yousef is silent with respect to “a first via disposed on the first gate; and a second via disposed on the first drain contact, wherein the metal routing extends over the first via and the second via”.
FIG. 1 of Subramanian discloses a similar chip, comprising a metal routing (26), wherein a first via disposed on the first gate (18a); and a second via disposed on the first drain contact (20b), wherein the metal routing extends over the first via and the second via (Claim 20).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Suzuki, as taught by Subramanian. The ordinary artisan would have been motivated to modify Suzuki in the above manner for purpose of more tolerant of process-induced threshold voltage variations ([0003] of Subramanian).
Regarding Claim 7
FIG. 1 of Subramanian discloses the first via and the second via are aligned in the first direction.
Claims 8 and 9 rejected under 35 U.S.C. 103 as being unpatentable over Suzuki, Kim and Yousef in view of Tsai323 (U.S. Patent Pub. No. 2023/0061323) of record.
Regarding Claim 8
Suzuki as modified Kim and Yousef discloses Claim 1, comprising a metal routing, wherein the first metal routing is coupled to the first drain contact and the first gate.
Suzuki as modified Kim and Yousef is silent with respect to “a dummy gate between the spare cell and the tie cell, wherein the dummy gate extends in the first direction, and the metal routing crosses over the dummy gate”.
FIG. 5 of Tsai323 discloses a similar chip, comprising a dummy gate (500) between the spare cell (212b) and the tie cell (212a), wherein the dummy gate extends in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Suzuki, as taught by Tsai323, such that the metal routing crosses over the dummy gate. The ordinary artisan would have been motivated to modify Suzuki in the above manner for purpose of improving performance and reducing fabrication cost ([0002] of Tsai323).
Regarding Claim 9
Tsai323 discloses the dummy gate comprises a poly over diffusion edge (PODE).
Claims 21-23 rejected under 35 U.S.C. 103 as being unpatentable over Suzuki, Kim and Yousef in view of Yang (U.S. Patent Pub. No. 2014/0239412) of record.
Regarding Claim 21
Suzuki as modified Kim and Yousef discloses Claim 14, comprising a metal routing, wherein the first metal routing is coupled to the first drain contact and the first gate.
Suzuki as modified Kim and Yousef is silent with respect to “a first dummy gate between the tie cell and the first spare cell, wherein the first dummy gate extends in the first direction; a second dummy gate between the tie cell and the second spare cell, wherein the second dummy gate extends in the first direction, and the metal routing crosses over the first dummy gate and the second dummy gate”.
FIG. 1 of Yang discloses a similar chip, comprising a first dummy gate (108/110) between the tie cell (200) and the first spare cell (100), wherein the first dummy gate extends in the first direction; a second dummy gate (208/210) between the tie cell and the second spare cell (300), wherein the second dummy gate extends in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Suzuki, as taught by Yang, such that the metal routing crosses over the first dummy gate and the second dummy gate. The ordinary artisan would have been motivated to modify Suzuki in the above manner for purpose of mitigating signal integrity issues and improving performance.
Regarding Claim 22
Yang discloses the first dummy gate comprises a first poly over diffusion edge (PODE), and the second dummy gate comprises a second PODE [0004].
Regarding Claim 23
FIG. 1 of Yang discloses the first spare cell and the second spare cell are located on opposite sides of the tie cell.
Pertinent Art
Cicalo (U.S. Patent Pub. No. 2014/0332979), Correale (U.S. Patent Pub. No. 2019/0138682), Tsai (U.S. Patent Pub. No. 2009/0249273), Tsai (U.S. Patent Pub. No. 2005/0224950), Fanjoy (U.S. Patent No. 6,801,051) and Schadt (U.S. Patent No. 6,404,226).
Response to Arguments
Applicant’s arguments with respect to Claims 1 and 14 have been considered but they are not persuasive. The Examiner respectfully submits that the first source contact of Suzuki is coupled (via 77 and 79) to a first rail (VSS, FIG. 6); and a circuit configured to couple the second gate (T7) to a second rail (VDD). FIG. 2a of Kim is used to modify the circuit of Suzuki to comprise: a first transistor (220), wherein a source (224) of the first transistor is coupled to the second rail (VDD), and a drain (226) of the first transistor is coupled to the second gate; and a second transistor (210), wherein a gate (212) of the second transistor is coupled to the gate (222) of the first transistor, a drain (214) of the second transistor is coupled to the gate of the second transistor, a source (216) of the second transistor is coupled to the first rail (VSS), and the second gate 212 is coupled to the second rail VDD. Such modification would not render Suzuki inoperable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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