DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 11/29/2025, responding to the Office action mailed on 9/8/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-6 and 8-9, withdrawn claims 10, 14, and 16, and new claim 19 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20160071784 A1), Chang1 hereafter in view of Akiba (US 20180158771 A1).
Re Claim 1 Chang1 teaches a semiconductor structure, comprising:
a substrate (26, [0053]) comprising a first surface (21b) (FIG. 2Q);
a first solder pad located on the first surface (top part of 302, [0062], “conductive via”);
a transferring part (32, 303, and 304) [0062] [0064] located on the first solder pad (top of 302), and comprising a first subpart (303 and 304) covering the first solder pad (top of 302) and a second subpart (32) covering the first subpart (303 and 304), wherein orthographic projections of the first subpart (303 and 304) and the first solder pad (top of 302) on the first surface (21b) fall within an orthographic projection of the second subpart (32) on the first surface (21b); and
a solder ball (33) [0065] located on the second subpart (FIG. 2Q).
The FIG. 2Q fragment below shows how the layers are applied
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Chang1 does not teach transmission lines located on the first surface; and a dielectric layer covering the transmission lines and filling a gap between the first solder pad and the transmission line, wherein a first opening exposing the first solder pad is formed in the dielectric layer, the first subpart is located in the first opening, and the second subpart covers the first subpart and part of the dielectric layer.
Akiba teaches transmission lines (22) [0090] located on the first surface (top of 21c); and a dielectric layer (21) [0091] covering the transmission lines (22) and filling a gap between the first solder pad (35, [0096] “…bump electrodes 35 made of, e.g., a solder.”) and the transmission line (22), wherein a first opening (there is space between 21 and 35 occupied by 25) exposing the first solder pad (22) is formed in the dielectric layer (21), the first subpart (25) [0096] is located in the first opening, and the second subpart (33) [0096] covers the first subpart (25) and part of the dielectric layer (21, FIG. 7).
The ordinary artisan would have been motivated to modify Akiba in combination with Chang1 in the above manner for the motivation of adding a conductive material over the substrate, covering it with a dielectric, and having an opening in the dielectric with allows for interlayer communication and enables the semiconductor structure to function ideally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Akiba into the structure of Chang1.
Re Claim 4 Chang1 in view of Akiba teaches the semiconductor structure of claim 1, wherein a width of the first subpart (Chang1, 303 and 304) gradually increases in a direction perpendicular to the first surface (21b) and from the first solder pad (top of 302) to the second subpart (32, part of the first subpart fits that shape profile).
Re Claim 5 Chang1 in view of Akiba teaches the semiconductor structure of claim 1, further comprising: a composite enhancing layer (Chang1, 302) located between the first subpart (303 ad 304) and the first solder pad (top of 302).
Re Claim 6 Chang1 in view of Akiba teaches the semiconductor structure of claim 1, further comprising: a solderable layer located (Chang1, bottom of 32) between the solder ball (33) and the second subpart (32).
Re Claim 9 Chang1 in view of Akiba teaches a packaging device, comprising: at least one chip (Chang1, 25) [0053], and the semiconductor structure of claim 1, wherein the at least one chip (25) is bonded to the semiconductor structure (FIG. 2H).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chang1 in view of Akiba as applied to claim 1 above, and further in view of Chang (US 20210050309 A1), Chang2 hereafter.
Re Claim 2 Chang1 in view of Akiba teaches the semiconductor structure of claim 1, but does not teach an orthographic projection of the solder ball on the first surface completely coincides with the orthographic projection of the second subpart on the first surface, or the orthographic projection of the solder ball on the first surface falls within the orthographic projection of the second subpart on the first surface.
Chang2 teaches the orthographic projection of the solder ball (130) [0027] on the first surface (use bottom surface of top 100 layer for 1st surface) falls within the orthographic projection of the second subpart (124) [0025] on the first surface (FIG. 3A).
The ordinary artisan would have been motivated to modify Chang2 in combination with Chang1 in view of Akiba in the above manner for the motivation of making the orthographic projection of the solder ball fall within second subpart on the first face. It is critical the solder ball have proper sizing to optimize the current in the semiconductor chip.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chang2 into the structure of Chang1 in view of Akiba.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chang1 in view of Akiba as applied to claim 1 above, and further in view of Lu (US 20190053373 A1).
Re Claim 3 Chang1 in view of Akiba teaches the semiconductor structure of claim 1, but does not teach the orthographic projection of the first subpart on the first surface completely coincides with the orthographic projection of the first solder pad on the first surface, or the orthographic projection of the first subpart on the first surface falls within the orthographic projection of the first solder pad on the first surface.
Lu teaches the orthographic projection of the first subpart (14a) on the first surface (bottom of 11) falls within the orthographic projection of the first solder pad (14b and 14c) on the first surface (bottom of 11, FIG. 1B).
The ordinary artisan would have been motivated to modify Lu in combination with Chang1 in view of Akiba in the above manner for the motivation of having the orthographic projection of the of the first subpart fall within the orthographic projection of the first solder pad because it is more practical to build as stated in paragraphs [0028] and [0029] which allows for an a more efficient device.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Lu into the structure of Chang1 in view of Akiba.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chang1 in view of Akiba as applied to claim 1 above, and further in view of Goh (US 20190103346 A1).
Re Claim 8 Chang1 in view of Akiba teaches the semiconductor structure of claim 1, but does not teach a plurality of second solder pads located on a second surface of the substrate opposite to the first surface, wherein the dielectric layer further fills gaps between the plurality of second solder pads, and a plurality of second openings are formed in the dielectric layer, and wherein the second openings expose the second solder pads.
Goh teaches a plurality of second solder pads (134) located on a second surface (118) [0023] of the substrate (104) [0019] opposite to the first surface (bottom of 104), wherein the dielectric layer (108, [0023 states, “108 can include a mold 132 and at least one through-mold via 134. For instance, the mold 132 can include a polymer or other dielectric material”]) further fills gaps between the plurality of second solder pads (134), and a plurality of second openings are formed in the dielectric layer (108), and wherein the second openings expose the second solder pads (134, FIG. 1).
The ordinary artisan would have been motivated to modify Goh in combination with Chang1 in view of Akiba in the above manner for the motivation of adding solder pads top the top of the substrate. Adding a second plurality of solder pads will allow for the device to send and/or receive signals though a second channel allowing for device function optimization.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Goh into the structure of Chang1 in view of Akiba.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chang1 in view of Akiba as applied to claim 1 above, and further in view of Chen (US 9646894 B2).
Re Claim 19 Chang1 in view of Akiba teaches the semiconductor structure of claim 1, but does not teach a height of the first subpart is greater than a height of the first opening.
Chen teaches a height of the first subpart (501, col 8 line 5) is greater than a height of the first opening (use pocket in 505 that 501 rests, FIG. 5A).
The ordinary artisan would have been motivated to modify Chen in combination with Chang1 in view of Akiba in the above manner for the motivation having the first subpart have a greater height than the first opening to allow for optimal integration as electronic components continue to reduce in size. Col 1 line 21 states, “The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Chang1 in view of Akiba.
Response to Arguments
Applicant's arguments filed 11/29/2025 have been fully considered but they are not persuasive.
Re Claim 7 On page 7 the applicant argues Chang1 fails to disclose at least the recitation of the amended claim 1 below:
"transmission lines located on the first surface and a dielectric layer covering the transmission lines and filling a gap between the first solder pad and the transmission line, wherein a first opening exposing the first solder pad is formed in the dielectric
layer, the first subpart is located in the first opening, and the second subpart covers the first subpart and part of the dielectric layer."
The examiner agrees.
The applicant also argues on page 7, “Secondly, Akiba discloses that the first subpart 23 is a via layer in the insulating layer 21. Akiba fails to disclose there is an opening in the insulating layer 21, so the first subpart cannot locate in the opening. The second subpart doesn't cover the first subpart 23. Therefore, claim 1 is allowable over Chang1 and Akiba.”
The examiner respectfully disagrees. The claim 7 limitation written into claim 1 was remapped with Akiba, considered as a whole, and using bump electrodes 35 made of solder (Akiba [0096] states, “…bump electrodes 35 made of, e.g., a solder.”) as the first solder pad for clarification. The first subpart (25) is located in an opening of between dielectric (21) and 35 in FIG. 7, and the second subpart (33) covers the first subpart (25)in Fig. 7.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/16/26