DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/23/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 18 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 18 recites limitations “the barrier layer covers a bottom surface of the gate insulating layer” that are in contradiction with the independent claim 13. Specifically, claim 13 recites limitations “a lowermost surface of the conductive layer directly contacts the gate insulating layer” that excludes “the barrier layer” between “the conductive layer” and “the gate insulating layer”, wherein “the barrier layer covers a bottom surface of the gate insulating layer” (as recited in claim 18). Thus, claim 18 reciting “the barrier layer covers a bottom surface of the gate insulating layer” fails to include all the limitations of the claim 13 upon which claim 18 depends.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0343846 to Ping et al. (hereinafter Ping) in view of Cho et al. (US 2012/0281484, hereinafter Cho), Miyazaki et al. (US 2014/0284800, hereinafter Miyazaki), and Yang (US Patent No. 11,189,622).
With respect to claims 1 and 2, Ping discloses a semiconductor device (e.g., semiconductor memory device including buried gate) (Ping, Fig. 4g, ¶0002, ¶0005-¶0012, ¶0034-¶0075) comprising:
a substrate (100) (Ping, Figs. 4a, 4g, ¶0034-¶0036) including a trench (101), a source region (e.g., doped active region on one side of the gate structure) (Ping, Fig. 4g, ¶0012, ¶0075), and a drain region (e.g., doped active region on another side of the gate structure), the source region and the drain region spaced apart from each other by the trench (101);
a gate insulating layer (121) (Ping, Figs. 4b, 4g, ¶0043-¶0044) covering a bottom surface of the trench (101) and an inner surface of the trench (101); and
a gate electrode (122/123/124) (Ping, Figs. 4c, 4g, ¶0045-¶0048, ¶0051) in the trench (101),
the gate electrode (122/123/124) including a lower filling portion (123) (Ping, Fig. 4g, ¶0048) and an upper filling portion (124) (Ping, Fig. 4g, ¶0051) surrounded by the gate insulating layer (121), the lower filling portion (123) in the trench (101) and filling a lower region of the trench (101), and the upper filling portion (124) on the lower filling portion (123) and filling an upper region of the trench (101), wherein
the lower filling portion (122/123) (Ping, Fig. 4g, ¶0048) includes a first conductive layer (e.g., 123, good conductivity material including graphene) surrounded by the gate insulating layer (121) and filling the lower region of the trench (101),
the upper filling portion (124) (Ping, Fig. 4g, ¶0051) includes a second conductive layer (e.g., low work function material including Al, Ta, or Zr) surrounded by the gate insulating layer (121) and filling the upper region of the trench (101), and
the first conductive layer (123) includes graphene (Ping, Fig. 4g, ¶0048),
wherein the second conductive layer (124) is selected from the group consisting of Al, Ta,
the second conductive layer (124) is between the source region (e.g., doped active region on one side of the gate structure) and the drain region (e.g., doped active region on another side of the gate structure) in a horizontal direction, the horizontal direction being a direction parallel to an upper surface of the substrate (100), and
the second conductive layer (124) of the upper filling portion is an uppermost conductive layer of the gate electrode (122/123/124) (as claimed in claim 1);
wherein the first conductive layer includes only the graphene (as claimed in claim 2).
Further, Ping does not specifically disclose that (1) graphene doped with metal (as claimed in claim 1 and claim 2), wherein the metal is selected from the group consisting of ruthenium (Ru), titanium (Ti), platinum (Pt), tantalum (Ta), rhodium (Rh), iridium (Ir), cobalt (Co), and tungsten (W) (as claimed in claim 1); (2) the second conductive layer overlapping the source region and the drain region in a horizontal direction (as claimed in claim 1).
Regarding (1), Cho teaches forming a memory device (Cho, Fig. 2A, ¶0009-¶0018, ¶0034-¶0038, ¶0047) having a MOSFET transistor including a doped graphene layer (e.g., P-doped graphene layer) (Cho, Fig. 2A, ¶0037) having a high work function of 5.2 eV or more as a gate electrode, to improve device reliability by the properties of the doped graphene having a high work function that does not cause the deterioration of a lower insulating film against voltage and temperature stress due to its excellent mechanical flexibility (Cho, Fig. 2A, ¶0047).
Further, Miyazaki teaches doping graphene layer (Miyazaki, Fig. 1, ¶0002, ¶0011-¶0028) with a metal comprising at least one of ruthenium (Ru), platinum (Pt), iridium (Ir), and cobalt (Co) (Miyazaki, Fig. 1, ¶0019-¶0020) to increase conductivity of graphene; specifically, an elemental metal such as ruthenium (Ru) or cobalt (Co) can strongly bind to graphene (Miyazaki, Fig. 1, ¶0023), and therefore can modify the band structure and convert semiconductor graphene to metallic graphene.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping by forming a doped graphene as a gate electrode as taught by Cho, wherein the doped graphene is doped with metal materials as taught by Miyazaki to have the semiconductor device comprising: graphene doped with metal (as claimed in claim 1 and claim 2), wherein the graphene doped with metal comprises at least one of ruthenium (Ru), platinum (Pt), iridium (Ir), and cobalt (Co) (as claimed in claim 1), in order to improve device electrical characteristics and reliability by the properties of the doped graphene having a high work function that does not cause the deterioration of a lower insulating film against voltage and temperature stress due to its excellent mechanical flexibility; and to increase conductivity of graphene by modifying the band structure of graphene, and to convert semiconductor graphene to metallic graphene (Cho, ¶0009-¶0011, ¶0037-¶0038, ¶0047; Miyazaki, ¶0002, ¶0019-¶0020, ¶0023, ¶0028).
Regarding (2), Yang teaches forming a semiconductor device (Yang, Fig. 1, Col. 5, lines 45-67; Col. 7, lines 66-67; Col. 8, lines 1-16) comprising the gate electrode (115/117/119) including lower electrode layer (115) and the upper electrode layer (119, the second conductive layer), wherein the upper electrode layer (119) overlapping the source region (105) and the drain region (103) in a horizontal direction, to provide semiconductor device with increased operation speed and improved overall device performance (Yang, Fig. 1, Col. 3, lines 37-42).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping by forming the source and drain regions on sides of the gate electrode as taught by Yang to have the semiconductor device, wherein the second conductive layer overlapping the source region and the drain region in a horizontal direction (as claimed in claim 1), in order to provide semiconductor device with increased operation speed and improved overall device performance (Yang, Col. 3, lines 37-42).
Regarding claim 6, Ping in view of Cho, Miyazaki, and Yang discloses the semiconductor device of claim 1. Further, Ping discloses the semiconductor device, further comprising: a capping layer (e.g., protective layer 130) (Ping, Fig. 4g, ¶0056-¶0059) on the gate electrode (122/123/124).
Regarding claim 7, Ping in view of Cho, Miyazaki, and Yang discloses the semiconductor device of claim 1. Further, Ping discloses that the semiconductor device, wherein the lower filling portion (122/123) further comprises a barrier layer (e.g., 122, TiN) (Ping, Fig. 4g, ¶0045) covering a bottom surface of the gate insulating layer (121) and a lower region of an inner surface of the gate insulating layer (121), and the barrier layer (122) surrounds the first conductive layer (123) in the trench (101).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0343846 to Ping in view of Cho (US 2012/0281484), Miyazaki (US 2014/0284800), and Yang (US Patent No. 11,189,622) as applied to claim 1, and further in view of Huang et al. (US 2017/0263940, hereinafter Huang).
Regarding claim 3, Ping in view of Cho, Miyazaki, and Yang discloses the semiconductor device of claim 1. Further, Ping does not specifically disclose that a ratio of metal to carbon in the graphene doped with metal is 0.2 at% to 50 at%.
However, Huang teaches forming a metal-doped graphene layer (Huang, Fig. 1, ¶0003, ¶0006-¶0011, ¶0025, ¶0044-¶0048) having high conductivity and high specific surface area, and is suitable for an electrode material, wherein the graphene layer is doped with a metal (e.g., Fe or Pd), wherein ratio of metal (102) to the total content of the metal-doped graphene including carbon atoms (100b) is 1 at% to 30 at%. Further, Huang teaches that parameters of the process including a group VI precursor layer (Huang, Fig. 1, ¶0028, ¶0046-¶0047) are adjusted to provide growing graphene and doping at the same time to avoid extra heating.
Thus, Huang recognizes that the doping concentrations of the metal atoms and group VI precursor atoms impact a conductivity of the growing metal-doped graphene layer. Thus, the doping concentrations of the metal atoms and other precursors (e.g., group VI precursor atoms) are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the doping concentrations of the metal atoms and other precursors (e.g., group VI precursor atoms) as Huang has identified the doping concentrations of the metal atoms and other precursors (e.g., group VI precursor atoms) as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific ratio of metal to carbon in the graphene doped with specific metal, e.g., 0.2 at% to 50 at%, in order to provide high conductivity and high specific surface area metal-doped graphene layer suitable for an electrode material and obtained without extra heating as taught by Huang (¶0003, ¶0006-¶0011, ¶0046-¶0047) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Cho/Miyazaki/Yang by optimizing the metal content and other precursors during the growing and doping the metal-doped graphene layer as taught by Huang to have the semiconductor device, wherein a ratio of metal to carbon in the graphene doped with metal is 0.2 at% to 50 at%, in order to provide high conductivity and high specific surface area metal-doped graphene layer suitable for an electrode material and obtained without extra heating (Huang, ¶0003, ¶0006-¶0011, ¶0046-¶0047).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0343846 to Ping in view of Cho (US 2012/0281484), Miyazaki (US 2014/0284800), and Yang (US Patent No. 11,189,622) as applied to claim 1, and further in view of Heo et al. (US 2020/0091306, hereinafter Heo).
Regarding claim 4, Ping in view of Cho, Miyazaki, and Yang discloses the semiconductor device of claim 1. Further, Ping does not specifically disclose that in the graphene doped with metal, a ratio of carbon having an sp2 bond structure to total carbon is 50 % to 99 %, wherein the graphene doped with metal comprises nanocrystalline graphene, and the nanocrystalline graphene comprises crystals each having a size of 0.5 nm to 100 nm.
However, Heo teaches forming a carbon material (Heo, Fig. 1, ¶0003-¶0009, ¶0040-¶0061) having an sp2 bonding structure, and configured as a gate electrode (150) (Heo, Fig. 1, ¶0055), wherein the carbon material having an sp2 bonding structure is nanocrystalline graphene, and wherein the nanocrystalline graphene includes crystals having a size of 0.5 nm to 100 nm (Heo, Fig. 1, ¶0048), and with a ratio of carbon having an sp2 bond structure to total carbon that is 50 % to 99 %, to prevent diffusion of metal into the substrate in a high temperature annealing process, and to provide a semiconductor device with improved performance characteristics and capable of scaling down (Heo, ¶0003-¶0009, ¶0048, ¶0060-¶0061).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Cho/Miyazaki/Yang by forming a graphene layer having an sp2 bonding structure as taught by Heo to have the semiconductor device, wherein in the graphene doped with metal, a ratio of carbon having an sp2 bond structure to total carbon is 50 % to 99 %, wherein the graphene doped with metal comprises nanocrystalline graphene, and the nanocrystalline graphene comprises crystals each having a size of 0.5 nm to 100 nm, in order to prevent diffusion of metal into the substrate in a high temperature annealing process, and to provide a semiconductor device with improved performance characteristics and capable of scaling down (Heo, ¶0003-¶0009, ¶0048, ¶0060-¶0061).
Claims 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0343846 to Ping in view of Cho (US 2012/0281484) and Yang (US Patent No. 11,189,622).
With respect to claim 8, Ping discloses a semiconductor device (e.g., semiconductor memory device including buried gate) (Ping, Fig. 4g, ¶0002, ¶0005-¶0012, ¶0034-¶0075) comprising:
a substrate (100) (Ping, Figs. 4a, 4g, ¶0034-¶0036) including a trench (101), a source region (e.g., doped active region on one side of the gate structure) (Ping, Fig. 4g, ¶0012, ¶0075), and a drain region (e.g., doped active region on another side of the gate structure), the source region and the drain region spaced apart from each other by the trench (101);
a gate insulating layer (121) (Ping, Figs. 4b, 4g, ¶0043-¶0044) covering a bottom surface of the trench (101) and an inner surface of the trench (101); and
a gate electrode (122/123/124) (Ping, Figs. 4c, 4g, ¶0045-¶0048, ¶0051) in the trench (101),
the gate electrode (122/123/124) including a lower filling portion (122/123) (Ping, Fig. 4g, ¶0048) and an upper filling portion (124) (Ping, Fig. 4g, ¶0051) surrounded by the gate insulating layer (121), the lower filling portion (122/123) in the trench (101) and filling a lower region of the trench (101), and the upper filling portion (124) on the lower filling portion (122/123) and filling an upper region of the trench (101), wherein
the lower filling portion (122/123) (Ping, Fig. 4g, ¶0048) includes a first conductive layer (e.g., 123, good conductivity material including graphene) surrounded by the gate insulating layer (121) and filling the lower region of the trench (101),
the upper filling portion (124) (Ping, Fig. 4g, ¶0051) includes a second conductive layer (e.g., low work function material including Al, Ta, or Zr) surrounded by the gate insulating layer (121) and filling the upper region of the trench (101), and
the first conductive layer (123) includes graphene (Ping, Fig. 4g, ¶0048),
wherein the second conductive layer (124) is selected from the group consisting of Al, Ta,
the second conductive layer (124) is between the source region (e.g., doped active region on one side of the gate structure) and the drain region (e.g., doped active region on another side of the gate structure) in a horizontal direction, the horizontal direction being a direction parallel to an upper surface of the substrate (100), and
the second conductive layer (124) of the upper filling portion is an uppermost conductive layer of the gate electrode (122/123/124).
Further, Ping does not specifically disclose that (1) graphene doped with metal; (2) wherein the upper filling portion further comprises a two-dimensional material layer in contact with an upper region of an inner surface of the gate insulating layer, and the two-dimensional material layer surrounds the second conductive layer, and the two-dimensional material layer is above the first conductive layer; (3) the second conductive layer overlapping the source region and the drain region in a horizontal direction.
Regarding (1), Cho teaches forming a memory device (Cho, Fig. 2A, ¶0009-¶0018, ¶0034-¶0038, ¶0047) having a MOSFET transistor including a doped graphene layer (e.g., P-doped graphene layer) (Cho, Fig. 2A, ¶0037) having a high work function of 5.2 eV or more as a gate electrode, to improve device reliability by the properties of the doped graphene having a high work function that does not cause the deterioration of a lower insulating film against voltage and temperature stress due to its excellent mechanical flexibility (Cho, Fig. 2A, ¶0047).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping by forming a doped graphene as a gate electrode as taught by Cho to have the semiconductor device comprising: graphene doped with metal, in order to improve device electrical characteristics and reliability by the properties of the doped graphene having a high work function that does not cause the deterioration of a lower insulating film against voltage and temperature stress due to its excellent mechanical flexibility (Cho, ¶0009-¶0011, ¶0037-¶0038, ¶0047).
Regarding (2), Yang teaches forming a semiconductor device (Yang, Fig. 1, col. 1, lines 46-58; Col. 5, lines 45-67; Col. 7, lines 25-67; Col. 8, lines 1-47) comprising a gate electrode (115/117/119) in the trench (110), the gate electrode includes a graphene layer (117) (Yang, Fig. 1, Col. 7, lines 45-57; Col. 8, lines 17-36) covering an upper region of a sidewall of the gate insulating layer (113) in the trench (110), and a gate electrode (115/119) filling the trench (110), wherein the upper gate filling portion includes a second conductive layer (e.g., 119) being surrounded by the two-dimensional material layer (117), and the graphene layer (117) is above the first conductive layer (115) of the lower gate filling portion, the graphene layer (117) is a low resistance material and is provided to reduce the resistance of the gate structure and to reduce resistive-capacitive (RC) delay of signals transmitted through the conductive layers (Yang, Col. 31-42; Col. 8, lines 34-36) to improve performance of the device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Cho by forming a gate structure including a two-dimensional material layer as taught by Yang to have the semiconductor device, wherein the upper filling portion further comprises a two-dimensional material layer in contact with an upper region of an inner surface of the gate insulating layer, and the two-dimensional material layer surrounds the second conductive layer, and the two-dimensional material layer is above the first conductive layer, in order to reduce the resistance of the gate structure and to reduce resistive-capacitive (RC) delay of signals transmitted through the conductive layers to improve performance of the device (Yang, Col. 1, lines 46-67; Col. 2, lines 1-3; Col. 3, lines 37-42; Col. 8, lines 34-36).
Regarding (3), Yang teaches forming a semiconductor device (Yang, Fig. 1, Col. 5, lines 45-67; Col. 7, lines 66-67; Col. 8, lines 1-16) comprising the gate electrode (115/117/119) including lower electrode layer (115) and the upper electrode layer (119, the second conductive layer), wherein the upper electrode layer (119) overlapping the source region (105) and the drain region (103) in a horizontal direction, to provide semiconductor device with increased operation speed and improved overall device performance (Yang, Fig. 1, Col. 3, lines 37-42).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Cho by forming the source and drain regions on sides of the gate electrode as taught by Yang to have the semiconductor device, wherein the second conductive layer overlapping the source region and the drain region in a horizontal direction, in order to provide semiconductor device with increased operation speed and improved overall device performance (Yang, Col. 3, lines 37-42).
Regarding claim 11, Ping in view of Cho and Yang discloses the semiconductor device of claim 8. Further, Ping does not specifically disclose that the two-dimensional material layer covers an upper surface of the first conductive layer.
However, Yang teaches that the graphene layer (117) (Yang, Fig. 1, Col. 7, lines 45-57; Col. 8, lines 17-36) covers an upper surface of the lower conductive layer (115).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Cho/Yang by forming a gate structure including a two-dimensional material layer as taught by Yang to have the semiconductor device, wherein the two-dimensional material layer covers an upper surface of the first conductive layer, in order to reduce the resistance of the gate structure and to reduce resistive-capacitive (RC) delay of signals transmitted through the conductive layers to improve performance of the device (Yang, Col. 1, lines 46-67; Col. 2, lines 1-3; Col. 3, lines 37-42; Col. 8, lines 34-36).
Claims 9-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0343846 to Ping in view of Cho (US 2012/0281484) and Yang (US Patent No. 11,189,622) as applied to claim 8, and further in view of Lee et al. (US 2016/0343805, hereinafter Lee).
Regarding claim 9, Ping in view of Cho and Yang discloses the semiconductor device of claim 8. Further, Ping does not specifically disclose that the two-dimensional material layer comprises at least one of black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, a transition metal dichalcogenide, titanium oxide (TiOx), niobium oxide (NbOx), manganese oxide (MnOx), vanadium oxide (VOx), manganese trioxide (MnO3), tantalum trioxide (TaO3), tungsten trioxide (WO3), molybdenum dichloride (MoCl2), chromium trichloride (CrCl3), ruthenium trichloride (RuCl3), bismuth triiodide (BiI3), lead tetrachloride (PbCl4), germanium sulfide (GeS), gallium sulfide (GaS), germanium selenide (GeSe), gallium selenide (GaSe), platinum diselenide (PtSe2), diindium triselenide(In2Se3), gallium telluride (GaTe), indium sulfide (InS), indium selenide (InSe), and indium telluride (InTe).
However, Yang teaches forming a gate structure comprising a two-dimensional material layer including carbon-based material (e.g., graphene layer 117) (Yang, Fig. 1, Col. 7, lines 45-57; Col. 8, lines 17-36), to reduce the resistance of the gate structure.
Further, Lee teaches forming a two-dimensional material layer (104/105) (Lee, Fig. 1, ¶0003, ¶0009-¶0015, ¶0051-¶0055, ¶0063-¶0064) comprising a carbon-based 2D material (e.g., graphene) or non-carbon based 2D material including dichalcogenide (TMD), or other 2D materials including hexagonal boron nitride (h-BN), phosphorene, titanium oxide (TiOx), niobium oxide (NbOx), manganese oxide (MnOx), vanadium oxide (VOx), manganese trioxide (MnO3), tantalum trioxide (TaO3), tungsten trioxide (WO3), molybdenum dichloride (MoCl2), chromium trichloride (CrCl3), ruthenium trichloride (RuCl3), bismuth triiodide (BiI3), lead tetrachloride (PbCl4), germanium sulfide (GeS), gallium sulfide (GaS), germanium selenide (GeSe), gallium selenide (GaSe), platinum diselenide (PtSe2), diindium triselenide(In2Se3), gallium telluride (GaTe), indium sulfide (InS), indium selenide (InSe), and indium telluride (InTe). The two-dimensional materials have high thermal stability to improve the durability of the semiconductor device, provide a diffusion barrier between the metal atoms and semiconductor atoms, and reduce resistivity.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Cho/Yang by forming the gate structure including the two-dimensional material layer as taught by Yang, wherein the two-dimensional material includes non-carbon based 2D material as taught by Lee to have the semiconductor device, wherein the two-dimensional material layer comprises at least one of black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, a transition metal dichalcogenide, titanium oxide (TiOx), niobium oxide (NbOx), manganese oxide (MnOx), vanadium oxide (VOx), manganese trioxide (MnO3), tantalum trioxide (TaO3), tungsten trioxide (WO3), molybdenum dichloride (MoCl2), chromium trichloride (CrCl3), ruthenium trichloride (RuCl3), bismuth triiodide (BiI3), lead tetrachloride (PbCl4), germanium sulfide (GeS), gallium sulfide (GaS), germanium selenide (GeSe), gallium selenide (GaSe), platinum diselenide (PtSe2), diindium triselenide(In2Se3), gallium telluride (GaTe), indium sulfide (InS), indium selenide (InSe), and indium telluride (InTe), in order to reduce the resistance of the gate structure; to improve the durability of the semiconductor device and to provide a diffusion barrier between the metal atoms and semiconductor atoms to improve performance of the device (Yang, Col. 1, lines 46-67; Col. 2, lines 1-3; Col. 3, lines 37-42; Col. 8, lines 34-36; Lee, ¶0003, ¶0010-¶0011, ¶0053, ¶0064).
Regarding claim 10, Ping in view of Cho, Yang, and Lee discloses the semiconductor device of claim 9. Further, Ping does not specifically disclose that the transition metal dichalcogenide comprises a metal element and a chalcogen element, the metal element includes one of Mo, W, niobium (Nb), vanadium (V), Ta, Ti, zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), Cu, gallium (Ga), indium (In), tin (Sn), germanium (Ge), and lead (Pb), and the chalcogen element includes one of sulfur (S), selenium (Se), and tellurium (Te).
However, Lee teaches forming a two-dimensional material layer (104/105) (Lee, Fig. 1, ¶0003, ¶0009-¶0015, ¶0051-¶0055, ¶0063-¶0064) comprising non-carbon based 2D material including dichalcogenide (TMD), wherein the transition metal dichalcogenide (Lee, Fig. 1, ¶0053) comprises a metal element and a chalcogen element, the metal element includes one of Mo, W, niobium (Nb), Ta, Ti, hafnium (Hf), rhenium (Re), Cu, gallium (Ga), indium (In), tin (Sn), germanium (Ge), and the chalcogen element includes one of sulfur (S), selenium (Se), and tellurium (Te).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Cho/Yang/Lee by forming the two-dimensional material including non-carbon based 2D material as taught by Lee to have the semiconductor device, wherein the transition metal dichalcogenide comprises a metal element and a chalcogen element, the metal element includes one of Mo, W, niobium (Nb), Ta, Ti, hafnium (Hf), rhenium (Re), Cu, gallium (Ga), indium (In), tin (Sn), germanium (Ge), and the chalcogen element includes one of sulfur (S), selenium (Se), and tellurium (Te), in order to improve the durability of the semiconductor device and to provide a diffusion barrier between the metal atoms and semiconductor atoms to improve performance of the device (Lee, ¶0003, ¶0010-¶0011, ¶0053, ¶0064).
Regarding claim 12, Ping in view of Cho and Yang discloses the semiconductor device of claim 8. Further, Ping does not specifically disclose that the two-dimensional material layer has a thickness of 0.3 nm to 5 nm.
However, Yang teaches forming a gate structure comprising a two-dimensional material layer including carbon-based material (e.g., graphene layer 117) (Yang, Fig. 1, Col. 7, lines 45-57; Col. 8, lines 17-36), to reduce the resistance of the gate structure.
Further, Lee teaches forming a two-dimensional material layer (104/105) (Lee, Fig. 1, ¶0003, ¶0009-¶0015, ¶0051-¶0055, ¶0063-¶0064) comprising a carbon-based 2D material (e.g., graphene) or non-carbon based 2D material including dichalcogenide (TMD), or other 2D materials, wherein the two-dimensional material has high thermal stability to improve the durability of the semiconductor device, provides a diffusion barrier between the metal atoms and semiconductor atoms, and reduces resistivity. The two-dimensional material layer (104/105) has a thickness in a rnage between 0.3 nm and 5 nm (Lee, Fig. 1, ¶0063).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Cho/Yang by forming the gate structure including the two-dimensional material layer as taught by Yang, wherein the two-dimensional material includes non-carbon based 2D material as taught by Lee to have the semiconductor device, wherein the two-dimensional material layer has a thickness of 0.3 nm to 5 nm, in order to reduce the resistance of the gate structure; to improve the durability of the semiconductor device and to provide a diffusion barrier between the metal atoms and semiconductor atoms to improve performance of the device (Yang, Col. 1, lines 46-67; Col. 2, lines 1-3; Col. 3, lines 37-42; Col. 8, lines 34-36; Lee, ¶0003, ¶0010-¶0011, ¶0053, ¶0064).
Claims 13, 17, and 18 rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0343846 to Ping in view of Yang (US Patent No. 11,189,622), Cho (US 2012/0281484), Miyazaki (US 2014/0284800), and Fujimoto (US 2016/0027785).
With respect to claim 13, Ping discloses a semiconductor device (e.g., semiconductor memory device including buried gate) (Ping, Fig. 4g, ¶0002, ¶0005-¶0012, ¶0034-¶0075) comprising:
a substrate (100) (Ping, Figs. 4a, 4g, ¶0034-¶0036) including a trench (101), a source region (e.g., doped active region on one side of the gate structure) (Ping, Fig. 4g, ¶0012, ¶0075), and a drain region (e.g., doped active region on another side of the gate structure), the source region and the drain region spaced apart from each other by the trench (101);
a gate insulating layer (121) (Ping, Figs. 4b, 4g, ¶0043-¶0044) covering a bottom surface of the trench (101) and an inner surface of the trench (101); and
a gate electrode (122/123/124) (Ping, Figs. 4c, 4g, ¶0045-¶0048, ¶0051) in the trench (101),
wherein the gate electrode (122/123/124) includes a conductive layer (123) (Ping, Fig. 4g, ¶0048), and the conductive layer (123) filling the trench (101) and being surrounded by the gate insulating layer (121),
wherein the conductive layer (123) is a single material consisting of graphene (Ping, Fig. 4g, ¶0048),
wherein the second conductive layer (124) is selected from the group consisting of Al, Ta,
the conductive layer (123) is between the source region (e.g., doped active region on one side of the gate structure) and the drain region (e.g., doped active region on another side of the gate structure) in a horizontal direction, the horizontal direction being a direction parallel to an upper surface of the substrate (100).
Further, Ping does not specifically disclose that (1) a two-dimensional material layer, the two-dimensional material layer covering an upper region of a sidewall of the gate insulating layer in the trench, and the conductive layer being surrounded by the two-dimensional material layer, (2) graphene doped with metal, wherein the metal is selected from the group consisting of ruthenium (Ru), titanium (Ti), platinum (Pt), tantalum (Ta), rhodium (Rh), iridium (Ir), cobalt (Co), and tungsten (W); (3) the upper portion of the conductive layer is between the source region and the drain region in a horizontal direction, and lowermost surface of the conductive layer directly contacts the gate insulating layer.
Regarding (1), Yang teaches forming a semiconductor device (Yang, Fig. 1, col. 1, lines 46-58; Col. 5, lines 45-67; Col. 7, lines 25-67; Col. 8, lines 1-47) comprising a gate electrode (115/117/119) in the trench (110), the gate electrode includes a graphene layer (117) (Yang, Fig. 1, Col. 7, lines 45-57; Col. 8, lines 17-36) covering an upper region of a sidewall of the gate insulating layer (113) in the trench (110), and a conductive layer (115/119) filling the trench (110) and the conductive layer (e.g., 119) being surrounded by the two-dimensional material layer (117), the graphene layer (117) is a low resistance material and is provided to reduce the resistance of the gate structure and to reduce resistive-capacitive (RC) delay of signals transmitted through the conductive layers (Yang, Col. 31-42; Col. 8, lines 34-36) to improve performance of the device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping by forming a gate structure including a two-dimensional material layer as taught by Yang to have the semiconductor device comprising: a two-dimensional material layer, the two-dimensional material layer covering an upper region of a sidewall of the gate insulating layer in the trench, and the conductive layer being surrounded by the two-dimensional material layer, in order to reduce the resistance of the gate structure and to reduce resistive-capacitive (RC) delay of signals transmitted through the conductive layers to improve performance of the device (Yang, Col. 3, lines 37-42; Col. 8, lines 34-36).
Regarding (2), Cho teaches forming a memory device (Cho, Fig. 2A, ¶0009-¶0018, ¶0034-¶0038, ¶0047) having a MOSFET transistor including a doped graphene layer (e.g., P-doped graphene layer) (Cho, Fig. 2A, ¶0037) having a high work function of 5.2 eV or more as a gate electrode, to improve device reliability by the properties of the doped graphene having a high work function that does not cause the deterioration of a lower insulating film against voltage and temperature stress due to its excellent mechanical flexibility (Cho, Fig. 2A, ¶0047).
Further, Miyazaki teaches doping graphene layer (Miyazaki, Fig. 1, ¶0002, ¶0011-¶0028) with a metal comprising at least one of ruthenium (Ru), platinum (Pt), iridium (Ir), and cobalt (Co) (Miyazaki, Fig. 1, ¶0019-¶0020) to increase conductivity of graphene; specifically, an elemental metal such as ruthenium (Ru) or cobalt (Co) can strongly bind to graphene (Miyazaki, Fig. 1, ¶0023), and therefore can modify the band structure and convert semiconductor graphene to metallic graphene.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping by forming a doped graphene as a gate electrode as taught by Cho, wherein the doped graphene is doped with metal materials as taught by Miyazaki to have the semiconductor device comprising: graphene doped with metal (as claimed in claim 1 and claim 2), wherein the graphene doped with metal comprises at least one of ruthenium (Ru), platinum (Pt), iridium (Ir), and cobalt (Co) (as claimed in claim 1), in order to improve device electrical characteristics and reliability by the properties of the doped graphene having a high work function that does not cause the deterioration of a lower insulating film against voltage and temperature stress due to its excellent mechanical flexibility; and to increase conductivity of graphene by modifying the band structure of graphene, and to convert semiconductor graphene to metallic graphene (Cho, ¶0009-¶0011, ¶0037-¶0038, ¶0047; Miyazaki, ¶0002, ¶0019-¶0020, ¶0023, ¶0028).
Regarding (3), Fujimoto teaches forming a semiconductor device (Fujimoto, Fig. 1, ¶0040-¶0043) comprising the gate electrode (17) including a conductive layer filled in the trench (15) and surrounded by the gate insulating layer (16), wherein the upper portion of the conductive layer (17) is between the source region (13) (Fujimoto, Fig. 1, ¶0043) and the drain region (13) in a horizontal direction, and lowermost surface of the conductive layer (17) directly contacts the gate insulating layer (16), to provide semiconductor device including memory cell with embedded gate electrode to reduce dimensions of the memory cell (Fujimoto, Fig. 1, ¶0038, ¶0040-¶0041).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping by forming the embedded gate electrode and the source and drain regions on sides of the embedded gate electrode as taught by Fujimoto to have the semiconductor device, wherein the upper portion of the conductive layer is between the source region and the drain region in a horizontal direction, and lowermost surface of the conductive layer directly contacts the gate insulating layer, in order to provide semiconductor device including memory cell with embedded gate electrode to reduce dimensions of the memory cell (Fujimoto, ¶0002, ¶0038, ¶0040-¶0041).
Regarding claim 17, Ping in view of Yang, Cho, Miyazaki, and Fujimoto discloses the semiconductor device of claim 13. Further, Ping discloses the semiconductor device, further comprising: a capping layer (e.g., protective layer 130) (Ping, Fig. 4g, ¶0056-¶0059) on the gate electrode (122/123/124).
Regarding claim 18, Ping in view of Yang, Cho, Miyazaki, and Fujimoto discloses the semiconductor device of claim 13. Further, Ping discloses that the semiconductor device, wherein the gate electrode (122/123) further comprises a barrier layer (e.g., 122, TiN) (Ping, Fig. 4g, ¶0045), and the barrier layer covers a bottom surface of the gate insulating layer (121) and a lower region of an inner surface of the gate insulating layer (121) in the trench (101).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0343846 to Ping in view of Yang (US Patent No. 11,189,622), Cho (US 2012/0281484), Miyazaki (US 2014/0284800), and Fujimoto (US 2016/0027785) as applied to claim 13, and further in view of Huang (US 2017/0263940).
Regarding claim 15, Ping in view of Yang, Cho, Miyazaki, and Fujimoto discloses the semiconductor device of claim 13. Further, Ping does not specifically disclose that in the graphene doped with metal, a ratio of metal to carbon is 0.2 at% to 50 at%.
However, Huang teaches forming a metal-doped graphene layer (Huang, Fig. 1, ¶0003, ¶0006-¶0011, ¶0025, ¶0044-¶0048) having high conductivity and high specific surface area, and is suitable for an electrode material, wherein the graphene layer is doped with a metal comprising aluminum (Al), wherein ratio of metal (102) to the total content of the metal-doped graphene including carbon atoms (100b) is 1 at% to 30 at%. Further, Huang teaches that parameters of the process including a group VI precursor layer (Huang, Fig. 1, ¶0028, ¶0046-¶0047) are adjusted to provide growing graphene and doping at the same time to avoid extra heating.
Thus, Huang recognizes that the doping concentrations of the metal atoms and group VI precursor atoms impact a conductivity of the growing metal-doped graphene layer. Thus, the doping concentrations of the metal atoms and other precursors (e.g., group VI precursor atoms) are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the doping concentrations of the metal atoms and other precursors (e.g., group VI precursor atoms) as Huang has identified the doping concentrations of the metal atoms and other precursors (e.g., group VI precursor atoms) as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific ratio of metal to carbon in the graphene doped with specific metal, e.g., 0.2 at% to 50 at%, in order to provide high conductivity and high specific surface area metal-doped graphene layer suitable for an electrode material and obtained without extra heating as taught by Huang (¶0003, ¶0006-¶0011, ¶0046-¶0047) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Yang/Cho/Miyazaki/ Fujimoto by optimizing the metal content and other precursors during the growing and doping the metal-doped graphene layer as taught by Huang to have the semiconductor device, wherein in the graphene doped with metal, a ratio of metal to carbon is 0.2 at% to 50 at%, in order to provide high conductivity and high specific surface area metal-doped graphene layer suitable for an electrode material and obtained without extra heating (Huang, ¶0003, ¶0006-¶0011, ¶0046-¶0047).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0343846 to Ping in view of Yang (US Patent No. 11,189,622), Cho (US 2012/0281484), Miyazaki (US 2014/0284800), and Fujimoto (US 2016/0027785) as applied to claim 13, and further in view of Heo (US 2020/0091306).
Regarding claim 16, Ping in view of Yang, Cho, Miyazaki, and Fujimoto discloses the semiconductor device of claim 13. Further, Ping does not specifically disclose that in the graphene doped with metal, a ratio of carbon having an sp2 bond structure to total carbon is 50 % to 99 %, wherein the graphene doped with metal comprises nanocrystalline graphene, and the nanocrystalline graphene comprises crystals each having a size of 0.5 nm to 100 nm.
However, Heo teaches forming a carbon material (Heo, Fig. 1, ¶0003-¶0009, ¶0040-¶0061) having an sp2 bonding structure, and configured as a gate electrode (150) (Heo, Fig. 1, ¶0055), wherein the carbon material having an sp2 bonding structure is nanocrystalline graphene, and wherein the nanocrystalline graphene includes crystals having a size of 0.5 nm to 100 nm (Heo, Fig. 1, ¶0048), and with a ratio of carbon having an sp2 bond structure to total carbon that is 50 % to 99 %, to prevent diffusion of metal into the substrate in a high temperature annealing process, and to provide a semiconductor device with improved performance characteristics and capable of scaling down (Heo, ¶0003-¶0009, ¶0048, ¶0060-¶0061).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Yang/Cho/Miyazaki/ Fujimoto by forming a graphene layer having an sp2 bonding structure as taught by Heo to have the semiconductor device, wherein in the graphene doped with metal, a ratio of carbon having an sp2 bond structure to total carbon is 50 % to 99 %, wherein the graphene doped with metal comprises nanocrystalline graphene, and the nanocrystalline graphene comprises crystals each having a size of 0.5 nm to 100 nm, in order to prevent diffusion of metal into the substrate in a high temperature annealing process, and to provide a semiconductor device with improved performance characteristics and capable of scaling down (Heo, ¶0003-¶0009, ¶0048, ¶0060-¶0061).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0343846 to Ping in view of Yang (US Patent No. 11,189,622), Cho (US 2012/0281484), Miyazaki (US 2014/0284800), and Fujimoto (US 2016/0027785) as applied to claim 13, and further in view of Lee (US 2016/0343805).
Regarding claim 19, Ping in view of Yang, Cho, Miyazaki, and Fujimoto discloses the semiconductor device of claim 13. Further, Ping does not specifically disclose that the two-dimensional material layer comprises at least one of black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, a transition metal dichalcogenide, titanium oxide (TiOx), niobium oxide (NbOx), manganese oxide (MnOx), vanadium oxide (VOx), manganese trioxide (MnO3), tantalum trioxide (TaO3), tungsten trioxide (WO3), molybdenum dichloride (MoCl2), chromium trichloride (CrCl3), ruthenium trichloride (RuCl3), bismuth triiodide (BiI3), lead tetrachloride (PbCl4), germanium sulfide (GeS), gallium sulfide (GaS), germanium selenide (GeSe), gallium selenide (GaSe), platinum diselenide (PtSe2), diindium triselenide(In2Se3), gallium telluride (GaTe), indium sulfide (InS), indium selenide (InSe), and indium telluride (InTe).
However, Yang teaches forming a gate structure comprising a two-dimensional material layer including carbon-based material (e.g., graphene layer 117) (Yang, Fig. 1, Col. 7, lines 45-57; Col. 8, lines 17-36), to reduce the resistance of the gate structure.
Further, Lee teaches forming a two-dimensional material layer (104/105) (Lee, Fig. 1, ¶0003, ¶0009-¶0015, ¶0051-¶0055, ¶0063-¶0064) comprising a carbon-based 2D material (e.g., graphene) or non-carbon based 2D material including dichalcogenide (TMD), or other 2D materials including hexagonal boron nitride (h-BN), phosphorene, titanium oxide (TiOx), niobium oxide (NbOx), manganese oxide (MnOx), vanadium oxide (VOx), manganese trioxide (MnO3), tantalum trioxide (TaO3), tungsten trioxide (WO3), molybdenum dichloride (MoCl2), chromium trichloride (CrCl3), ruthenium trichloride (RuCl3), bismuth triiodide (BiI3), lead tetrachloride (PbCl4), germanium sulfide (GeS), gallium sulfide (GaS), germanium selenide (GeSe), gallium selenide (GaSe), platinum diselenide (PtSe2), diindium triselenide(In2Se3), gallium telluride (GaTe), indium sulfide (InS), indium selenide (InSe), and indium telluride (InTe). The two-dimensional materials have high thermal stability to improve the durability of the semiconductor device, provide a diffusion barrier between the metal atoms and semiconductor atoms, and reduce resistivity.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Yang/Cho/Miyazaki/ Fujimoto by forming the gate structure including the two-dimensional material layer as taught by Yang, wherein the two-dimensional material includes non-carbon based 2D material as taught by Lee to have the semiconductor device, wherein the two-dimensional material layer comprises at least one of black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, a transition metal dichalcogenide, titanium oxide (TiOx), niobium oxide (NbOx), manganese oxide (MnOx), vanadium oxide (VOx), manganese trioxide (MnO3), tantalum trioxide (TaO3), tungsten trioxide (WO3), molybdenum dichloride (MoCl2), chromium trichloride (CrCl3), ruthenium trichloride (RuCl3), bismuth triiodide (BiI3), lead tetrachloride (PbCl4), germanium sulfide (GeS), gallium sulfide (GaS), germanium selenide (GeSe), gallium selenide (GaSe), platinum diselenide (PtSe2), diindium triselenide(In2Se3), gallium telluride (GaTe), indium sulfide (InS), indium selenide (InSe), and indium telluride (InTe), in order to reduce the resistance of the gate structure; to improve the durability of the semiconductor device and to provide a diffusion barrier between the metal atoms and semiconductor atoms to improve performance of the device (Yang, Col. 1, lines 46-67; Col. 2, lines 1-3; Col. 3, lines 37-42; Col. 8, lines 34-36; Lee, ¶0003, ¶0010-¶0011, ¶0053, ¶0064).
Regarding claim 20, Ping in view of Yang, Cho, Miyazaki, Fujimoto, and Lee discloses the semiconductor device of claim 19. Further, Ping does not specifically disclose that the transition metal dichalcogenide comprises a metal element and a chalcogen element, the metal element includes one of Mo, W, niobium (Nb), vanadium (V), Ta, Ti, zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), Cu, gallium (Ga), indium (In), tin (Sn), germanium (Ge), and lead (Pb), and the chalcogen element includes one of sulfur (S), selenium (Se), and tellurium (Te).
However, Lee teaches forming a two-dimensional material layer (104/105) (Lee, Fig. 1, ¶0003, ¶0009-¶0015, ¶0051-¶0055, ¶0063-¶0064) comprising non-carbon based 2D material including dichalcogenide (TMD), wherein the transition metal dichalcogenide (Lee, Fig. 1, ¶0053) comprises a metal element and a chalcogen element, the metal element includes one of Mo, W, niobium (Nb), Ta, Ti, hafnium (Hf), rhenium (Re), Cu, gallium (Ga), indium (In), tin (Sn), germanium (Ge), and the chalcogen element includes one of sulfur (S), selenium (Se), and tellurium (Te).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Ping/Yang/Cho/Miyazaki/ Fujimoto/Lee by forming the two-dimensional material including non-carbon based 2D material as taught by Lee to have the semiconductor device, wherein the transition metal dichalcogenide comprises a metal element and a chalcogen element, the metal element includes one of Mo, W, niobium (Nb), Ta, Ti, hafnium (Hf), rhenium (Re), Cu, gallium (Ga), indium (In), tin (Sn), germanium (Ge), and the chalcogen element includes one of sulfur (S), selenium (Se), and tellurium (Te), in order to improve the durability of the semiconductor device and to provide a diffusion barrier between the metal atoms and semiconductor atoms to improve performance of the device (Lee, ¶0003, ¶0010-¶0011, ¶0053, ¶0064).
Response to Arguments
Applicant’s arguments with respect to claims 1-4, 6-13, and 15-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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