Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/08/2026 has been entered.
Response to Arguments
Applicant's arguments filed June 8, 2026 have been fully considered but they are not persuasive. Claim 34, was indicated allowable based on all its dependencies being put in independent form, but Applicant did not incorporate all limitations into the independent claim, therefore, upon further search and consideration, all claims were not considered allowable (also note independent claims 1 and 17 did not have the limitations of claim 34 in any of their dependents, so the combination had to be evaluated). This is seen in the new rejection below with some claims being indicated as allowable.
Allowable Subject Matter
Claims 1-3, 5-6, 8-15 are allowed. In particular, claim 1, contains the following combination of limitations that put it in a state of allowance: “a third thin film transistor in the display area, the third thin film transistor comprising a third semiconductor pattern including an oxide semiconductor patter, a third gate electrode, a third source electrode, and a third drain electrode” with “a second light shield pattern overlapping the third semiconductor pattern” and “wherein a vertical distance between the second semiconductor pattern and the first light shield pattern is less than a vertical distance between the third semiconductor pattern and the second light shield pattern.” In particular, the combination, with the other limitations of claim 1, of a third transistor with two light shielding patterns situated in a specific area in a display and non-display area overcomes the combinations of Maruyama (US 20170278916), Park et al (20220013549), Lee et al (US 2022013619) and Baeck et al (US 20200176603). Though Lee et al (US 20230189569) does disclose two light blocking layers, it does not disclose three transistors in such an arrangement that one of the second light shield pattern overlaps a third semiconductor pattern and the first light shield pattern overlaps the second semiconductor pattern with said first light shield pattern connected to the second source electrode. To modified Park et al as modified to incorporate two light blocking layers with would have no motivation to do so, nor would it be physically possible given the disclosures. Additionally, said limitations in combination with the newly amended limitation “wherein a vertical distance between the second semiconductor pattern and the first light shield pattern is less than a vertical distance between the third semiconductor pattern and the second light shield pattern.” Thus, claim 1 is in a state of allowance. Additionally, dependent claims 2-3, 5-6 and 8-15 upon independent claim 1 further limit allowable independent claim 1 and thus are in a state of allowance.
Claims 28-33 are objected to and if written in independent form would be in a state of allowance. In particular, previous claim 34 was objected to if written in independent form, including all of the limitations of claim 28 and 25. Amended claim 25, contains the limitations of previous claim 34 and some of previous claim 28 but not all of the limitations and thus does not contain all of the limitations of previous claim 34 if written in independent form. Current claim 28, if written in independent form would contain all of the limitations of previous objected claim 34 if written in independent form, thus amended claim 28 (current claim 28) is now objected, and all claims that depend upon claim 28, specifically claims 29-33.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-22 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 20220013549 A1) in view of Koo (US 20200403011 A1), Lee et al (US 20220013619), and Kanegae et al (US 20140048807 A1).
Park et al teaches
[claim 17] An organic light emitting display device comprising: a substrate on which a display area and a non-display area located outside of the display area are disposed (paragraph 0039, where the display area contains the transistors in the enclosure, and the non-display area is outside the display area);
a first thin film transistor disposed in the display area, and comprising a first semiconductor pattern comprising, a first conductive pattern, a first gate electrode, a first source electrode, and a first drain electrode (figure 4, paragraphs 0064, 0092-0095, where the first conductive pattern is elements CT2 and CT3, the first semiconductor pattern is element ACT1, the first gate electrode is element G1, first source electrode is element S1 and the first drain electrode is element D1);
a second thin film transistor disposed in the display area, and comprising a second semiconductor pattern comprising, a second conductive pattern, a second gate electrode, and a second source electrode, and a second drain electrode (figure 4, paragraphs 0064, 0092-0095, where the second conductive pattern is elements CT4 and CT5, the second semiconductor pattern is element ACT2, the second gate electrode is element G2, second source electrode is element S2 and the second drain electrode is element D2);
a first light shield pattern located under, and overlapping, the first semiconductor pattern such that the first light shield pattern is closer to the substrate than the first semiconductor pattern (figure 5, paragraph 0066, where element BML is the first light shield pattern and overlaps the first semiconductor pattern [element ACT1] and is situated under the first semiconductor pattern, and closer to the substrate [element SUB] than the first semiconductor pattern is);
wherein the first light shield pattern overlaps the first thin film transistor (figure 4, paragraph 0065 and 0066, where the light shielding/blocking layer is BML an overlaps the first thin film transistor [of which element ACT1 is the semiconductor portion of the first transistor]),
However, Park et al does not specifically disclose
[claim 17] and a second light shield pattern overlapping the second semiconductor pattern, wherein a vertical distance between the first semiconductor pattern and the first light shield pattern is less than a vertical distance between the second semiconductor pattern and the second light shield pattern, wherein the first semiconductor pattern comprises a first channel region, a first source region, and a first drain region such that the first channel region is interposed between the first source region and the first drain region,wherein the second semiconductor pattern comprises a second channel region, a second source region, and a second drain region such that the second channel region is interposed between the second source region and the second drain region, wherein the first conductive pattern is in contact with upper surfaces both of the first source region and the first drain region, and the second conductive pattern is in contact with upper surfaces both of the second source region and the second drain region, and wherein the first source region and the first drain region and the second source region and the second drain region are intrinsic semiconductor patterns in which an impurity ion is not doped, wherein the second light shield pattern overlaps the second thin film transistor.
However, Koo does teach
[claim 17] and a second light shield pattern overlapping the second semiconductor pattern (figure 14, paragraph 0074, where element 210 is the second light shield pattern which replaces the element G2 of the primary [Park et al, figure 4] reference [note the gate electrode is serving a dual function]),
Wherein the second light shield pattern overlaps the second thin film transistor (figure 14, paragraph 0074 where element 210 is the second light shield pattern which overlaps the second thin film transistor [element 20]),
wherein a vertical distance between the first semiconductor pattern and the first light shield pattern is less than a vertical distance between the second semiconductor pattern and the second light shield pattern (figure 14, paragraph 0074 and figure 4 of the primary [Park et al] reference, where element 210 of the secondary [Koo] reference replaces element G2 of the primary reference [figure 4, Park et al], when looking at the primary reference element G2 is located closer to the second semiconductor pattern [ACT2] than the first light shield layer is to the first semiconductor pattern [element BML is the light shield layer and element ACT1 is the first semiconductor pattern]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Park et al with the teachings of Koo in order to maximize space while creating a more efficient device by blocking more incident light while adding no new structure by making the gate electrode both a gate electrode and light shielding layer.
Additionally, Park et al as modified does not specifically disclose
[claim 17] wherein the first semiconductor pattern comprises a first channel region, a first source region, and a first drain region such that the first channel region is interposed between the first source region and the first drain region, wherein the second semiconductor pattern comprises a second channel region, a second source region, and a second drain region such that the second channel region is interposed between the second source region and the second drain region, wherein the conductive pattern is in contact with upper surfaces of both the first source region and the first drain region, and/or with upper surfaces of both the second source region and the second drain region, and wherein upper surfaces of the first source region and the first drain region and/or upper surfaces of the second source region and the second drain region, and wherein the first source region and the first drain region and the second source region and the second drain region are intrinsic semiconductor patterns in which an impurity ion is not doped.
However, Lee et al does teach
[claim 17] wherein the first semiconductor pattern comprises a first channel region, a first source region, and a first drain region such that the first channel region is interposed between the first source region and the first drain region (figure 11, paragraphs 0115-0116, where element ST1 is the first semiconductor pattern [S1, AC1 and D1 specifically], and the first region is AC1, the first source region is S1, and the first drain region is D1, and the channel region is interposed between the first source and first drain region),
wherein the second semiconductor pattern comprises a second channel region, a second source region, and a second drain region such that the second channel region is interposed between the second source region and the second drain region (figure 11, paragraph 0119, where ST3 is the second semiconductor pattern [specifically S3, D3, and ACT3] where the source region is S3, the drain region is D3 and the channel region is ACT3 and the channel reigon is interposed between the source and drain region),
wherein the conductive pattern is in contact with upper surfaces of both the first source region and the first drain region, and/or with upper surfaces of both the second source region and the second drain region, and wherein upper surfaces of the first source region and the first drain region and/or upper surfaces of the second source region and the second drain region (figure 11, paragraph 0164, where elements CNT4 and CNT3 comprise the conductive pattern and are filled in such that they contact the top layer of the first source/drain region [ST1] and the top layer of the second source/drain region [ST3]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Park et al as modified to incorporate the teachings of Lee et al in order to provide contacts between the first and second semiconductor regions to turn the semiconductors on using one conductive pattern instead of multiple, thus maximizing efficiency of the device (in particular, efficiency of materials used).
However, Park et al as modified does not specifically disclose
[claim 17] and wherein the first source region and the first drain region and the second source region and the second drain region are intrinsic semiconductor patterns in which an impurity ion is not doped.
However, Kanegae et al does teach
[claim 17] and wherein the first source region and the first drain region and the second source region and the second drain region are intrinsic semiconductor patterns in which an impurity ion is not doped (paragraph 0048, where the semiconductor layer for both the first and second semiconductor layers are intrinsic and no impurity ion is doped).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Park et al as modified to incorporate the teachings of Kanegae et al to use an intrinsic semiconductor layer for both semiconductor layers in order to provide more electrical stability for the devices as intrinsic semiconductor layers are known to be more stable than doped layers.
Regarding claims 18-22
Park et al further teaches
[claim 18] The organic light emitting display device according to claim 17, wherein the conductive pattern is on respective upper surfaces of the first semiconductor pattern and the second semiconductor pattern (figure 4, paragraphs 0092-0095 where elements CT2 and CT3 [first conductive pattern] is on an upper surface of the first semiconductor pattern [element ACT1], and the second conductive pattern [elements CT4 and CT5] are on an upper surface of the second semiconductor pattern [ACT2]).
[claim 19] The organic light emitting display device according to claim 17, wherein the first semiconductor pattern and the second semiconductor pattern each comprise an oxide semiconductor pattern (paragraph 0061, where the active regions of both the first and second semiconductor pattern [linked to T1 and T2 respectively] are made of an oxide semiconductor material).
[claim 20] The organic light emitting display device according to claim 17, wherein the first light shield pattern is connected to the first source electrode (figure 4, where element BML [first light shielding layer] is connected to the first source electrode [element S1] via element CT1).
[claim 21] The organic light emitting display device according to claim 17, wherein the first gate electrode, the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the second drain electrode are in a same layer (figure 4, where the first gate electrode [element G1], source electrode [element S1], drain electrode [element D1], second gate electrode [element G2], second source electrode [element S2], second drain electrode [element D2] all reside within layer 140, thus being in the same layer).
[claim 22] The organic light emitting display device according to claim 17, further comprising: a storage capacitor comprising one electrode in a same layer as the first semiconductor pattern and the first conductive pattern (figure 4, paragraph 0054, where the storage capacitor [Cst] has one electrode as the first gate electrode [element G1] in element T1, thus putting the capacitor in the same layer as the first semiconductor pattern and conductive pattern [layer 140]).
Claim(s) 25-27 rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 20220013549 A1) in view of Kanegae et al (US 20140048807 A1) and Koo (US 20200403011 A1).
Park et al teaches
[claim 25] A light emitting display device comprising: a substrate including a display area and a non-display area around the display area (paragraph 0039, where the display area contains the transistors in the enclosure, and the non-display area is outside the display area);
a first thin film transistor in the display area, the first thin film transistor including a first drain electrode, a first source electrode, a first gate electrode, and a first semiconductor pattern having a first channel region, a first source region at a first end of the first channel region, and a first drain region at a second end of the first channel region that is opposite the first end (figure 4, paragraphs 0064, 0092-0095, where transistor T1 is the first thin film transistor in the display area, and consists of a first semiconductor pattern [element ACT1] with a first channel region CH1, a first source region on one end labeled SP1, a first drain region opposite end of the first source region labeled D1, a first source electrode labeled S1, first gate electrode G1, and first drain electrode D1);
a second thin film transistor in the display area, the second thin film transistor including a second drain electrode, a second source electrode, a second gate electrode, and a second semiconductor pattern having a second channel region, a second source region at a first end of the second channel region, and a second drain region at a second end of the second channel region that is opposite the first end of the second channel region(figure 4, paragraphs 0064, 0092-0095, where transistor T3 is the second thin film transistor in the display area, and consists of a second semiconductor pattern [element ACT2] with a second channel region CH2, a second source region on one end labeled SP2, a second drain region opposite end of the first source region labeled D2, a second source electrode labeled S2, second gate electrode G2, and second drain electrode D2);
a first conductive pattern on the first semiconductor pattern, the first conductive pattern including a first conductive portion that is in contact with and overlaps an upper surface of the first source region and a second conductive portion that is in contact with and overlaps an upper surface of the second source region (figure 4, paragraphs 0064, 0092-0095, where the first conductive pattern is elements CT2 and CT3 located on the first semiconductor pattern [ACT1] where element CT2 of the first conductive pattern is in contact with the first source region SP1 and is the first conductive portion, and element CT3 of the first conductive pattern is in contact with the first drain region DP1 and is the second conductive portion in contact with the drain region and each overlaps an upper service of the respective region);
and a light emitting element configured to emit light, the light emitting element connected to the first thin film transistor (figure 3, paragraph 0054, where transistor T1 is shown to be connected to the light emitting element [element EML);
a first light shield layer that overlaps the first thin film transistor (figure 4, paragraph 0065 and 0066, where the light shield/blocking layer is BML and overlaps the first thin film transistor [where element ACT1 is part of the first transistor and the BML specifically overlaps this portion])
However, Park et al does not specifically disclose
[claim 25] wherein the first source region and the first drain region are intrinsic semiconductor patterns in which an impurity ion is not doped, a second light shield layer that overlaps the second thin film transistor.
However, Kanegae et al does teach
[claim 25] wherein the first source region and the first drain region are intrinsic semiconductor patterns in which an impurity ion is not doped (paragraph 0048, where the semiconductor layer for both the first and second semiconductor layers are intrinsic and no impurity ion is doped).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Park et al as modified to incorporate the teachings of Kanegae et al to use an intrinsic semiconductor layer for both semiconductor layers in order to provide more electrical stability for the devices as intrinsic semiconductor layers are known to be more stable than doped layers.
Additionally, Park et al as modified does not specifically disclose
[claim 25] Wherein the second light shield pattern overlaps the second thin film transistor, wherein a vertical distance between the first semiconductor pattern and the first light shield pattern is less than a vertical distance between the second semiconductor pattern and the second light shield pattern.
However, Koo et al does teach
[claim 25] Wherein the second light shield pattern overlaps the second thin film transistor (figure 14, paragraph 0074 where element 210 is the second light shield pattern which overlaps the second thin film transistor [element 20]),
wherein a vertical distance between the first semiconductor pattern and the first light shield pattern is less than a vertical distance between the second semiconductor pattern and the second light shield pattern (figure 14, paragraph 0074 and figure 4 of the primary [Park et al] reference, where element 210 of the secondary [Koo] reference replaces element G2 of the primary reference [figure 4, Park et al], when looking at the primary reference element G2 is located closer to the second semiconductor pattern [ACT2] than the first light shield layer is to the first semiconductor pattern [element BML is the light shield layer and element ACT1 is the first semiconductor pattern]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Park et al as modified with the teachings of Koo in order to maximize space while creating a more efficient device by blocking more incident light while adding no new structure by making the gate electrode both a gate electrode and light shielding layer.
Regarding claims 26-27,
Park et al further teaches
[claim 26] The light emitting display device of claim 25, wherein the first conductive pattern is non-overlapping with the first channel region and is not in contact with the first channel region (figure 4, elements CT2 and CT3 comprise the first conductive pattern and neither overlaps nor contacts the first channel region [CH1]).
[claim 27] The light emitting display device of claim 25, wherein the first source electrode is in contact with the first conducive portion and the first drain electrode is in contact with the second conductive portion (figure 4, element S1 is the source electrode and is contact with the first conductive portion [element CT2], and the drain electrode, D1, is in contact with the second conductive portion [element CT3]).
Conclusion
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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