Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In response to the correspondence filed 12/19/2025, the amendments to claims 25 and 28 overcome the previous 112(b) rejection. Additionally, the amendment to claims 1, 17, and 25 overcome the previous prior art rejection. However, upon further search and consideration, a new rejection is formulated with another reference below.
Additionally, it is noted that Park et al does not address the current amendments to claim 1, however a different reference is used to address the amended claims. Baeck et al does not address the specific limitations pertaining to the intrinsic semiconductor layers connected to a conductive pattern, however a new reference is used to address such amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-6, and 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama (US 20170278916 A1) in view of Park et al (US 20220013549 A1) Lee et al (US 20220013619) and Baeck et al (US 20200176603 A1).
Maruyama teaches
[claim 1] An organic light emitting display device comprising (paragraph 0019, said display device is an organic light emitting display device):
a substrate including a display area and a non-display area located outside of the display area (figure 4, paragraphs 0023-0024, where element 10 is the substrate and it includes a display area [labeled ‘DA’] and a non-display area [labeled ‘PR’ – meaing peripheral region but functions as a non-display area]);
a first thin film transistor on the substrate, the first thin film transistor comprising a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode (figure 4, paragraph 0024, where element TFT1 is the first thin film transistor located on the substrate [element 10], and it comprises a semiconductor pattern [labeled CH1 and portions in the active layer that correspond to the source and drain region that are not the source and drain electrodes], a first source electrode labeled SE1, a first drain electrode labeled DE1, and a first gate electrode labeled GE1);
a second thin film transistor on the substrate, the second thin film transistor comprising a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode (figure 4, paragraph 0026, where element TFT2 is the second thin film transistor and is located on the substrate [element 10], and it comprises a second semiconductor pattern [where the semiconductor pattern is labeled element CH2 and portions in the active layer that correspond to the source and drain region that are not the source and drain electrodes], a second gate electrode labeled GE2, a second source electrode labeled SE2, and a second drain electrode labeled DE2);
wherein the first semiconductor pattern comprises a polycrystalline semiconductor pattern (paragraph 0007, where polysilicon is a polycrystalline material and the transistors, specifically the semiconductor materials that make up the source and drain which are designated as the first semiconductor patter, is made of polycrystalline material).
However, Maruyama does not specifically disclose
[claim 1] a conductive pattern on an upper surface of at least one of the first semiconductor pattern or the second semiconductor pattern; and a first light shield pattern overlapping the second semiconductor pattern, the first light shield pattern connected to the second source electrode, and the second semiconductor pattern comprises an oxide semiconductor pattern, wherein the first semiconductor pattern comprises a first channel region, a first source region, and a first drain region such that the first channel region is interposed between the first source region and the first drain region, wherein the second semiconductor pattern comprises a second channel region, a second source region, and a second drain region such that the second channel region is interposed between the second source region and the second drain region, wherein the conductive pattern is in contact with upper surfaces of both the first source region and the first drain region, and/or with upper surfaces of both the second source region and the second drain region, and wherein upper surfaces of the first source region and the first drain region and/or upper surfaces of the second source region and the second drain region, with which the conductive pattern is in contact, are formed of an intrinsic semiconductor pattern.
However, Park et al does teach
[claim 1] a conductive pattern on an upper surface of at least one of the first semiconductor pattern or the second semiconductor pattern (figure 4, paragraphs 0092-0093, where the second semiconductor pattern is element ACT1, and replaces the second semiconductor pattern of the primary reference, Maruyama, and the conductive pattern is formed by contact holes CT2 and CT3 which are on the second semiconductor pattern [ACT1], where CT2 and CT3 are contact holes and are filled with conductive material to connect the drain and source regions of the semiconductor pattern);
and a first light shield pattern overlapping the second semiconductor pattern, the first light shield pattern connected to the second source electrode (figure 4, paragraph 0065 and 0066, where the light shielding/blocking layer is BML and overlaps the second semiconductor pattern [element ACT1], and additionally is connected to the second source electrode, element S1 which replaces the source electrode, SE2, of the primary reference Maruyama).
and the second semiconductor pattern comprises an oxide semiconductor pattern (paragraph 0061, element T1 which contains ACT1 [the second semiconductor pattern] is made of an oxide semiconductor material).
It would have been obvious to one of ordinary skill in the art to have modified the teachings Maruyama to incorporate the teachings of Park et al in order to shield the semiconductor pattern from light with a light blocking layer and provide connections via a conductive patter from said semiconductor pattern to limit ambient light on the display region/area of the semiconductor device to create a brighter display region for the overall device and allow electrical signals to be sent from transistors to the rest of the circuit to create a functioning display device.
Additionally, Maruyama as modified does not specifically disclose
[claim 1] wherein the first semiconductor pattern comprises a first channel region, a first source region, and a first drain region such that the first channel region is interposed between the first source region and the first drain region, wherein the second semiconductor pattern comprises a second channel region, a second source region, and a second drain region such that the second channel region is interposed between the second source region and the second drain region, wherein the conductive pattern is in contact with upper surfaces of both the first source region and the first drain region, and/or with upper surfaces of both the second source region and the second drain region, and wherein upper surfaces of the first source region and the first drain region and/or upper surfaces of the second source region and the second drain region, with which the conductive pattern is in contact, are formed of an intrinsic semiconductor pattern.
However, Lee et al does teach
[claim 1] wherein the first semiconductor pattern comprises a first channel region, a first source region, and a first drain region such that the first channel region is interposed between the first source region and the first drain region (figure 11, paragraphs 0115-0116, where element ST1 is the first semiconductor pattern [S1, AC1 and D1 specifically], and the first region is AC1, the first source region is S1, and the first drain region is D1, and the channel region is interposed between the first source and first drain region),
wherein the second semiconductor pattern comprises a second channel region, a second source region, and a second drain region such that the second channel region is interposed between the second source region and the second drain region (figure 11, paragraph 0119, where ST3 is the second semiconductor pattern [specifically S3, D3, and ACT3] where the source region is S3, the drain region is D3 and the channel region is ACT3 and the channel reigon is interposed between the source and drain region),
wherein the conductive pattern is in contact with upper surfaces of both the first source region and the first drain region, and/or with upper surfaces of both the second source region and the second drain region, and wherein upper surfaces of the first source region and the first drain region and/or upper surfaces of the second source region and the second drain region (figure 11, paragraph 0164, where elements CNT4 and CNT3 comprise the conductive pattern and are filled in such that they contact the top layer of the first source/drain region [ST1] and the top layer of the second source/drain region [ST3]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Maruyama as modified to incorporate the teachings of Lee et al in order to provide contacts between the first and second semiconductor regions to turn the semiconductors on using one conductive pattern instead of multiple, thus maximizing efficiency of the device (in particular, efficiency of materials used).
However, Maruyama et al as modified does not specifically disclose
[claim 1] [the conductive pattern], are formed of an intrinsic semiconductor pattern.
However, Baeck et al does teach
[claim 1] [the conductive pattern], are formed of an intrinsic semiconductor pattern (figure 1, paragraphs 0063-0064, where the semiconductor pattern [element 133] is of an intrinsic semiconductor material and contacts the conductive elements [element 150]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Maruyama as modified to incorporate the teachings of Baeck et al to use an intrinsic semiconductor material to ensure stable behavior of the material for the functioning of the device, increasing reliability of the device.
Regarding claims 2-3, 10, and 12,
Maruyama additionally teaches
[claim 2] an organic light emitting display device, wherein the first thin film transistor is in the non-display area and the second thin film transistor is in the display area (figure 4, paragraphs 0023-0024, element TFT1 is the first thin film transistor and is in the non-display region [labeled PR] and the second thin film transistor [element TFT2] is located in the display area).
[claim 3] an organic light emitting display device, wherein the first gate electrode and the second gate electrode are in different layers, and the first gate electrode and the second gate electrode are respectively over the first semiconductor pattern and the second semiconductor pattern (figure 4, paragraphs 0025-0026 where the first gate electrode [element GE1] and the second gate electrode [element GE2] are in different layers and each one is respectively over first semiconductor pattern [element CH1 and corresponding elements on that layer] and the second semiconductor pattern [element CH2 and corresponding elements on that layer]).
[claim 10] The organic light emitting display device according to claim 1, wherein the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the second drain electrode are in a same layer (figure 4, where the first source electrode [element SE1], and first drain electrode [DE1] extend through multiple layers and reside in the same layer as the second source electrode [SE2], and second drain electrode [SE2]).
[claim 12] The organic light emitting display device according to claim 3, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are in a same layer (figure 4, where the first source electrode [element SE1], and first drain electrode [DE1] extend through multiple layers and reside in the same layer as the second source electrode [SE2], and second drain electrode [SE2]).
and the second gate electrode is between the second semiconductor pattern and the second source electrode (figure 4, element GE2 is the second gate electrode and it is situated between the semiconductor pattern [element CH2 and adjacent elements] and the second source electrode [SE2]).
Regarding claims 5-6, 9, 11, 13, and 14
Maruyama further teaches
[claim 9] The organic light emitting display device according to claim 1, further comprising: a lower buffer layer between the substrate and the first semiconductor pattern (figure 4, paragraph 0024, where element 36 is a butter layer between the first semiconductor patter [element CH1 and adjacent elements] and the substrate [element 10]);
[claim 11] The organic light emitting display device according to claim 1, wherein the first source electrode and the first drain electrode are on a different layer from the second source electrode and the second drain electrode (figure 4, elements SE1 and DE1 are the first source and drain electrodes respectively, and they extend into a layer below the second semiconductor patter [element CH2], and subsequently below the second source and drain electrodes [elements SE2 and DE2], thus the first and second source and drain electrodes are on a different layer than the second source and drain electrodes).
[claim 13] The organic light emitting display device according to claim 11, wherein the first source electrode and the first drain electrode are over the first gate electrode such that at least one insulating layer is interposed between the first gate electrode and the first source electrode and the first drain electrode (figure 4, paragraph 0025, where the first source electrode [element SE1], the first drain electrode [element DE1] are over the first gate electrode [GE1] where there is an insulating layer between the two [element 16]).
However, Maruyama as modified does not specifically disclose
[claim 5] an organic light emitting display device, wherein the conductive pattern is a metal pattern contacting at least one of the first semiconductor pattern and the second semiconductor pattern.
[claim 6] an organic light emitting display device, wherein the first light shield pattern is under the second semiconductor pattern such that the first light shield pattern is closer to the substrate than the second semiconductor pattern.
[claim 9] and an upper buffer layer between the first semiconductor pattern and the second semiconductor pattern, wherein the first light shield pattern is inside of the upper buffer layer.
[claim 11] where at least one insulating layer is interposed between the first source electrode and the first drain electrode and the second source electrode and the second drain electrode
[claim 13] and the first source electrode and the first drain electrode are in a same layer as the first light shield pattern.
[claim 14] The organic light emitting display device according to claim 1, wherein the conductive pattern is on upper edges of the second source region and the second drain region.
However, Park et al does teach
[claim 5] an organic light emitting display device, wherein the conductive pattern is a metal pattern contacting at least one of the first semiconductor pattern and the second semiconductor pattern (figure 4, paragraphs 0092-0093 where the conductive pattern [CT2 and CT3] is made of metal and contacts the second semiconductor pattern [element ACT1 which consists of SP1, CP1, and DP1] where the metal conductive pattern specifically contacts SP1 and DP1 of the second semiconductor pattern [ACT1]).
[claim 6] an organic light emitting display device, wherein the first light shield pattern is under the second semiconductor pattern such that the first light shield pattern is closer to the substrate than the second semiconductor pattern (figure 5, where BML is the first light shield pattern and is located under the second semiconductor pattern [element ACT1] and is located closer to the substrate [element SUB] than the second semiconductor pattern [element ACT1] as shown visually by the picture where element BML is located on the substrate and element ACT1 is located above BML further from the substrate than element BML).
[claim 9] and an upper buffer layer between the first semiconductor pattern and the second semiconductor pattern, wherein the first light shield pattern is inside of the upper buffer layer (figure 4, where element 10 is the second transistor and replaces the second transistor of figure 4 in the base reference [figure 4, TFT2], in replacing this transistor the active layers are assumed to be in the same layer, thus in the secondary reference [Park et al] in figure 4 and paragraph 0071, the layers BML, BF1 and BF2 are below the second semiconductor patter [ACT1] and in insulating layer 140 [paragraph 0087], and thus are above the first semiconductor pattern of the primary reference [figure 4 of Maruyama, element CH1 and adjacent elements], and is considered the upper buffer layer).
[claim 11] where at least one insulating layer is interposed between the first source electrode and the first drain electrode and the second source electrode and the second drain electrode (figure 4, where element 10 is the second transistor and replaces the second transistor of figure 4 in the base reference [figure 4, TFT2], in replacing this transistor the active layers of the second semiconductor pattern in the first reference and second reference are assumed to be in the same layer, thus in the secondary reference [Park et al] in figure 4 and paragraph 0071, the layers BML, BF1 and BF2 are below the second semiconductor patter [ACT1] and in insulating layer 140 [paragraph 0087], thus there would be an insulating layer between the second drain and source electrodes and the first source and drain electrodes).
[claim 13] and the first source electrode and the first drain electrode are in a same layer as the first light shield pattern (figure 4 of element Maruyama and figure 4 of Park et al, where layer 140 of Park et al replaces the layer of Maruyama in which the second active layer resides [TFT2 in section 20], which places the light blocking layer below the active layer [reading Maruyama in light of Park et al] causing the first drain electrode and first source electrode of Maruyama et al residing in the same layer [layer 16]).
[claim 14] The organic light emitting display device according to claim 1, wherein the conductive pattern is on upper edges of the second source region and the second drain region (figure 4, elements CT2 and CT3 being the conductive pattern is located on the upper edges of the second source [SP1] and drain [DP1] region).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Maruyaman as modified to incorporate the teachings of Park et al in order to shield the semiconductor pattern from light with a light blocking layer and provide connections via a conductive patter from said semiconductor pattern to limit ambient light on the display region/area of the semiconductor device to create a brighter display region for the overall device and allow electrical signals to be sent from transistors to the rest of the circuit to create a functioning display device.
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Figure 4 of primary reference Maruyama.
Claim(s) 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama (US 20170278916 A1), Park et al (US 20220013549 A1), Lee et al (US 20220013619) and Baeck et al (US 20200176603 A1), as applied to claim 6, and further in view of Koo (US 20200403011 A1).
Maruyama as modified teaches all of the limitations of the dependent claim, claim 6, but does not specifically disclose
[claim 7] an organic light emitting display device, further comprising: a third thin film transistor in the display area, the third thin film transistor comprising a third semiconductor pattern including an oxide semiconductor pattern, a third gate electrode, a third source electrode, and a third drain electrode; and a second light shield pattern overlapping the third semiconductor pattern, wherein a vertical distance between the second semiconductor pattern and the first light shield pattern is less than a vertical distance between the third semiconductor pattern and the second light shield pattern.
[claim 8] and organic light emitting display device, wherein the second thin film transistor is a driving thin film transistor in a pixel and the driving thin film transistor is configured to drive a light emitting element included in the pixel, and the third thin film transistor is a switching thin film transistor in the pixel and the third thin film transistor is connected to the second thin film transistor.
However, Koo does teach
[claim 7] an organic light emitting display device, further comprising: a third thin film transistor in the display area, the third thin film transistor comprising a third semiconductor pattern including an oxide semiconductor pattern, a third gate electrode, a third source electrode, and a third drain electrode (figures 4 and 14, where the two transistors of figure 14 are located in the display area, thus when reading it onto the primary reference Maruyama, the two transistors, elements 10 and 20, take the place of the two transistors of the display area of Maruyama. Per paragraphs 0138-0139 and figure 14, element 20 is the third transistor which has a third semiconductor pattern made of an oxide film [paragraph 0140, element 230], a third gate electrode [element 210], a third source electrode [element 250], a third drain electrode [element 260]);
and a second light shield pattern overlapping the third semiconductor pattern, wherein a vertical distance between the second semiconductor pattern and the first light shield pattern is less than a vertical distance between the third semiconductor pattern and the second light shield pattern (paragraph 0076, where the gate electrode [element 210] acts as a light blocking layer and overlaps the third semiconductor pattern, and is closer to the semiconductor layer than the first light blocking layer [element 110 of transistor 10 which is replaced as the second transistor in the display area] is to the second semiconductor pattern [element 130], the main difference is the presence of layer 140 which causes element 110 to be further from the semiconductor layer 130 than element 210 is from the semiconductor layer 230).
[claim 8] and organic light emitting display device, wherein the second thin film transistor is a driving thin film transistor in a pixel and the driving thin film transistor is configured to drive a light emitting element included in the pixel, and the third thin film transistor is a switching thin film transistor in the pixel and the third thin film transistor is connected to the second thin film transistor (paragraph 0061, figure 14, where the two transistors, elements 10 and 20, can either be a driving or a switching transistor. In the present case, element 10 is the driving thin film transistor and element 20 is the switching thin film transistor. Per paragraph 0061-0062, the transistors are connected to circuitry for one LED device and thus are connected to each other).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Maruyama as modified to incorporate the teachings of Koo in order to make a more efficient device by including the light shielding layers with the third and fourth semiconductor layers.
Claim(s) 17-22 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 20220013549 A1) in view of Koo (US 20200403011 A1), Lee et al (US 20220013619), and , Kanegae et al (US 20140048807 A1).
Park et al teaches
[claim 17] An organic light emitting display device comprising: a substrate on which a display area and a non-display area located outside of the display area are disposed (paragraph 0039, where the display area contains the transistors in the enclosure, and the non-display area is outside the display area);
a first thin film transistor disposed in the display area, and comprising a first semiconductor pattern comprising, a first conductive pattern, a first gate electrode, a first source electrode, and a first drain electrode (figure 4, paragraphs 0064, 0092-0095, where the first conductive pattern is elements CT2 and CT3, the first semiconductor pattern is element ACT1, the first gate electrode is element G1, first source electrode is element S1 and the first drain electrode is element D1);
a second thin film transistor disposed in the display area, and comprising a second semiconductor pattern comprising, a second conductive pattern, a second gate electrode, and a second source electrode, and a second drain electrode (figure 4, paragraphs 0064, 0092-0095, where the second conductive pattern is elements CT4 and CT5, the second semiconductor pattern is element ACT2, the second gate electrode is element G2, second source electrode is element S2 and the second drain electrode is element D2);
a first light shield pattern located under, and overlapping, the first semiconductor pattern such that the first light shield pattern is closer to the substrate than the first semiconductor pattern (figure 5, paragraph 0066, where element BML is the first light shield pattern and overlaps the first semiconductor pattern [element ACT1] and is situated under the first semiconductor pattern, and closer to the substrate [element SUB] than the first semiconductor pattern is);
However, Park et al does not specifically disclose
[claim 17] and a second light shield pattern overlapping the second semiconductor pattern, wherein a vertical distance between the first semiconductor pattern and the first light shield pattern is less than a vertical distance between the second semiconductor pattern and the second light shield pattern, wherein the first semiconductor pattern comprises a first channel region, a first source region, and a first drain region such that the first channel region is interposed between the first source region and the first drain region,wherein the second semiconductor pattern comprises a second channel region, a second source region, and a second drain region such that the second channel region is interposed between the second source region and the second drain region, wherein the first conductive pattern is in contact with upper surfaces both of the first source region and the first drain region, and the second conductive pattern is in contact with upper surfaces both of the second source region and the second drain region, and wherein the first source region and the first drain region and the second source region and the second drain region are intrinsic semiconductor patterns in which an impurity ion is not doped.
However, Koo does teach
[claim 17] and a second light shield pattern overlapping the second semiconductor pattern (figure 14, paragraph 0074, where element 210 is the second light shield pattern which replaces the element G2 of the primary [Park et al, figure 4] reference [note the gate electrode is serving a dual function],
wherein a vertical distance between the first semiconductor pattern and the first light shield pattern is less than a vertical distance between the second semiconductor pattern and the second light shield pattern (figure 14, paragraph 0074 and figure 4 of the primary [Park et al] reference, where element 210 of the secondary [Koo] reference replaces element G2 of the primary reference [figure 4, Park et al], when looking at the primary reference element G2 is located closer to the second semiconductor pattern [ACT2] than the first light shield layer is to the first semiconductor pattern [element BML is the light shield layer and element ACT1 is the first semiconductor pattern]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Park et al with the teachings of Koo in order to maximize space while creating a more efficient device by blocking more incident light while adding no new structure by making the gate electrode both a gate electrode and light shielding layer.
Additionally, Park et al as modified does not specifically disclose
[claim 17] wherein the first semiconductor pattern comprises a first channel region, a first source region, and a first drain region such that the first channel region is interposed between the first source region and the first drain region, wherein the second semiconductor pattern comprises a second channel region, a second source region, and a second drain region such that the second channel region is interposed between the second source region and the second drain region, wherein the conductive pattern is in contact with upper surfaces of both the first source region and the first drain region, and/or with upper surfaces of both the second source region and the second drain region, and wherein upper surfaces of the first source region and the first drain region and/or upper surfaces of the second source region and the second drain region, and wherein the first source region and the first drain region and the second source region and the second drain region are intrinsic semiconductor patterns in which an impurity ion is not doped.
However, Lee et al does teach
[claim 17] wherein the first semiconductor pattern comprises a first channel region, a first source region, and a first drain region such that the first channel region is interposed between the first source region and the first drain region (figure 11, paragraphs 0115-0116, where element ST1 is the first semiconductor pattern [S1, AC1 and D1 specifically], and the first region is AC1, the first source region is S1, and the first drain region is D1, and the channel region is interposed between the first source and first drain region),
wherein the second semiconductor pattern comprises a second channel region, a second source region, and a second drain region such that the second channel region is interposed between the second source region and the second drain region (figure 11, paragraph 0119, where ST3 is the second semiconductor pattern [specifically S3, D3, and ACT3] where the source region is S3, the drain region is D3 and the channel region is ACT3 and the channel reigon is interposed between the source and drain region),
wherein the conductive pattern is in contact with upper surfaces of both the first source region and the first drain region, and/or with upper surfaces of both the second source region and the second drain region, and wherein upper surfaces of the first source region and the first drain region and/or upper surfaces of the second source region and the second drain region (figure 11, paragraph 0164, where elements CNT4 and CNT3 comprise the conductive pattern and are filled in such that they contact the top layer of the first source/drain region [ST1] and the top layer of the second source/drain region [ST3]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Park et al as modified to incorporate the teachings of Lee et al in order to provide contacts between the first and second semiconductor regions to turn the semiconductors on using one conductive pattern instead of multiple, thus maximizing efficiency of the device (in particular, efficiency of materials used).
However, Park et al as modified does not specifically disclose
[claim 17] and wherein the first source region and the first drain region and the second source region and the second drain region are intrinsic semiconductor patterns in which an impurity ion is not doped.
However, Kanegae et al does teach
[claim 17] and wherein the first source region and the first drain region and the second source region and the second drain region are intrinsic semiconductor patterns in which an impurity ion is not doped (paragraph 0048, where the semiconductor layer for both the first and second semiconductor layers are intrinsic and no impurity ion is doped).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Park et al as modified to incorporate the teachings of Kanegae et al to use an intrinsic semiconductor layer for both semiconductor layers in order to provide more electrical stability for the devices as intrinsic semiconductor layers are known to be more stable than doped layers.
Regarding claims 18-22
Park et al further teaches
[claim 18] The organic light emitting display device according to claim 17, wherein the conductive pattern is on respective upper surfaces of the first semiconductor pattern and the second semiconductor pattern (figure 4, paragraphs 0092-0095 where elements CT2 and CT3 [first conductive pattern] is on an upper surface of the first semiconductor pattern [element ACT1], and the second conductive pattern [elements CT4 and CT5] are on an upper surface of the second semiconductor pattern [ACT2]).
[claim 19] The organic light emitting display device according to claim 17, wherein the first semiconductor pattern and the second semiconductor pattern each comprise an oxide semiconductor pattern (paragraph 0061, where the active regions of both the first and second semiconductor pattern [linked to T1 and T2 respectively] are made of an oxide semiconductor material).
[claim 20] The organic light emitting display device according to claim 17, wherein the first light shield pattern is connected to the first source electrode (figure 4, where element BML [first light shielding layer] is connected to the first source electrode [element S1] via element CT1).
[claim 21] The organic light emitting display device according to claim 17, wherein the first gate electrode, the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the second drain electrode are in a same layer (figure 4, where the first gate electrode [element G1], source electrode [element S1], drain electrode [element D1], second gate electrode [element G2], second source electrode [element S2], second drain electrode [element D2] all reside within layer 140, thus being in the same layer).
[claim 22] The organic light emitting display device according to claim 17, further comprising: a storage capacitor comprising one electrode in a same layer as the first semiconductor pattern and the first conductive pattern (figure 4, paragraph 0054, where the storage capacitor [Cst] has one electrode as the first gate electrode [element G1] in element T1, thus putting the capacitor in the same layer as the first semiconductor pattern and conductive pattern [layer 140]).
Claim(s) 25-27 rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 20220013549 A1) in view of Kanegae et al (US 20140048807 A1).
Park et al teaches
[claim 25] A light emitting display device comprising: a substrate including a display area and a non-display area around the display area (paragraph 0039, where the display area contains the transistors in the enclosure, and the non-display area is outside the display area);
a first thin film transistor in the display area, the first thin film transistor including a first drain electrode, a first source electrode, a first gate electrode, and a first semiconductor pattern having a first channel region, a first source region at a first end of the first channel region, and a first drain region at a second end of the first channel region that is opposite the first end (figure 4, paragraphs 0064, 0092-0095, where transistor T1 is the first thin film transistor in the display area, and consists of a first semiconductor pattern [element ACT1] with a first channel region CH1, a first source region on one end labeled SP1, a first drain region opposite end of the first source region labeled D1, a first source electrode labeled S1, first gate electrode G1, and first drain electrode D1);
a first conductive pattern on the first semiconductor pattern, the first conductive pattern including a first conductive portion that is in contact with and overlaps an upper surface of the first source region and a second conductive portion that is in contact with and overlaps an upper surface of the second source region (figure 4, paragraphs 0064, 0092-0095, where the first conductive pattern is elements CT2 and CT3 located on the first semiconductor pattern [ACT1] where element CT2 of the first conductive pattern is in contact with the first source region SP1 and is the first conductive portion, and element CT3 of the first conductive pattern is in contact with the first drain region DP1 and is the second conductive portion in contact with the drain region and each overlaps an upper service of the respective region);
and a light emitting element configured to emit light, the light emitting element connected to the first thin film transistor (figure 3, paragraph 0054, where transistor T1 is shown to be connected to the light emitting element [element EML).
However, Park et al does not specifically disclose
[claim 25] wherein the first source region and the first drain region are intrinsic semiconductor patterns in which an impurity ion is not doped.
However, Kanegae et al does teach
[claim 25] wherein the first source region and the first drain region are intrinsic semiconductor patterns in which an impurity ion is not doped (paragraph 0048, where the semiconductor layer for both the first and second semiconductor layers are intrinsic and no impurity ion is doped).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Park et al as modified to incorporate the teachings of Kanegae et al to use an intrinsic semiconductor layer for both semiconductor layers in order to provide more electrical stability for the devices as intrinsic semiconductor layers are known to be more stable than doped layers.
Regarding claims 26-27,
Park et al further teaches
[claim 26] The light emitting display device of claim 25, wherein the first conductive pattern is non-overlapping with the first channel region and is not in contact with the first channel region (figure 4, elements CT2 and CT3 comprise the first conductive pattern and neither overlaps nor contacts the first channel region [CH1]).
[claim 27] The light emitting display device of claim 25, wherein the first source electrode is in contact with the first conducive portion and the first drain electrode is in contact with the second conductive portion (figure 4, element S1 is the source electrode and is contact with the first conductive portion [element CT2], and the drain electrode, D1, is in contact with the second conductive portion [element CT3]).
Claim(s) 28-33 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 20220013549 A1) and Kanegae et al (US 20140048807 A1), as applied to claim 25, and further in view of Maruyama (US 20170278916 A1).
Park et al as modified teaches all of the limitations of the parent claim, claim 25, and additionally teaches
[claim 28] The light emitting display device of claim 25, further comprising: a second thin film transistor in the display area, the second thin film transistor including a second drain electrode, a second source electrode, a second gate electrode, and a second semiconductor pattern having a second channel region, a second source region at a first end of the second channel region, and a second drain region at a second end of the second channel region that is opposite the first end of the second channel region (figure 4, paragraphs 0064, 0092-0095, where transistor T3 is the second thin film transistor in the display area, and consists of a second semiconductor pattern [element ACT2] with a second channel region CH2, a second source region on one end labeled SP2, a second drain region opposite end of the first source region labeled D2, a second source electrode labeled S2, second gate electrode G2, and second drain electrode D2);
wherein the first semiconductor pattern and the second semiconductor pattern comprise oxide (paragraph 0060, transistors T1 and T2 both are made of oxide semiconductors; thus, the semiconductor pattern is made of them).
[claim 30] The light emitting display device of claim 29, further comprising: a second conductive pattern on the second semiconductor pattern, the second conductive pattern including a first conductive portion that is in contact with and overlaps an upper surface of the second source region and a second conductive portion that is in contact with and overlaps an upper surface of the second source region (figure 4, elements CT4 and CT5 comprise the second conductive pattern on the second semiconductor pattern [ACT2], the first conductive portion of the conductive pattern is the left hand side element CT4 as shown in figure 2 below, and is in contact with and overlaps the second source region [S2]. The second conductive portion of the second conductive pattern is the right-hand side of element CT4 as shown in figure 2 below. Both sections overlap and are in contact with the second source region, S2).
[claim 31] The light emitting display device of claim 29, wherein the first gate electrode is closer to the substrate than the first drain electrode and the first source electrode (figure 4, where elements S1 and D1 [source and drain electrodes] reside in layer 150, and the first gate electrode [G1] is in layer 140, where the first gate electrode is closer to the substrate [SUB] than the first source and drain electrodes).
[claim 33] The light emitting display device of claim 32, further comprising: a second conductive pattern on the second semiconductor pattern, the second conductive pattern including a first conductive portion that is in contact with and overlaps an upper surface of the second source region and a second conductive portion that is in contact with and overlaps the second source region (figure 4, elements CT4 and CT5 comprise the second conductive pattern on the second semiconductor pattern [ACT2], the first conductive portion of the conductive pattern is the left hand side element CT4 as shown in figure 2 below, and is in contact with and overlaps the second source region [S2]. The second conductive portion of the second conductive pattern is the right-hand side of element CT4 as shown in figure 2 below. Both sections overlap and are in contact with the second source region, S2).
However, Park et al as modified does not specifically disclose
[claim 28] and a third thin film transistor in the non-display area, the third thin film transistor including a third drain electrode, a third source electrode, a third gate electrode, and a third semiconductor pattern having a third channel region, a third source region at a first end of the third channel region, and a third drain region at a second end of the third channel region that is opposite the first end of the third channel region, and the third semiconductor pattern comprises polycrystalline.
[claim 29] The light emitting display device of claim 28, wherein the first drain electrode, the first source electrode, the second drain electrode, the second source electrode, the third drain electrode, and the third source electrode are on a same layer.
[claim 30] and a third conductive pattern on the third semiconductor pattern, the third conductive pattern including a first conductive portion that is in contact with and overlaps an upper surface of the third source region and a second conductive portion that is in contact with and overlaps an upper surface of the third source region.
[claim 32] The light emitting display device of claim 28, wherein the first drain electrode, the first source electrode, the second drain electrode, and the second source electrode are on a different layer from the third source electrode and the third drain electrode such that the third source electrode and the third drain electrode are closer to the substrate than the first drain electrode, the first source electrode, the second drain electrode, and the second source electrode.
However, Maruyama does teach
[claim 28] and a third thin film transistor in the non-display area, the third thin film transistor including a third drain electrode, a third source electrode, a third gate electrode, and a third semiconductor pattern having a third channel region, a third source region at a first end of the third channel region, and a third drain region at a second end of the third channel region that is opposite the first end of the third channel region (figure 4, paragraphs 0028-0029, 0040, where the third transistor is element TFT1 and is located in the non-display area [labeled PR on figure 4 which is the peripheral region, also known as the non-display area], the transistor comprises a third drain electrode [element DE1], a third source electrode [element SE1], a third gate electrode [element GE1], and a third semiconductor pattern consisting of element CH1 and the adjacent regions, a third source region which is the region adjacent to CH1 underneath element SE1, and on the opposite end of CH1 from the source region is the drain region situated beneath element DE1),
and the third semiconductor pattern comprises polycrystalline (paragraph 0007, where any of the transistors can be made of polysilicon which is a polycrystalline material).
[claim 29] The light emitting display device of claim 28, wherein the first drain electrode, the first source electrode, the second drain electrode, the second source electrode, the third drain electrode, and the third source electrode are on a same layer (figure 4, where elements SE1, SE2, SE3, DE1, DE2, and DE3 represent the first, second, third source and drain electrodes respectively. The first and second drain electrodes are read onto the primary reference in terms of their location only, thus according to Maruyama, the three sets of electrodes all reside in the top layer of element 16 of figure 4, thus being on the same layer).
[claim 30] and a third conductive pattern on the third semiconductor pattern, the third conductive pattern including a first conductive portion that is in contact with and overlaps an upper surface of the third source region and a second conductive portion that is in contact with and overlaps an upper surface of the third source region (figure 4, paragraphs 0028-0029, 0040, where the third transistor is element TFT1 and is located in the non-display area [labeled PR on figure 4 which is the peripheral region, also known as the non-display area], where the first and second conductive portion is the lefthand element CP1 of element TFT1, where the first portion is the lefthand side portion of said CP1 element [similar to figure 2 below where the conductive pattern is split in half], and the second conductive portion is the right-hand side portion of said element CP1, both of which overlap and contact the third source region [element adjacent to the left of element CH1 in the same layer as CH1 underneath element SE1]).
[claim 32] The light emitting display device of claim 28, wherein the first drain electrode, the first source electrode, the second drain electrode, and the second source electrode are on a different layer from the third source electrode and the third drain electrode such that the third source electrode and the third drain electrode are closer to the substrate than the first drain electrode, the first source electrode, the second drain electrode, and the second source electrode (figure 4 of Maruyama and figure 4 of Park et al, where transistors T1 and T2 of figure 4 of Park et al are placed in the same region as TFT2 in section 18 and section 20 of Maruyama. These two transistors in the display area consist of the first two transistors with first source electrode, first drain electrode, second source electrode and second drain electrode all on the same layer in Park et al [layer 150], where layer 150 is in the place of the top layer of element 16 in Maruyama et al, and the active regions of Park et al [ACT1 and ACT2] are in the same location as active layers of Maruyama [TFT2 SW1 and TFT2 SW2]. With these being in place, the third source and drain electrode, element SE1 and SE2 of Maruyama extend below the active layer of the first two transistors [TFT2 SW1 and TFT2 SW2 of Maruyama] and thus are closer to the substrate than the first and second source and drain electrodes, and subsequently is on different layers).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings Park et al as modified with the teachings of Maruyama to incorporate a third transistor outside the display area to maximize production by not needing to lay the transistor underneath the display layers.
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Figure 2: Figure 4 of Park et al with designation for the second conductive pattern.
Allowable Subject Matter
Claims 15 and 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818