DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/22/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3, 5 – 12, 15, 17, and 19 – 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claim is dependent on cancelled claim 13. The claim will be interpreted as being dependent on claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5 – 12, 14, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2021/0366818).
Regarding claim 1, Kim teaches (FIG. 10, 12):
A microelectronic structure comprising:
a substrate (101);
an electronic device (200) bonded to the substrate with an array of solder bumps (210);
a pattern on the substrate laterally adjacent to the array of solder bumps, wherein the pattern extends directly underneath the electronic device and outside of edges of the electronic device (111C);
an underfill material (300) between the electronic device and the substrate, wherein the underfill material includes a plurality of isolated underfill regions adjacent to one or more of the edges of the electronic device, wherein ingress of each isolated underfill region underneath the electronic device is confined by the pattern and encapsulates a corresponding group of solder bumps of the array of solder bumps; and
a plurality of vent openings along the one or more of the edges and between the plurality of isolated underfill regions;
wherein the plurality of vent openings comprises a first vent opening and a second vent opening, wherein the first vent opening is fluidly connected to the second vent opening with a first vent pathway that encompasses a first plurality of solder bumps of the array of solder bumps (FIG. 10, 12, spaces between dams 111).
Regarding claim 3, Kim teaches (FIG. 10, 12):
The microelectronic structure of claim 1, wherein the first vent opening is along a first edge of the one or more edges and the second vent opening is along a second edge of the one or more edges.
Regarding claim 5, Kim teaches (FIG. 10, 12):
The microelectronic structure of claim 1, wherein the plurality of vent openings comprises a third vent opening and a fourth vent opening, wherein the third vent opening is fluidly connected to the fourth vent opening with a second vent pathway.
Regarding claim 6, Kim teaches (FIG. 10, 12):
The microelectronic structure of claim 5, further comprising a vent cavity, wherein the first vent pathway and the second vent pathway are fluidly connected with the vent cavity.
Regarding claim 7, Kim teaches (FIG. 10, 12):
The microelectronic structure of claim 1, wherein the plurality of isolated underfill regions includes:
a first isolated underfill region that spans underneath a first corner of the electronic device;
a second isolated underfill region that spans underneath a second corner of the electronic device; and
a third isolated underfill region that spans underneath a third corner of the electronic device.
Regarding claim 8, Kim teaches (semiconductor chip 200):
The microelectronic structure of claim 1, wherein the electronic device is selected from the group consisting of a die, a package, an active component, a passive component, and a routing substrate ([0018]).
Regarding claim 9, Kim teaches (FIG. 19):
The microelectronic structure of claim 1, further comprising a plurality of isolated edge bond regions adjacent to the one or more edges of the electronic device (115 defines additional edge and corner regions).
Regarding claim 10, Kim teaches (FIG. 19):
The microelectronic structure of claim 9, wherein the first vent opening of the plurality of vent openings is between a first isolated edge bond region of the plurality of isolated edge bond regions and a first isolated underfill region of the plurality of isolated underfill regions (115 defines additional edge and corner regions).
Regarding claim 11, Kim teaches (FIG. 19):
The microelectronic structure of claim 10, wherein the second vent opening of the plurality of vent openings is between the first isolated edge bond region of the plurality of isolated edge bond regions and a second isolated underfill region of the plurality of isolated underfill regions (115 defines additional edge and corner regions).
Regarding claim 12, Kim teaches (FIG. 19):
The microelectronic structure of claim 11, wherein the first vent opening and the second vent opening are along a same edge of the electronic device, the first isolated underfill region spans underneath a first corner of the electronic device, and the second isolated underfill region spans underneath a second corner of the electronic device (115 defines additional edge and corner regions).
Regarding claim 14, Kim teaches, as best understood by the examiner in light of the rejection under 35 USC 112:
The microelectronic structure of claim 13, wherein the pattern is a solder mask pattern ([0019]).
Regarding claim 21, Kim teaches (FIG. 10, 12):
The microelectronic structure of claim 1, wherein the plurality of isolated underfill regions includes:
a first isolated edge bond region that spans along a first corner of the electronic device;
a second isolated edge bond region that spans along a second corner of the electronic device; and
a third isolated edge bond region that spans along a third corner of the electronic device.
Claims 15, 17, 19, 20, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lakhera et al. (US 2019/0157222).
Regarding claim 15, Lakhera teaches (FIG. 2A, 2B):
A microelectronic structure comprising:
a substrate (102);
an electronic device (104) bonded to the substrate with an array of solder bumps (130, 132);
a plurality of isolated edge bond regions (124) of an edge bond material adjacent to one or more edges of the electronic device, wherein the plurality of isolated edge bond regions does not encapsulate any solder bumps of the array of solder bumps (FIG. 2B); and
a plurality of vent openings along the one or more edges and between the plurality of isolated edge bond regions (128, FIG. 2B);
wherein the plurality of vent openings comprises a first vent opening and a second vent opening, wherein the first vent opening is fluidly connected to the second vent opening with a first vent pathway that encompasses a first plurality of solder bumps of the array of solder bumps (FIG. 2B).
Regarding claim 17, Lakhera teaches (FIG. 2A, 2B):
The microelectronic structure of claim 15, wherein the first vent opening is along a first edge of the one or more edges and the second vent opening is along a second edge of the one or more edges (dam 222 does not contact both the device and the substrate, thereby allowing for fluid connection between edge openings).
Regarding claim 19, Lakhera teaches (FIG. 2A, 2B):
The microelectronic structure of claim 15, wherein the plurality of vent openings comprises a third vent opening and a fourth vent opening, wherein the third vent opening is fluidly connected to the fourth vent opening with a second vent pathway.
Regarding claim 20, Lakhera teaches (FIG. 2A, 2B):
The microelectronic structure of claim 19, further comprising a vent cavity, wherein the first vent pathway and the second vent pathway are fluidly connected with the vent cavity.
Regarding claim 22, Lakhera teaches:
The microelectronic structure of claim 15, wherein the electronic device is selected from the group consisting of a die, a package, an active component, a passive component, and a routing substrate ([0012]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624
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