DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 5 is objected to because of the following informalities:
Regarding claim 1
“in at least one or an azimuth and an elevation direction” should read -- in at least one of an azimuth and an elevation direction –
Regarding claim 5
“larger than ASIC bump pitch” should read -- larger than an ASIC bump pitch --
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 8-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20210138506 A1, “Lee”).
Regarding claim 1, Lee discloses an electro-acoustic module, comprising: an acoustic stack; and at least one application-specific integrated circuit (ASIC) electrically coupled to the acoustic stack by an interconnect having a fan-out architecture(Fig. 1, [0023] acoustic array (10) is comprised of multiple transducer elements (10E) distributed over a grid in one or two dimensions. Interposer (12) provides high density signal routing and is placed between the acoustic array and a micro-beamforming ASIC (14)) ; wherein the electro-acoustic module has an active aperture substantially equal to an overall size of the electro-acoustic module in at least one or an azimuth and an elevation direction (Fig. 1 (10) illustrates the acoustic array being comprised of acoustic transducers (10E) that create an active aperture that is of substantially the same size as the electro-acoustic module in an azimuth direction).
Regarding claim 2, Lee discloses the electro-acoustic module of claim 1. Lee further discloses the interconnect is a multi-layer interposer, and wherein the interconnect includes input/output (I/O) connections located along an underside of the interconnect, opposite of the acoustic stack (Fig. 1, [0044] interposer (12) is a substrate bearing through-silicon-vias (12D). the core is made of silicon waver in the middle and high-density routing layers (12B) formed on either one surface or both surfaces of the silicon core)([0036] interposer has two opposing surfaces which include conductors such as I/O pads).
Regarding claim 3, Lee discloses the electro-acoustic module of claim 1. Lee further discloses the interconnect is positioned between the acoustic stack and the at least one ASIC along a propagation direction of the electro-acoustic module (Fig. 1, [0022], interposer is positioned between the ASIC and the acoustic array)(it is the examiner’s interpretation that the positioning of the acoustic array, interposer, and ASIC, is along a propagation direction of the electro-acoustic module); and each layer of a plurality of layers of the interconnect has a bump pitch that is different from adjacent layers ([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps)(it can be seen in Fig. 1 that electrical joints of the various layers have different pitches).
Regarding claim 4, Lee discloses the electro-acoustic module of claim 3. Lee further discloses the bump pitch of each of the plurality of layers decreases in a direction from the acoustic stack to the at least one ASIC([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints (16) on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps)(Fig. 1 Illustrates that electrical joints of the various layers have different pitches, with the bump pitch of the electrical joints decreasing from the acoustic stack side to the ASIC side).
Regarding claim 5, Lee discloses the electro-acoustic module of claim 1. Lee further discloses an element pitch of the acoustic stack is larger than ASIC bump pitch of the at least one ASIC([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps)(Fig. 1 illustrates that the element pitch of acoustic elements (10E) is larger than the ASIC bump pitch of electrical joints (16)).
Regarding claim 6, Lee discloses the electro-acoustic module of claim 1. Lee further discloses wherein the interconnect has bumps protruding outwards from a top layer of the interconnect, the bumps of the top layer having a first pitch corresponding to an element pitch of the acoustic stack, and bumps protruding outwards from a bottom layer of the interconnect, the bumps of the bottom layer having a second pitch corresponding to an ASIC bump pitch of the at least one ASIC([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps)(Fig. 1 illustrates that the element pitch of acoustic elements (10E) matches the bump pitch of the first electrical joints (15) and the ASIC bump pitch of electrical joints (16)) have a second pitch corresponding to the ASIC).
Regarding claim 8, Lee discloses the electro-acoustic module of claim 1. Lee further discloses the electro-acoustic module is manufactured having a chip-scale package including the acoustic stack, the at least one ASIC, and the interconnect ([0019], wafer-based interposer is provided for an ultrasound transducer, such as a matrix array ultrasound transducer, interposer chip is placed between acoustic elements and micro-beamforming ASICs).
Regarding claim 9, Lee method for manufacturing a line of ultrasound probes, the method comprising: obtaining at least one first application-specific integrated circuit (ASIC) having a first area along a plane perpendicular to a propagation direction of a first acoustic stack; and coupling a first interconnect of a plurality of interconnects to the at least one first ASIC, the plurality of interconnects having different fan-out architectures, wherein the first interconnect has a footprint corresponding to a first active aperture of a first ultrasound probe, and wherein the first active aperture of the first ultrasound probe is larger than the first area of the at least one first ASIC (Fig. 4, [0056], multiple interposers (12) may be provided corresponding to multiple ASICS (14A and (14B)) which are tiled side by side.)(Fig. 4 illustrates that the routing traces (See (12C) in Fig. 1) have differing fan out architecture between the two interposers.)(Fig. 4 illustrates that the interposers (12) each have a footprint corresponding to a respective active aperture of acoustic elements (10E) and are larger than the area of their corresponding ASIC (14A or 14B)).
Regarding claim 10, Lee discloses the method of claim 9. Lee further discloses coupling a second interconnect of the plurality of interconnects to at least one second ASIC, the second interconnect selected based on a second active aperture of a second ultrasound probe, the second active aperture larger than the first active aperture, and wherein a second area of the at least one second ASIC is equal to the first area of the at least one first ASIC, and the at least one second ASIC and the at least one first ASIC are of a common type (Implicit, Fig. 4, [0056], multiple interposers (12) may be provided corresponding to multiple ASICS (14A and (14B)) which are tiled side by side. Fig. 4 illustrates the integrated circuits are tiled with a 1-1 ratio between the interposers, however other ratios of tiling may be used)(Fig. 4 illustrates that the second interposer corresponding to ASIC (14B) corresponds to a second active aperture which is different from the first active aperture. Additionally Fig. 4 illustrates that ASICs (14A and 14B) have equal area).
Regarding claim 11, Lee discloses the method of claim 10. Lee further discloses the first ultrasound probe is of a different probe type than the second ultrasound probe ([0023] the acoustic module includes the acoustic array (10) which has transducer elements (10E) distributed in a grid over one or two dimensions. Multidimensional transducer array is an array of piezoelectric or microelectromechanical elements).
Regarding claim 12, Lee discloses the method of claim 9. Lee further discloses an acoustic stack of the first ultrasound probe is electrically coupled to the at least one first ASIC by arranging interposer bumps of an interposer of the acoustic stack in face-sharing contact with interconnect bumps of the first interconnect protruding from a top layer of the first interconnect, and arranging interconnect bumps protruding from a bottom layer of the first interconnect in face-sharing contact with ASIC bumps of the at least one first ASIC([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints (16) on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps)(Fig. 4 illustrates the same electrical joints (15 and 16) being present in the embodiment of Fig. 4 (see [0056]), which illustrates the acoustic elements being connected to the interposer via bumps protruding from the top surface of interposer (12) and the ASIC (14A and/or 14B) being connected to the Interposer via a second plurality of bumps protruding from a bottom surface of interposer (12)) .
Regarding claim 13, the method of claim 9, further comprising forming the first ultrasound probe as a chip-scale package by attaching an acoustic stack of the first ultrasound probe and the at least one first ASIC to the first interconnect using one or more of thermocompression bonding, soldering, conductive epoxy, and ultrasonic bonding([0019], wafer-based interposer is provided for an ultrasound transducer, such as a matrix array ultrasound transducer, interposer chip is placed between acoustic elements and micro-beamforming ASICs)([0069]-[0070] first electrical joints (Fig. 1 (16) are formed with solder reflow).
Regarding claim 14, Lee discloses the method of claim 9, wherein an assembly formed of the first interconnect coupled to the at least one first ASIC includes input/output (I/O) connections routed to a bottom side of the assembly(Implicit, Fig. 1, [0044] interposer (12) is a substrate bearing through-silicon-vias (12D). the core is made of silicon waver in the middle and high-density routing layers (12B) formed on either one surface or both surfaces of the silicon core)([0036] interposer has two opposing surfaces which include conductors such as I/O pads)(it is the examiner’s interpretation that the interposer I/O connections of the embodiment of Fig. 1 is implicitly included in the embodiment of Fig. 4 in which multiple interposers and ASICs are utilized).
Regarding claim 15, Lee discloses a plurality of ultrasound probes, comprising: active apertures of varying sizes amongst the plurality of ultrasound probes, wherein the plurality of ultrasound probes each incorporate at least one ASIC of a common size and type and an interconnect having a fan-out architecture, the at least one ASIC having a footprint equal to or less than a smallest active aperture of the plurality of ultrasound probes(Implicit, Fig. 4, [0056], multiple interposers (12) may be provided corresponding to multiple ASICS (14A and (14B)) which are tiled side by side. Fig. 4 illustrates the integrated circuits are tiled with a 1-1 ratio between the interposers, however other ratios of tiling may be used)(Fig. 4 illustrates that the second interposer corresponding to ASIC (14B) corresponds to a second active aperture which is different from the first active aperture. Additionally Fig. 4 illustrates that ASICs (14A and 14B) have equal area and are smaller in footprint when compared to the active area of the acoustic elements connected to the ASICs)(it is the examiner’s interpretation that the acoustic elements connected to a respective ASIC constitute their own probe).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lee et al. (US 20170238902 A1, “Lee 2”).
Regarding claim 7, Lee discloses the electro-acoustic module of claim 6. Lee may not explicitly teach the bottom layer of the interconnect further includes I/O connections arranged peripheral to the bumps of the bottom layer having the second pitch.
Lee 2 teaches the bottom layer of the interconnect further includes I/O connections arranged peripheral to the bumps of the bottom layer having the second pitch ([0032], ASIC may include one or more input-output connections along the periphery of the ASIC. Due to the presence of peripheral I/O connections at the periphery of the ASIC, the ASIC and Flex interconnect may be extended beyond the lateral size of the array aperture).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art of ultrasound probes, before the effective filing date of the claimed invention, to modify the electro-acoustic module of Lee, to include the interconnect I/O connections of Lee 2 with a reasonable expectation of success, with the motivation of allowing for flex interconnect to maintain a minimum bending radius to avoid failure due to trace breakage and to allow the housing to extend such that the transducer components are covered [0032].
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Wodnicki et al. (US 7892176 B2, “Wodnicki”).
Regarding claim 16, Lee discloses the plurality of ultrasound probes of claim 15. Lee may not explicitly teach a first ultrasound probe of the plurality of ultrasound probes has two or more electro-acoustic modules (EAMs) aligned along a plane perpendicular to a propagation direction of the first ultrasound probe, and wherein a first EAM of the two or more EAMs has a first element pitch that is the same or different from a second element pitch of a second EAM of the two or more EAMs.
Wodnicki teaches a first ultrasound probe of the plurality of ultrasound probes has two or more electro-acoustic modules (EAMs) aligned along a plane perpendicular to a propagation direction of the first ultrasound probe, and wherein a first EAM of the two or more EAMs has a first element pitch that is the same or different from a second element pitch of a second EAM of the two or more EAMs (Fig. 2, [column 3, lines 5-19], Probe unit (110) comprises a transducer assembly (101) having an array (103) of transducer cells (103). transducer cell array includes a plurality of subarrays (104), each subarray including a like number of transducer cells (103))(Fig. 2 illustrates various subarrays (104) arranged perpendicular to a propagation direction of the ultrasound probe)(Fig. 2 illustrates that the pitch of elements (103) within subarrays (104) are the same across multiple subarrays).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art of ultrasound probes, before the effective filing date of the claimed invention, to modify the ultrasound probes of Lee, to include the multiple EAM modules with same pitch of Wodnicki with a reasonable expectation of success, with the motivation of allowing the transducer modules to be tiled uniformly to prevent significant variations in spacings between modules and preventing significant caps between cells in adjoining arrays [column 6, lines 43-50].
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Tkacyzk et al, (US 20120133001 A1, “Tkacyzk”).
Regarding claim 17, Lee discloses the plurality of ultrasound probes of claim 15. Lee may not explicitly disclose the at least one ASIC has through-silicon vias, and wherein additional ASICs are coupled to the at least one ASIC by the through-silicon vias.
Tkaczyk teaches the at least one ASIC has through-silicon vias, and wherein additional ASICs are coupled to the at least one ASIC by the through-silicon vias ([0033] the integrated circuit includes one or more through vias disposed therethrough. The through silicon vias provide vertical connection that passes completely through the silicon wafer and is configured to aid in coupling devices in a package while reducing footprint of the package).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art of ultrasound probes, before the effective filing date of the claimed invention, to modify the ultrasound probes of Lee, to include the silicon via ASIC connections of Tkacyzk with a reasonable expectation of success, with the motivation of aiding in coupling devices in a package while reducing footprint of the package [0033].
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Wodnicki et al. (US 20200046320 A1, “Wodnicki 2”).
Regarding claim 18, Lee discloses the plurality of ultrasound probes of claim 15. Lee may not explicitly disclose a second ultrasound probe of the plurality of ultrasound probes includes a thermal substrate coupled to a bottom face of the at least one ASIC.
Wodnicki 2 teaches a second ultrasound probe of the plurality of ultrasound probes includes a thermal substrate coupled to a bottom face of the at least one ASIC (Fig. 4, [0061], ASIC (142) is coupled to interposer (132) via bonding interface (441). ASIC includes an ASIC substrate (441). ASIC substrate can have an array of pads which have been bumped with low temperature conducting adhesive beforehand).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art of ultrasound probes, before the effective filing date of the claimed invention, to modify the ultrasound probes of Lee, to include the thermal substrate of Wodnicki 2 with a reasonable expectation of success, with the motivation of creating Ohmic contact between the interposer and ASIC substrate [0062].
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Wodnicki et al. (US 20110071397 A1, “Wodnicki 3”) and Wodnicki 2.
Regarding claim 19, Lee discloses the plurality of ultrasound probes of claim 15. Lee may not explicitly teach a third ultrasound probe of the plurality of ultrasound probes has one or more EAMs are coupled to a common thermal substrate, each of the one or more EAMs including the at least one ASIC, and wherein the common thermal substrate has electronic islands spaced apart by the footprint of the at least one ASIC, the electronic islands configured to provide electrical continuity through the common thermal substrate.
Wodnicki 3 teaches a third ultrasound probe of the plurality of ultrasound probes has one or more EAMs are coupled to a common substrate, each of the one or more EAMs including the at least one ASIC, and wherein the common substrate has electronic islands spaced apart by the footprint of the at least one ASIC, the electronic islands configured to provide electrical continuity through the common substrate (Fig. 8, [0058]-[0060], transducer assembly includes multiple tileable modules (805). Individual transducer arrays (815) have multiple cells (820) that are separated by gaps (830) and are flip -chip bonded to the interposer (840). Integrated circuits are bonded to the interposer on the opposite side of the transducer arrays. BGA balls (855) are used to couple the interposer to substrate (860)(Fig. 8 illustrates 4 ASICs (850) and 4 transducer arrays (815) that are connected to one another through the interposers (840). The bump pitch connecting the ASIC to the interposers is less than the bump pitch connecting the interposer to the transducer arrays, indicating that the interposer has a fan-out architecture)(Fig. 8 illustrates all ASICs (850) are connected to a common substrate (860))(it is the examiner’s interpretation that the BGA balls act as electronic islands, separating the various ASICs).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art of ultrasound probes, before the effective filing date of the claimed invention, to modify the ultrasound probes of Lee, to include the third probe with enclosed ASIC surrounded by electronic islands of Wodnicki 3 with a reasonable expectation of success, with the motivation of providing electrical coupling between the tileable modules, interposer, ASIC, and substrate [0060].
Lee, as modified in view of Wodnicki 3 may not explicitly teach a thermal substrate.
Wodnicki 2 teaches(Fig. 4, [0061], ASIC (142) is coupled to interposer (132) via bonding interface (441). ASIC includes an ASIC substrate (441). ASIC substrate can have an array of pads which have been bumped with low temperature conducting adhesive beforehand)
Therefore, it would have been prima facie obvious to one of ordinary skill in the art of ultrasound probes, before the effective filing date of the claimed invention, to modify the ultrasound probes of Lee, as modified in view of Wodnicki 3, to include the thermal substrate of Wodnicki 2 with a reasonable expectation of success, with the motivation of creating Ohmic contact between the interposer and ASIC substrate [0062].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Wodnicki 3.
Regarding claim 20, Lee discloses the plurality of ultrasound probes of claim 15. Lee may not explicitly disclose a fourth ultrasound probe of the plurality of ultrasound probes includes an EAM with the interconnect having the fan-out architecture, peripheral layers, the peripheral layers surrounding a perimeter of the at least one ASIC, and a bottom layer extending across a bottom of the EAM, the bottom layer enclosing the at least one ASIC within the interconnect and having I/O connections protruding outwards therefrom.
Wodnicki 3 teaches a fourth ultrasound probe of the plurality of ultrasound probes includes an EAM with the interconnect having the fan-out architecture, peripheral layers, the peripheral layers surrounding a perimeter of the at least one ASIC, and a bottom layer extending across a bottom of the EAM, the bottom layer enclosing the at least one ASIC within the interconnect and having I/O connections protruding outwards therefrom(Fig. 8, [0058]-[0060], transducer assembly includes multiple tileable modules (805). Individual transducer arrays (815) have multiple cells (820) that are separated by gaps (830) and are flip -chip bonded to the interposer (840). Integrated circuits are bonded to the interposer on the opposite side of the transducer arrays. BGA balls (855) are used to couple the interposer to substrate (860)(Fig. 8 illustrates 4 ASICs (850) and 4 transducer arrays (815) that are connected to one another through the interposers (840). The bump pitch connecting the ASIC to the interposers is less than the bump pitch connecting the interposer to the transducer arrays, indicating that the interposer has a fan-out architecture)(it is the examiner’s interpretation that the BGA balls are considered peripheral layers and surround the perimeter of the ASICs, with the substrate acting to enclose the ASICs within the interposer).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art of ultrasound probes, before the effective filing date of the claimed invention, to modify the ultrasound probes of Lee, to include the fourth probe with enclosed ASIC surrounded by peripheral layers of Wodnicki 3 with a reasonable expectation of success, with the motivation of providing electrical coupling between the tileable modules, interposer, ASIC, and substrate [0060].
Conclusion
Prior art made of record though not relied upon in the present basis of rejection are noted in the attached PTO 892 and include:
Wodnicki et al. (US 8742646 B2, “Wodnicki 4”) which discloses methods for ultrasound acoustic assembly manufacture
Wildes et al. (US 10347818 B2, “Wildes”) which discloses methods for manufacturing ultrasound transducers
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER RICHARD WALKER whose telephone number is (571)272-6136. The examiner can normally be reached Monday - Friday 7:30 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yuqing Xiao can be reached at 571-270-3603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER RICHARD WALKER/Examiner, Art Unit 3645
/YUQING XIAO/Supervisory Patent Examiner, Art Unit 3645