DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In the amendments filed May 22nd, 2026, the following has occurred: claims 1-2, 6-9, and 14-15 have been amended; claims 1-20 remain pending in this application.
Response to Arguments
Applicant's arguments filed May 22nd, 2026 have been fully considered but they are not persuasive. On pg. 2 of Applicant’s Remarks, Applicant argues that the current basis of rejection fails to teach the limitations of newly amended claims 1, 9, and 15 for the following reasons:
Lee fails to teach the interconnect having input/output connections outside of the active area
Lee 2 fails to remedy the deficiencies of newly amended claim 1, as Lee 2 only teaches one input/output connection of the interconnect
With respect to (1), the examiner agrees that Lee fails to teach the limitations of newly amended claim 1 requiring multiple input/output connections outside of an active area of the acoustic aperture, however Lee is not relied upon to teach those limitations. Rather, Lee 2 is introduced as teaching that limitation, as necessitated by Applicant’s amendments to the claim.
With respect to (2), the examiner respectfully disagrees that Lee 2 only teaches one input/output connection existing outside of the active area of the acoustic aperture. Firstly Lee 2 (See Lee 2 Spec. at [0029] and Fig. 2) teaches that the array aperture (227) has a lateral size corresponding to (228). Lee 2 (See Lee 2 Spec. at [0032] and Fig. 2) further teaches that the ASIC (216) may include one or more input-output (I/O connections (250) disposed along a periphery of the ASIC (216). The I/O connections are routed along the flex interconnect (212). Furthermore Fig. 2 of Lee 2 illustrates two different I/O connections (250) arranged along the periphery of the ASIC (216), as well as interconnect (212). The two I/O connections (250) extend outside of the lateral size (228), which correspond to the array aperture (227). Therefore Lee 2 teaches “the interconnect comprises input/output connection located outside of an active area of the electro-acoustic module”. The rejections of newly amended claims 1, 9, and 15 are maintained under 35 U.S.C. 103, as necessitated by Applicant’s amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210138506 A1, “Lee”) in view of Lee et al. (US 20170238902 A1, “Lee 2”).
Regarding claim 1, Lee discloses an electro-acoustic module, comprising:
an acoustic stack (Fig. 1 (10));
and at least one application-specific integrated circuit (ASIC) (Fig. 1 (14)) electrically coupled to the acoustic stack by an interconnect having a fan-out architecture(Fig. 1, [0023] acoustic array (10) is comprised of multiple transducer elements (10E) distributed over a grid in one or two dimensions. Interposer (12) provides high density signal routing and is placed between the acoustic array and a micro-beamforming ASIC (14));
wherein the electro-acoustic module has an active aperture substantially equal to an overall size of the electro-acoustic module in at least one or an azimuth and an elevation direction (Fig. 1 (10) illustrates the acoustic array being comprised of acoustic transducers (10E) that create an active aperture that is of substantially the same size as the electro-acoustic module in an azimuth direction).
Lee fails to teach
Wherein the interconnect comprises input/output connections located outside of an active area of the electro-acoustic module.
Lee 2 teaches
Wherein the interconnect (Fig. 2 (212)) comprises input/output connections (Fig. 2 (250)) located outside of an active area (Fig. 2 (228)) of the electro-acoustic module (Fig. 2 (210)) ([0032], ASIC may include one or more input-output connections along the periphery of the ASIC. Due to the presence of peripheral I/O connections at the periphery of the ASIC, the ASIC and Flex interconnect may be extended beyond the lateral size of the array aperture).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the electro-acoustic module of Lee, to include the teaching of Lee 2 in order to yield an electro-acoustic module having I/O connections between the interconnect and ASIC so that the lateral size of the ASIC and interconnect can be extended beyond the aperture of the array, enabling electrical coupling between the ASIC and processing unit for communication of ultrasonic signals. Making such a modification amounts to using a known technique to improve a similar device in the same way. See MPEP 2141.III KSR Rational (C).
Regarding claim 2, Lee, as modified in view of Lee 2, teaches the electro-acoustic module of claim 1. Lee further teaches
the interconnect is a multi-layer interposer, and wherein the input/output (I/O) connections are located along an underside of the interconnect, opposite of the acoustic stack (Fig. 1, [0044] interposer (12) is a substrate bearing through-silicon-vias (12D). the core is made of silicon waver in the middle and high-density routing layers (12B) formed on either one surface or both surfaces of the silicon core)([0036] interposer has two opposing surfaces which include conductors such as I/O pads).
Regarding claim 3, Lee, as modified in view of Lee 2 teaches the electro-acoustic module of claim 1. Lee further teaches
the interconnect is positioned between the acoustic stack and the at least one ASIC along a propagation direction of the electro-acoustic module (Fig. 1, [0022], interposer is positioned between the ASIC and the acoustic array)(the positioning of the acoustic array, interposer, and ASIC, is along a propagation direction of the electro-acoustic module);
and each layer of a plurality of layers of the interconnect has a bump pitch that is different from adjacent layers ([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps)(it can be seen in Fig. 1 that electrical joints of the various layers have different pitches).
Regarding claim 4, Lee, as modified in view of Lee 2 teaches the electro-acoustic module of claim 3. Lee further teaches
the bump pitch of each of the plurality of layers decreases in a direction from the acoustic stack to the at least one ASIC([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints (16) on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps)(Fig. 1 Illustrates that electrical joints of the various layers have different pitches, with the bump pitch of the electrical joints decreasing from the acoustic stack side to the ASIC side).
Regarding claim 5, Lee, as modified in view of Lee 2 teaches the electro-acoustic module of claim 1. Lee further teaches
an element pitch of the acoustic stack is larger than ASIC bump pitch of the at least one ASIC([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps)(Fig. 1 illustrates that the element pitch of acoustic elements (10E) is larger than the ASIC bump pitch of electrical joints (16)).
Regarding claim 6, Lee, as modified in view of Lee 2 teaches the electro-acoustic module of claim 1. Lee further teaches
wherein the interconnect has bumps protruding outwards from a top layer of the interconnect within the active area([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps) (Fig. 7 illustrates electrical joints (15) being positioned within the active region corresponding to the acoustic stack),
the bumps of the top layer having a first pitch corresponding to an element pitch of the acoustic stack, and bumps protruding outwards from a bottom layer of the interconnect, the bumps of the bottom layer having a second pitch corresponding to an ASIC bump pitch of the at least one ASIC([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps)(Fig. 1 illustrates that the element pitch of acoustic elements (10E) matches the bump pitch of the first electrical joints (15) and the ASIC bump pitch of electrical joints (16) have a second pitch corresponding to the ASIC).
Regarding claim 7, Lee, as modified in view of Lee 2 teaches the electro-acoustic module of claim 6. Lee 2 teaches the bottom layer of the interconnect further includes I/O connections arranged outside the active area and peripheral to the bumps of the bottom layer having the second pitch ([0032], ASIC may include one or more input-output connections along the periphery of the ASIC. Due to the presence of peripheral I/O connections at the periphery of the ASIC, the ASIC and Flex interconnect may be extended beyond the lateral size of the array aperture)(Fig. 2 illustrates I/O connections (250) being positioned peripheral to ASIC bumps (248)).
Regarding claim 8, Lee, as modified in view of Lee 2 teaches the electro-acoustic module of claim 1. Lee further teaches
the electro-acoustic module is manufactured having a chip-scale package including the acoustic stack, the at least one ASIC, and the interconnect integrally packaged therewith ([0019], wafer-based interposer is provided for an ultrasound transducer, such as a matrix array ultrasound transducer, interposer chip is placed between acoustic elements and micro-beamforming ASICs)(making the acoustic stack, the at least one ASIC, and the interconnect integrally packaged is an obvious matter of design choice and one having ordinary skill in the art would have sufficient motivation to do so for the reasons of reducing manufacturing complexity/cost, among others. See MPEP 2144.04 (V)(B) and In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965)).
Regarding claim 9, Lee discloses a method for manufacturing a line of ultrasound probes, the method comprising:
obtaining at least one first application-specific integrated circuit (ASIC) having a first area along a plane perpendicular to a propagation direction of a first acoustic stack;
and coupling a first interconnect of a plurality of interconnects in an active area to the at least one first ASIC, the plurality of interconnects having different fan-out architectures, wherein the first interconnect has a footprint corresponding to a first active aperture of a first ultrasound probe, and wherein the first active aperture of the first ultrasound probe is larger than the first area of the at least one first ASIC (Fig. 4, [0056], multiple interposers (12) may be provided corresponding to multiple ASICS (14A and (14B)) which are tiled side by side.)(Fig. 4 illustrates that the routing traces (See (12C) in Fig. 1) have differing fan out architecture between the two interposers.)(Fig. 4 illustrates that the interposers (12) each have a footprint corresponding to a respective active aperture of acoustic elements (10E) and are larger than the area of their corresponding ASIC (14A or 14B)).
Lee fails to teach
Wherein an assembly formed of the first interconnect coupled to the at least one first ASIC includes input/output (I/O) connections arranged outside of the active area.
Lee 2 teaches
Wherein an assembly formed of the first interconnect coupled to the at least one first ASIC includes input/output (I/O) connections arranged outside of the active area([0032], ASIC may include one or more input-output connections along the periphery of the ASIC. Due to the presence of peripheral I/O connections at the periphery of the ASIC, the ASIC and Flex interconnect may be extended beyond the lateral size of the array aperture)( Fig. 2 illustrates two different I/O connections (250) arranged along the periphery of the ASIC (216), as well as interconnect (212). The two I/O connections (250) extend outside of the lateral size (228), which correspond to the array aperture (227))
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the method of Lee, to include the teaching of Lee 2 in order to yield an ultrasonic probe having I/O connections between the interconnect and ASIC so that the lateral size of the ASIC and interconnect can be extended beyond the aperture of the array, enabling electrical coupling between the ASIC and processing unit for communication of ultrasonic signals. Making such a modification amounts to using a known technique to improve a similar method in the same way. See MPEP 2141.III KSR Rational (C).
Regarding claim 10, Lee, as modified in view of Lee 2 teaches the method of claim 9. Lee further teaches
coupling a second interconnect of the plurality of interconnects to at least one second ASIC, the second interconnect selected based on a second active aperture of a second ultrasound probe, the second active aperture larger than the first active aperture Implicit, Fig. 4, [0056], multiple interposers (12) may be provided corresponding to multiple ASICS (14A and (14B)) which are tiled side by side. Fig. 4 illustrates the integrated circuits are tiled with a 1-1 ratio between the interposers, however other ratios of tiling may be used),
and wherein a second area of the at least one second ASIC is equal to the first area of the at least one first ASIC, and the at least one second ASIC and the at least one first ASIC are of a common type (Implicit, Fig. 4, [0056], multiple interposers (12) may be provided corresponding to multiple ASICS (14A and (14B)) which are tiled side by side. Fig. 4 illustrates the integrated circuits are tiled with a 1-1 ratio between the interposers, however other ratios of tiling may be used)(Fig. 4 illustrates that the second interposer corresponding to ASIC (14B) corresponds to a second active aperture which is different from the first active aperture. Additionally Fig. 4 illustrates that ASICs (14A and 14B) have equal area).
Regarding claim 11, Lee, as modified in view of Lee 2 teaches the method of claim 10. Lee further teaches
the first ultrasound probe is of a different probe type than the second ultrasound probe ([0023] the acoustic module includes the acoustic array (10) which has transducer elements (10E) distributed in a grid over one or two dimensions. Multidimensional transducer array is an array of piezoelectric or microelectromechanical elements).
Regarding claim 12, Lee, as modified in view of Lee 2 teaches the method of claim 9. Lee further teaches
an acoustic stack of the first ultrasound probe is electrically coupled to the at least one first ASIC by arranging interposer bumps of an interposer of the acoustic stack in face-sharing contact with interconnect bumps of the first interconnect protruding from a top layer of the first interconnect([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints (16) on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps) (Fig. 4 illustrates the same electrical joints (15 and 16) being present in the embodiment of Fig. 4 (see [0056]), which illustrates the acoustic elements being connected to the interposer via bumps protruding from the top surface of interposer (12) and the ASIC (14A and/or 14B) being connected to the Interposer via a second plurality of bumps protruding from a bottom surface of interposer (12)),
and arranging interconnect bumps protruding from a bottom layer of the first interconnect in face-sharing contact with ASIC bumps of the at least one first ASIC([0059], electrical joints (15) on the array facing surfaces are larger than the electrical joints (16) on the opposing surface facing the integrated circuit. The electrical joints may be solder balls, copper pillar bumps, or Au plated bumps)(Fig. 4 illustrates the same electrical joints (15 and 16) being present in the embodiment of Fig. 4 (see [0056]), which illustrates the acoustic elements being connected to the interposer via bumps protruding from the top surface of interposer (12) and the ASIC (14A and/or 14B) being connected to the Interposer via a second plurality of bumps protruding from a bottom surface of interposer (12)) .
Regarding claim 13, Lee as modified in view of Lee 2 teacehs the method of claim 9. Lee further teaches
forming the first ultrasound probe as a chip-scale package by attaching an acoustic stack of the first ultrasound probe and the at least one first ASIC to the first interconnect using one or more of
Regarding claim 14, Lee, as modified in view of Lee 2 teaches the method of claim 9. Lee further teaches
The input/output (I/O) connections routed to a bottom side of the assembly(Implicit, Fig. 1, [0044] interposer (12) is a substrate bearing through-silicon-vias (12D). the core is made of silicon waver in the middle and high-density routing layers (12B) formed on either one surface or both surfaces of the silicon core)([0036] interposer has two opposing surfaces which include conductors such as I/O pads).
Regarding claim 15, Lee discloses a plurality of ultrasound probes, comprising:
active apertures of varying sizes amongst the plurality of ultrasound probes(Fig. 4 illustrates that the second interposer (12) corresponding to ASIC (14B) corresponds to a second active aperture which is different from the first active aperture).,
wherein the plurality of ultrasound probes each incorporate at least one ASIC of a common size and type and an interconnect having a fan-out architecture with bumps in an active area and
Lee fails to teach
Input/output connections outside of the active area
Lee 2 teaches
Input/output connections outside of the active area([0032], ASIC may include one or more input-output connections along the periphery of the ASIC. Due to the presence of peripheral I/O connections at the periphery of the ASIC, the ASIC and Flex interconnect may be extended beyond the lateral size of the array aperture)( Fig. 2 illustrates two different I/O connections (250) arranged along the periphery of the ASIC (216), as well as interconnect (212). The two I/O connections (250) extend outside of the lateral size (228), which correspond to the array aperture (227))
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the ultrasound probes of Lee, to include the teaching of Lee 2 in order to yield an ultrasonic probe having I/O connections between the interconnect and ASIC so that the lateral size of the ASIC and interconnect can be extended beyond the aperture of the array, enabling electrical coupling between the ASIC and processing unit for communication of ultrasonic signals. Making such a modification amounts to using a known technique to improve a similar device in the same way. See MPEP 2141.III KSR Rational (C).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lee 2 and Wodnicki et al. (US 7892176 B2, “Wodnicki”).
Regarding claim 16, Lee, as modified in view of Lee 2 teaches the plurality of ultrasound probes of claim 15. Lee, as modified in view of Lee 2 fails to teach
a first ultrasound probe of the plurality of ultrasound probes has two or more electro-acoustic modules (EAMs) aligned along a plane perpendicular to a propagation direction of the first ultrasound probe,
and wherein a first EAM of the two or more EAMs has a first element pitch that is the same or different from a second element pitch of a second EAM of the two or more EAMs.
Wodnicki teaches a first ultrasound probe of the plurality of ultrasound probes has two or more electro-acoustic modules (EAMs) aligned along a plane perpendicular to a propagation direction of the first ultrasound probe(Fig. 2, [column 3, lines 5-19], Probe unit (110) comprises a transducer assembly (101) having an array (103) of transducer cells (103). transducer cell array includes a plurality of subarrays (104), each subarray including a like number of transducer cells (103)),
and wherein a first EAM of the two or more EAMs has a first element pitch that is the same
Therefore, it would have been prima facie obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify the ultrasound probes of Lee, as modified in view of the teachings of Lee 2, to further include the teachings of Wodnicki, in order to yield a plurality of ultrasound probes in which the transducer modules to be tiled uniformly to prevent significant variations in spacings between modules and preventing significant caps between cells in adjoining arrays. Making such a modification amounts to using a known technique to improve similar devices in the same way. See MPEP 2141.III KSR Rationale (C).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lee 2 and Tkacyzk et al, (US 20120133001 A1, “Tkacyzk”).
Regarding claim 17, Lee, as modified in view of Lee 2 teaches the plurality of ultrasound probes of claim 15. Lee, as modified in view of Lee 2 fails to teach
the at least one ASIC has through-silicon vias, and wherein additional ASICs are coupled to the at least one ASIC by the through-silicon vias.
Tkaczyk teaches
the at least one ASIC has through-silicon vias, and wherein additional ASICs are coupled to the at least one ASIC by the through-silicon vias ([0033] the integrated circuit includes one or more through vias disposed therethrough. The through silicon vias provide vertical connection that passes completely through the silicon wafer and is configured to aid in coupling devices in a package while reducing footprint of the package).
Therefore, it would have been prima facie obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify the ultrasound probes of Lee, as modified in view of the teachings of Lee 2, to further include the teachings of Tkaczyk, in order to yield a plurality of ultrasound probes which are more compact due to the overall footprint of the package being reduced through efficient coupling of devices in the package. Making such a modification amounts to combining prior art elements according to known methods to yield predictable results. See MPEP 2141.III KSR Rationale (A).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lee 2 and Wodnicki et al. (US 20200046320 A1, “Wodnicki 2”).
Regarding claim 18, Lee, as modified in view of Lee 2 teaches the plurality of ultrasound probes of claim 15. Lee, as modified in view of Lee 2 fails to teach
a second ultrasound probe of the plurality of ultrasound probes includes a thermal substrate coupled to a bottom face of the at least one ASIC.
Wodnicki 2 teaches
a second ultrasound probe of the plurality of ultrasound probes includes a thermal substrate coupled to a bottom face of the at least one ASIC (Fig. 4, [0061], ASIC (142) is coupled to interposer (132) via bonding interface (441). ASIC includes an ASIC substrate (441). ASIC substrate can have an array of pads which have been bumped with low temperature conducting adhesive beforehand).
Therefore, it would have been prima facie obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify the ultrasound probes of Lee, as modified in view of the teachings of Lee 2, to further include the teachings of Wodnicki 2 , in order to yield a plurality of ultrasound probes with increased ohmic contact between the ASIC and interposer, allowing for better conductivity between the two. Making such a modification amounts to combining prior art elements according to known methods to yield predictable results. See MPEP 2141.III KSR Rationale (A).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lee 2, Wodnicki et al. (US 20110071397 A1, “Wodnicki 3”), and Wodnicki 2.
Regarding claim 19, Lee, as modified in view of Lee 2 teaches the plurality of ultrasound probes of claim 15. Lee, as modified in view of Lee 2 fails to teach
a third ultrasound probe of the plurality of ultrasound probes has one or more EAMs are coupled to a common thermal substrate, each of the one or more EAMs including the at least one ASIC,
and wherein the common thermal substrate has electronic islands spaced apart by the footprint of the at least one ASIC, the electronic islands configured to provide electrical continuity through the common thermal substrate.
Wodnicki 3 teaches a third ultrasound probe of the plurality of ultrasound probes has one or more EAMs are coupled to a common
and wherein the common
Therefore, it would have been prima facie obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify the ultrasound probes of Lee, as modified in view of the teachings of Lee 2, to further include the teachings of Wodnicki 3 , in order to yield a plurality of ultrasound probes providing more efficient electrical coupling between the tileable modules, interposer, ASIC, and substrate, thus improving the overall operation of the probes. Making such a modification amounts to combining prior art elements according to known methods to yield predictable results. See MPEP 2141.III KSR Rationale (A).
Lee, as modified in view of Wodnicki 3 may not explicitly teach a thermal substrate.
Wodnicki 2 teaches
a thermal substrate (Fig. 4, [0061], ASIC (142) is coupled to interposer (132) via bonding interface (441). ASIC includes an ASIC substrate (441). ASIC substrate can have an array of pads which have been bumped with low temperature conducting adhesive beforehand)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify the ultrasound probes of Lee, as modified in view of the teachings of Lee 2 and Wodnicki 3, to further include the teachings of Wodnicki 2 , in order to yield a plurality of ultrasound probes with increased ohmic contact between the ASIC and interposer, allowing for better conductivity between the two. Making such a modification amounts to combining prior art elements according to known methods to yield predictable results. See MPEP 2141.III KSR Rationale (A).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lee 2 and Wodnicki 3.
Regarding claim 20, Lee, as modified in view of Lee 2 teaches the plurality of ultrasound probes of claim 15. Lee, as modified in view of Lee 2 fails to teach
a fourth ultrasound probe of the plurality of ultrasound probes includes an EAM with the interconnect having the fan-out architecture, peripheral layers, the peripheral layers surrounding a perimeter of the at least one ASIC,
and a bottom layer extending across a bottom of the EAM, the bottom layer enclosing the at least one ASIC within the interconnect and having I/O connections protruding outwards therefrom.
Wodnicki 3 teaches
a fourth ultrasound probe of the plurality of ultrasound probes includes an EAM with the interconnect having the fan-out architecture, peripheral layers, the peripheral layers surrounding a perimeter of the at least one ASIC(Fig. 8, [0058]-[0060], transducer assembly includes multiple tileable modules (805). Individual transducer arrays (815) have multiple cells (820) that are separated by gaps (830) and are flip -chip bonded to the interposer (840). Integrated circuits are bonded to the interposer on the opposite side of the transducer arrays. BGA balls (855) are used to couple the interposer to substrate (860)(Fig. 8 illustrates 4 ASICs (850) and 4 transducer arrays (815) that are connected to one another through the interposers (840)),
and a bottom layer extending across a bottom of the EAM, the bottom layer enclosing the at least one ASIC within the interconnect and having I/O connections protruding outwards therefrom(Fig. 8 illustrates 4 ASICs (850) and 4 transducer arrays (815) that are connected to one another through the interposers (840). The bump pitch connecting the ASIC to the interposers is less than the bump pitch connecting the interposer to the transducer arrays, indicating that the interposer has a fan-out architecture)(the BGA balls are considered peripheral layers and surround the perimeter of the ASICs, with the substrate acting to enclose the ASICs within the interposer).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify the ultrasound probes of Lee, as modified in view of the teachings of Lee 2, to further include the teachings of Wodnicki 3 in order to yield a multi-probe assembly with a fourth probe comprising enclosed ASIC surrounded by peripheral layers, which provides enhanced electrical coupling between the tileable modules, interposer, ASIC, and substrate. Making such a modification amounts to combining prior art elements according to known methods in order to yield predictable results. See MPEP 2141.III KSR Rationale (A).
Conclusion
Prior art made of record though not relied upon in the present basis of rejection are noted in the attached PTO 892 and include:
Wodnicki et al. (US 8742646 B2, “Wodnicki 4”) which discloses methods for ultrasound acoustic assembly manufacture
Wildes et al. (US 10347818 B2, “Wildes”) which discloses methods for manufacturing ultrasound transducers
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER RICHARD WALKER whose telephone number is (571)272-6136. The examiner can normally be reached Monday - Friday 7:30 am - 5:00 pm.
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/CHRISTOPHER RICHARD WALKER/Examiner, Art Unit 3645
/YUQING XIAO/Supervisory Patent Examiner, Art Unit 3645
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