DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 02/18/2026. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 03/15/2023
Oath/Declaration
The oath or declaration filed on 01/25/2023 is acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/19/2026 and 01/27/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Election/Restrictions
Applicant’s election, without traverse Species I, directed to an embodiment as depicted in FIGS. [1], with claims 1-11, 17-18 and 20, in the “Response to Election / Restriction Filed” filed on 02/18/2026 is acknowledged. This office action considers claims 1-20 are thus pending for prosecution.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Naito (US 2020/0058803 A1; hereafter Naito) in view of MITSUZUKA et al (US 2020/0091329 A1; hereafter MITSUZUKA).
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Annotated Fig 1.
Regarding claim 1. Naito discloses a semiconductor device comprising:
a semiconductor substrate (Fig 1a, substrate 10, Para [ 0078]) that has a transistor portion (transistor portion 70, Para [ 0077]) and a diode portion (diode portion 64, Para [ 0103]) and that is provided with a plurality of trench portions (gate trench portion 40), wherein the transistor portion (transistor portion 70, Para [ 0077]) has:
an emitter region of a first conductivity type (n+ emitter regions 12, Para [ 0093]) provided at a front surface of the semiconductor substrate (Fig 1a, substrate 10, Para [ 0078]));
a base region (p-type base region 14, Para [ 0081]) of a second conductivity type provided in the semiconductor substrate (Fig 1a, substrate 10, Para [ 0081]); and
a contact region (p+ contact region 15, Para [ 0081]) of the second conductivity type (p+ contact region 15, Para [ 0081]) that is provided at the front surface of the semiconductor substrate (Fig 1a, substrate 10, Para [ 0078])) and that has a doping concentration higher than that of the base region (p-type base region 14, Para [ 0081]), the diode portion (diode portion 64, Para [ 0103]) has an anode region (third mesa portions 64 includes base region 14) of the second conductivity type ( p type) that is provided at the front surface of the semiconductor substrate (Fig 1a, substrate 10) and
the transistor portion (transistor portion 70, Para [ 0077]) has:
a main region (annotated main region) that has the emitter region (n+ emitter regions 12) and the contact region (p+ contact region 15, Para [ 0081]) at the front surface of the semiconductor substrate (Fig 1a, substrate 10, Para [ 0078]) and that is spaced apart from the diode portion (diode portion 64); and
a first boundary region (annotated first boundary region) that is provided between the main region (annotated main region) and the diode portion (diode portion 64) and that has, at the front surface of the semiconductor substrate (Fig 1a, substrate 10, Para [ 0078]), the emitter region (n+ emitter regions 12, Para [ 0093]) and the base region (p-type base region 14) which are alternately provided in a trench extension direction (extending portions 29, Para [ 0069]).
But Naito does not disclose explicitly anode region that has a doping concentration lower than that of the base region.
In a similar field of endeavor, MITSUZUKA discloses anode region that has a doping concentration lower than that of the base region (Fig 1, Para [0079] discloses “the doping concentration of the anode region 13 is lower than the doping concentration of the base region 14”).
Since Naito and MITSUZUKA are both from the similar field of endeavor, and MITSUZUKA discloses semiconductor chip including a transistor portion 70 and a diode portion 80. Therefore, the purpose disclosed by MITSUZUKA would have been recognized in the pertinent art of Naito. Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Naito in light of MITSUZUKA teaching “anode region that has a doping concentration lower than that of the base region (Fig 1, Para [0079] discloses “the doping concentration of the anode region 13 is lower than the doping concentration of the base region 14”)” for further advantage such as to increase the resistivity of the diode region.
Regarding claim 2. Naito and MITSUZUKA discloses the semiconductor device according to claim 1, Naito further discloses wherein the main region (annotated main region) has, at the front surface of the semiconductor substrate (Fig 1a, substrate 10, Para [ 0081]), the contact region (p+ contact region 15, Para [ 0081]) and the emitter region (n+ emitter regions 12, Para [ 0093]) alternately which are provided in the trench extension direction (extending portions 29, Para [ 0069]).
Regarding claim 3. Naito and MITSUZUKA discloses the semiconductor device according to claim 1, Naito further discloses wherein a lifetime control region (Fig 1b, lifetime control region 72) that includes a lifetime killer (Para [ 0074]) is not provided in a front surface side of the semiconductor substrate (Fig 1a, substrate 10, Para [ 0081]).
Regarding claim 4. Naito and MITSUZUKA discloses the semiconductor device according to claim 1, Naito further discloses wherein the transistor portion (transistor portion 70) has a second boundary region (annotated second boundary) provided between the first boundary region (annotated first boundary region) and the diode portion (diode portion 64), and the second boundary region (annotated second boundary) has the anode region (third mesa portions 64 includes base region 14) at the front surface of the semiconductor substrate (Fig 1a, substrate 10, Para [ 0081]).
Regarding claim 5. Naito and MITSUZUKA discloses the semiconductor device according to claim 2, Naito further discloses wherein the transistor portion (transistor portion 70) has a second boundary region (annotated second boundary) provided between the first boundary region (annotated first boundary region) and the diode portion (diode portion 64), and the second boundary region has the anode region (third mesa portions 64 includes base region 14) at the front surface of the semiconductor substrate (Fig 1a, substrate 10, Para [ 0081]).
Regarding claim 6. Naito and MITSUZUKA discloses the semiconductor device according to claim 1, Naito further discloses wherein each of the transistor portion (transistor portion 70, Para [ 0077]) and the diode portion (diode portion 64, Para [ 0103]) further has a trench contact portion ( contact hole 54, Para [ 0048]) provided at the front surface of the semiconductor substrate ( substrate 10, Para [ 0081]), and a lower end of the trench contact portion ( contact hole 54, Para [ 0048]) is shallower than a lower end of the emitter region (emitter region 12, Para [ 0093] ).
Regarding claim 7. Naito and MITSUZUKA discloses the semiconductor device according to claim 2, Naito further discloses wherein each of the transistor portion (transistor portion 70, Para [ 0077]) and the diode portion (diode portion 64, Para [ 0103]) further has a trench contact portion ( contact hole 54, Para [ 0048]) provided at the front surface of the semiconductor substrate ( substrate 10, Para [ 0081]), and a lower end of the trench contact portion ( contact hole 54, Para [ 0048]) is shallower than a lower end of the emitter region (emitter region 12, Para [ 0093] ).
Regarding claim 17. Naito and MITSUZUKA discloses the semiconductor device according to claim 1, Naito further discloses wherein the transistor portion further has an accumulation region (Fig 1, another N+ type region 12, Para [0081]) of the first conductivity type (Fig 1, another N+ type region 12, Para [0081]) provided in the semiconductor substrate (Fig 1a, substrate 10).
Regarding claim 18. Naito and MITSUZUKA discloses the semiconductor device according to claim 17, Naito further discloses wherein the accumulation region (Fig 1b, another N+ type region 12, Para [0081]) is not provided below the anode region (Fig 1b, third mesa portions 64 includes base region 14, Para [ 0012]).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Naito (US 2020/0058803 A1; hereafter Naito) in view of MITSUZUKA et al (US 2020/0091329 A1; hereafter MITSUZUKA) as applied claims above and further in view of NAITO (US 2017/0317175 A1; hereafter NAITO’175).
Regarding claim 8. Naito and MITSUZUKA discloses the semiconductor device according to claim 1, But Naito and MITSUZUKA does not disclose explicitly wherein each of the transistor portion (Fig 1, region 70, Para [ 0050]) and the diode portion further has a trench contact portion provided at the front surface of the semiconductor substrate, and a lower end of the trench contact portion has a same depth as a lower end of the emitter region.
In a similar field of endeavor, NAITO’175 discloses wherein each of the transistor portion (Fig 5, region 70, Para [ 0037]) and the diode portion ( Fig 5, region 80, Para [ 0037]) further has a trench contact portion ( contact hole 36, Para [ 01081]) provided at the front surface of the semiconductor substrate ( substrate 10, Para [ 0103]), and a lower end of the trench contact portion ( contact hole 36, Para [ 01081]) has a same depth ( substantially same depth, as shown in figure 5) as a lower end of the emitter region (emitter region 12, Para [ 0052]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Naito and MITSUZUKA in light of NAITO’175 teaching “wherein each of the transistor portion (Fig 5, region 70, Para [ 0037]) and the diode portion ( Fig 5, region 80, Para [ 0037]) further has a trench contact portion ( contact hole 36, Para [ 01081]) provided at the front surface of the semiconductor substrate ( substrate 10, Para [ 0103]), and a lower end of the trench contact portion ( contact hole 36, Para [ 01081]) has a same depth ( substantially same depth, as shown in figure 5) as a lower end of the emitter region (emitter region 12, Para [ 0052])” for further advantage such as to prevent the flow of the return current from the emitter side toward the collector side of the IGBT region.
Examiner like to note that, applicant has not presented persuasive evidence that the claimed “lower end of the trench contact portion has a same depth as a lower end of the emitter region” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed reduced width). Also, the applicant has not shown that the claimed lower end of the trench contact portion has a same depth as a lower end of the emitter region produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to optimize the” lower end of the trench contact portion has a same depth as a lower end of the emitter region” for further advantage such as to prevent the flow of the return current from the emitter side toward the collector side of the IGBT region. where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
Regarding claim 9. Naito and MITSUZUKA discloses the semiconductor device according to claim 2, But Naito and MITSUZUKA does not disclose explicitly wherein each of the transistor portion (Fig 1, region 70, Para [ 0050]) and the diode portion further has a trench contact portion provided at the front surface of the semiconductor substrate, and a lower end of the trench contact portion has a same depth as a lower end of the emitter region.
In a similar field of endeavor, NAITO’175 discloses wherein each of the transistor portion (Fig 5, region 70, Para [ 0037]) and the diode portion ( Fig 5, region 80, Para [ 0037]) further has a trench contact portion ( contact hole 36, Para [ 01081]) provided at the front surface of the semiconductor substrate ( substrate 10, Para [ 0103]), and a lower end of the trench contact portion ( contact hole 36, Para [ 01081]) has a same depth ( substantially same depth, as shown in figure 5) as a lower end of the emitter region (emitter region 12, Para [ 0052]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Naito and MITSUZUKA in light of NAITO’175 teaching “wherein each of the transistor portion (Fig 5, region 70, Para [ 0037]) and the diode portion ( Fig 5, region 80, Para [ 0037]) further has a trench contact portion ( contact hole 36, Para [ 01081]) provided at the front surface of the semiconductor substrate ( substrate 10, Para [ 0103]), and a lower end of the trench contact portion ( contact hole 36, Para [ 01081]) has a same depth ( substantially same depth, as shown in figure 5) as a lower end of the emitter region (emitter region 12, Para [ 0052])” for further advantage such as to prevent the flow of the return current from the emitter side toward the collector side of the IGBT region.
Examiner like to note that, applicant has not presented persuasive evidence that the claimed “lower end of the trench contact portion has a same depth as a lower end of the emitter region” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed reduced width). Also, the applicant has not shown that the claimed lower end of the trench contact portion has a same depth as a lower end of the emitter region produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. It would have been obvious to one of ordinary skill in the art, before the effective filing date, to optimize the” lower end of the trench contact portion has a same depth as a lower end of the emitter region” for further advantage such as to prevent the flow of the return current from the emitter side toward the collector side of the IGBT region. where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
Allowable Subject Matter
Claims 10-11 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 10. The semiconductor device according to claim 6, wherein each of the transistor portion and the diode portion further has a plug region of the second conductivity type that is provided at a bottom portion of the trench contact portion and that has a doping concentration higher than that of the base region.
Regarding claim 11. The semiconductor device according to claim 8, wherein each of the transistor portion and the diode portion further has a plug region of the second conductivity type that is provided at a bottom portion of the trench contact portion and that has a doping concentration higher than that of the base region.
Regarding claim 20. The semiconductor device according to claim 1, wherein the transistor portion further has a collector region of the second conductivity type provided on a back surface of the semiconductor substrate, the diode portion further has: a first cathode region of the first conductivity type provided on the back surface of the semiconductor substrate; and a second cathode region of the second conductivity type that is provided on the back surface of the semiconductor substrate and that has an area smaller than that of the first cathode region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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