DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, the limitations “a first partial heat dissipation portion” and “a second partial heat dissipation portion” are unclear in that they lack a clearly defined scope. The specification defines a first heat dissipation portion and a second heat dissipation portion, but never refers to them as being ‘partial’ so it is unclear as to what limitations the word partial is attempting to be brought into this claim limitation. It is recommended applicant instead claim (deleting the word ‘partial’) “a first heat dissipation portion” and “a second heat dissipation portion” which is described in the specification and would have a clear scope.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Hakuto et al (US Publication 20220263425) in view of Park et al (US Publication 20180174945).
Regarding claim 1, Hakuto teaches a semiconductor module comprising:
A plurality of semiconductor elements (Fig. 6, elements 21L, 21U, and 30);
a heat dissipation portion (Fig. 7, 140); and
a plurality of spacers that are provided between the plurality of semiconductor elements and the heat dissipation portion (Fig. 7, elements 162 and 161),
wherein the plurality of semiconductor elements dissipate heat from the heat dissipation portion via the plurality of spacers (Fig. 7, semiconductors 21 dissipate heat to 140 via 162 and 161)
the plurality of semiconductor elements includes a plurality of first semiconductor elements that form a first row and are, in plan view of the semiconductor module, arranged in a straight line, being spaced apart from each other at intervals along a surface of the heat dissipation portion (Fig. 11, row of elements 21L in straight line and spaced apart from each other at intervals along a surface of the heat dissipation portion 140 with layers between as shown in Fig. 7), and
a plurality of second semiconductor elements that form a second row and are, in plan view of the semiconductor module, arranged in a straight line, being spaced apart from each other at intervals along the surface of the heat dissipation portion, and in parallel with the first row (Fig. 11, row of elements 21U and 30 in straight line, spaced apart from each other at intervals along a surface of the heat dissipation portion 140 with layers between as shown in Fig. 7, and parallel to row of 21L), and
the plurality of second semiconductor elements are shifted in a direction of the second row with respect to the plurality of first semiconductor elements so that the plurality of second semiconductor elements and the plurality of first semiconductor elements are misaligned (Fig. 11. row of elements 21L misaligned with row of elements 21U and 30).
Hakuto does not specifically teach a connection area of each of the plurality of spacers where each of the plurality of spacers contacts the heat dissipation portion is larger than a connection area of each of the plurality of spacers where each of the plurality of spacers contacts the semiconductor element
Park teaches a connection area of each of the plurality of spacers where each of the plurality of spacers contacts the heat dissipation portion is larger than a connection area of each of the plurality of spacers where each of the plurality of spacers contacts the semiconductor element (Fig. 4, spacer 41 contact surface area near 120/d is larger than near semiconductor element 31, in the present application the heat dissipation portion 72 and spacers 76 are connected via solder (para 34 of the present application) similar to what can be seen in layers 70 between the elements, therefore the elements in Park are in contact with each other via 'solder' in a similar manner).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hakuto to include the spacers as taught by Park in order to improve the heat dissipation properties of the device.
Regarding claims 2-5, Hakuto as modified teaches the limitations of claim 1 upon which claims 2-5 depend.
Hakuto does not specifically teach
[claim 2] wherein a cross-sectional area of each of the plurality of spacers increases toward the heat dissipation portion.
[claim 3] wherein a cross-sectional area of each of the plurality of spacers increases in a stepwise manner toward the heat dissipation portion.
[claim 4] wherein each of the plurality of spacers is in surface-contact with a surface of the semiconductor element and the heat dissipation portion.
[claim 5] wherein each of the plurality of spacers is electrically conductive.
Park teaches:
[claim 2] wherein a cross-sectional area of each of the plurality of spacers increases toward the heat dissipation portion (Fig. 4, spacer 4, col3, lines 11-13).
[claim 3] wherein a cross-sectional area of each of the plurality of spacers increases in a stepwise manner toward the heat dissipation portion (col 6, lines 3-6).
[claim 4] wherein each of the plurality of spacers is in surface-contact with a surface of the semiconductor element and the heat dissipation portion (Fig. 4, 41 in contact with 120 and 31 via SMT solder joints).
[claim 5] wherein each of the plurality of spacers is electrically conductive (col 6, lines 1-2, copper).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hakuto to include the spacers as taught by Park in order to improve the thermal properties of the device.
Regarding claim 6, Hakuto as modified teaches the limitations of claim 1 upon which claim 6 depends.
Hakuto teaches a power terminal that is connected to a power line and overlaps part of the heat dissipation portion in plan view of the semiconductor module (Fig. 7 and 10, 113 connected to 152 and overlapping 140),
wherein the first row is disposed between the power terminal and the second row (Fig. 10, 21U elements between 21L and 30 elements and 113), and
the plurality of first semiconductor elements are fewer than the plurality of second semiconductor elements (Fig. 10, 8 21U elements and 9 21L and 30 elements).
Regarding claim 7, Hakuto as modified teaches the limitations of claim 1 upon which claim 7 depends.
Hakuto teaches a conductive portion, wherein the plurality of second semiconductor elements are disposed between the plurality of first semiconductor elements and the conductive portion (Fig. 10, conductive portion 165 with 21L disposed between 21U and 165),
each of the plurality of first semiconductor elements is connected to the conductive portion via a first signal line that is routed between the plurality of second semiconductor elements (Fig. 11, 21L and 21U connected to 165 via 172), and
each of the plurality of second semiconductor elements is connected to the conductive portion via a second signal line (Fig. 11, 21U elements connected to 165 via 172).
Regarding claim 8, Hakuto as modified teaches the limitations of claim 1 upon which claim 8 depends.
Hakuto teaches wherein the plurality of semiconductor elements are divided into a first semiconductor element group and a second semiconductor element group that is disposed, in plan view of the semiconductor module, at a site different from a site of the first semiconductor element group (Fig. 10, 21U elements first group, 21L and 30 elements second group, first and second groups disposed at different sites in plan view of module),
each of the first semiconductor element group and the second semiconductor element group includes the plurality of first semiconductor elements forming the first row and the plurality of second semiconductor elements forming the second row (Fig. 10, first semiconductor element group 21U and second semiconductor element group 21L in rows along y axis),
the semiconductor module further comprises a plurality of connecting portions that are disposed between the first semiconductor element group and the second semiconductor element group (Fig. 10, first group 21U in row, second group 21L and 30 in row, and connecting portions 165 and 172),
a first partial heat dissipation portion that is provided between the plurality of spacers and the heat dissipation portion and covers, in plan view of the semiconductor module, the first semiconductor element group and one of the plurality of connecting portions (Fig. 7 and 10, 151 between 140 and 162, 151 covers elements 21 and 165), and
a second partial heat dissipation portion that is provided between the plurality of spacers and the heat dissipation portion and covers, in plan view of the semiconductor module, the second semiconductor element group and another one of the plurality of connecting portions (Fig. 7 and 10, 153 between 140 and 161, 151 covers elements 21 and 65).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818