DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/25/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of claims 1 through 10 in the reply filed on 2/2/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Okamoto (US 2025/0329352, JP 2022-151378)
Regarding claim1.
Okamoto teaches:
A method for forming a stacked semiconductor device (fig 2:10; [para 0138]),
the method comprising: forming a plurality of stacked dies (fig 2:20; [para 0138]),
the plurality of stacked dies comprising: a bottom die (fig 1,2:50; [para 0134]) comprising a first die type;
a plurality of upper dies (fig 2:40; [para 0109]) comprising a second die type different than the first die type;
and a facilitator die (fig 2:30; [para 0120]) comprising a third die type different than the first die type and the second die type;
and forming at least one of a signal connection (fig 1,2:SA_GBL,LBL; [para 0084,0127]) and a power distribution line hierarchically between the bottom die (fig 2:50; [para 0134]), the plurality of upper dies (fig 2:40; [para 0109]), and the facilitator die (fig 2:30; [para 0120]),
wherein connections between the bottom die (fig 2:50; [para 0134]) and the facilitator die (fig 2:30; [para 0120]) comprise a first hierarchical level (fig,1:SA_GBL; [para 0127])
and connections between the facilitator die (fig 2:30; [para 0120]) and one or more of the plurality of upper dies (fig 2:40; [para 0109]) comprise a second hierarchical level (fig 1,2:LBL; [para 0121]).
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Regarding claim 9.
Okamoto teaches the method of claim 1, further comprising:
forming a local memory (fig 10:94; [para 0230]) on the facilitator die (fig 10:30; [para 0233]),
the local memory (fig 10:94; [para 0230]) configured to receive request and data signals from the bottom die (fig 10:50; [para 0233]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) as applied to claim 1 in view of Kwon (US 2018/0226108).
Regarding claim 2
Okamoto teaches the method of claim 1, further:
Okamoto teaches:
forming a global power line (fig 2:SA_GBL; [para 0084,0142])
the global power line (fig 2:SA_GBL; [para 0084,0142]) coupled to the bottom die (fig 2:50; [para 0107]) and the facilitator die (fig 2:30; [para 00108]) in the first hierarchical level;
forming a local power line (fig 2:LBL; [para 0084,0109]) ,
the local power line (fig 2:LBL; [para 0084,0109]) coupled to the facilitator die (fig 2:30; [para 00108]) and one or more of the plurality of upper dies (fig 2:40; [para 00109]) in the second hierarchical level;
.
Okamoto does not teach a voltage converter
Kwon teaches:
a global power line comprising a first voltage (fig 14:1.8V; [para 0149]),
the global power line coupled to the bottom die (fig 14:120; [para 0149]) and the facilitator die (fig 14:113c; [para 0148]) in the first hierarchical level;
forming a local power line comprising a second voltage (fig 14:1.2V; [para 0150]) less than the first voltage (fig 14:1.8V; [para 0149]),
the local power line coupled to the facilitator die (fig 14:113c; [para 0148]) and one or more of the plurality of upper dies (fig 14:DIE1-8; [para 0148]) in the second hierarchical level;
and forming a voltage converter (fig 14:160; [para 0153]) on the facilitator die (fig 14:113c; [para 0148]),
the voltage converter (fig 14:160; [para 0153]) coupled to the global power line and the local power line (fig 14).
It would have been obvious to one of ordinary skill in the art to provide a voltage converter in order to provide the driving voltage required by the memory unit (paragraph 153).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) as applied to claim 1 and further in view of Kwon (US 2018/0226108)
Regarding claim 3.
Okamoto teaches the method of claim 1, further comprising:
forming a global signal line (fig 2:SA_GBL; [para 0084,0142]) coupled to the bottom die (fig 2:50; [para 0134]) and the facilitator die (fig 2:30; [para 0120]) in the first hierarchical level (fig 1,2);
forming a local signal bus (fig 2:LBL; [para 0109]) coupled to the facilitator die (fig 2:30; [para 0120])
and one or more of the plurality of upper dies (fig 2:40; [para 0109]) in the second hierarchical level (fig 1,2);
Okamoto does not teach a serializer
Kwon teaches:
forming a serializer (fig 7:117; [para 0109]) on the facilitator die (fig 7:113a; [para 0109]),
the serializer (fig 7:117; [para 0109]) coupled to the global signal line (fig 7:DATA; [para 0108]) and the local signal bus (fig 7:DQS; [para 0112]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a seiralizer so that the data realignment circuit may interface communications between the controller operating at high frequency and the memory chips at low frequency (paragraph 90).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) as applied to claim 1 and further in view of Seok (US 2015/0373848) in view of Kwon (US 2018/0226108).
Regarding claim 4.
Okamoto teaches the method of claim 1, further:
Okamoto teaches the bottom die (fig 2,50; [para 0134]) and the facilitator die (fig 2:30; [para 0120]) in the first hierarchical level;
Okamoto does not teach a common signal line.
Seok teaches:
a common signal line (fig 6: [para 0064]) comprising a fly-by-signal (address, control, and clock signals are combined; [para 0064]),
the common signal line coupled to the facilitator die (fig 6:630; [para 0064]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a common signal line in order that the command, the address, the control signal, and the clock signal, output can be combined into one line thereby reducing the number of lines to be formed (paragraph 64).
Okamoto does not teach ESD protection.
Kwon teaches:
forming an electrostatic discharge (ESD) protection circuit (fig 16:174; [para 0168]) on the facilitator die (fig 16:170; [para 0168]),
the ESD protection circuit (fig 16:174; [para 0168]) coupled to the signal line (fig 16:CH_1; [para 0166]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide ESD protection in order to prevent damage from static discharges.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) as applied to claim 1 and further in view of Pawlowski (US 2021/0200632)
Regarding claim 5.
Okamoto teaches the method of claim 1,
Okamoto teaches:
wherein the first hierarchical level and the second hierarchical level (fig 1,2)
Okamoto does not teach a redrive configuration.
Pawlowski teaches:
a stacked semiconductor die method (fig 1; [para 0015]) comprise a redrive configuration (fig 2; [para 0021].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a redrive configuration in order to drive signals to and from the memory dies (paragraph 21)
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) as applied to claim 1 and further in view of Hollis (US 2012/0051152)
Regarding claim 6.
Okamoto teaches the method of claim 1,
Okamoto teaches:
wherein the first hierarchical level and the second hierarchical level (fig 1,2)
Okamoto does not teach a two-level tree configuration.
Hollis teaches:
a two-level tree configuration (fig 4; [para 0036,0037]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide two level tree hierarchy because the additional levels of hierarchy enable lower capacitance at the lower levels of the hierarchy tree (paragraph 37).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) as applied to claim 1 and further in view of Hollis (US 2012/0051152)
Regarding claim 7.
Okamoto teaches the method of claim 1,
Okamoto teaches:
wherein the first hierarchical level and the second hierarchical level (fig 1,2)
Okamoto does not teach a both end configuration.
Hollis teaches:
a both-end drive configuration (fig 3; [para 0031,0032]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the memory for both ends in order to increase throughput using bidirectional communication (paragraph 33).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) as applied to claim 1 and further in view of Jayasena (US 2022/0413849)
Regarding claim 8.
Okamoto teaches the method of claim 1, further:
(fig 2:30; [para 0120]),
(fig 2,50; [para 0134]),
and transmit memory data to an upper die (fig 2:41[m]; [para 109]) of the plurality of upper dies (fig 2:40; [para 0109]).
Okamoto does not teach near memory computing.
Jayasena teaches:
forming a near memory processor (fig 2:142; [para 0033]),
the near memory processor (fig 2:142; [para 0033]) configured to receive an execution code (fig 2:232[0036]),
process the execution code, and transmit memory data to memory (fig 2:128; [para 0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that near memory processing can save time by reducing external communications (i.e., host to memory device communications) and can also conserve power (paragraph 1).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) as applied to claim 1 and further in view of Vergis (US 2018/0061478)
Regarding claim 10.
Okamoto teaches the method of claim 1,
Okamoto teaches further comprising:
forming the facilitator die (fig 2:30; [para 0120]),
configured to receive data from the bottom die (fig 2,50; [para 0134]), and transmit memory data to an upper die (fig 2:41[m]; [para 109]) of the plurality of upper dies (fig 2:40; [para 00109]).
Okamoto does not teach the facilitator die comprises a controller.
Vergis teaches:
forming a memory controller (fig 1:150; [para 0038])on the facilitator (fig 1:140; [para 0038]),
the memory controller (fig 1:150; [para 0038]) configured to receive data, process the data, and transmit memory data ([para 0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a memory controller in the memory device in order to configure the internal execution of commands for the connected memory die.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 7, 2026