DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 10 rejected, claims 11 through 20 withdrawn
Present action: claims 1 through 10 rejected, claims 11 through 20 withdrawn
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 6, 7, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) in view of Hollis (US 2012/0051152)
Regarding claim 1.
Okamoto teaches:
A method for forming a stacked semiconductor device (fig 2:10; [para 0138]), the method comprising:
forming a plurality of stacked dies (fig 2:20; [para 0138]), the plurality of stacked dies (fig 2:20; [para 0138]) comprising: a bottom die (fig 1,2:50; [para 0134]) comprising a first die type ([para 0127]);
a plurality of upper dies (fig 2:40; [para 0109]) comprising a second die type ([para 0109]) different than the first die type ([para 0127]);
a first facilitator die (fig 2:30; [para 0120]) comprising a third die type ([para 0120]) different than the first die type ([para 0127]) and the second die type ([para 0109]);
;
forming at least one of a signal connection (fig 1,2:SA_GBL,LBL; [para 0084,0127]) and a power distribution line hierarchically between the bottom die (fig 2:50; [para 0134]), the plurality of upper dies, the first facilitator die (fig 2:30; [para 0120]), , wherein connections between the bottom die (fig 2:50; [para 0134]) and the first facilitator die (fig 2:30; [para 0120]) comprise a first hierarchical level (fig,1:SA_GBL; [para 0127]), , l.
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Okamoto does not teach a plurality of second facilitator die and a third hierarchical level.
Hollis teaches:
a first facilitator die (fig 4:420; [para 0035]) comprising a third die type different than the first die type (fig 4:410; [para 0035]) and the second die type (fig 4:440; [para 0035]);
and a plurality of second facilitator dies (fig 4:422,424; [para 0035]);
forming at least one of a signal connection (fig 4:450; [para 0035]) hierarchically between the bottom die (fig 4:420; [para 0035]), the plurality of upper dies (fig 4:422,424; [para 0035]), the first facilitator die (fig 4:420; [para 0035]), and the plurality of second facilitator dies (fig 4:422,424; [para 0035]), wherein connections (fig 4:450; [para 0035]) between the bottom die (fig 4:410; [para 0035]) and the first facilitator die (fig 4:420; [para 0035]) comprise a first hierarchical level, connections (fig 4:452a; [para 0035]) between the first facilitator die (fig 4:420; [para 0035]) and the plurality of second facilitator dies (fig 4:422; [para 0035]) comprise a second hierarchical level, and connections (fig 4:454b; [para 0035]) between the plurality of second facilitator dies (fig 4:422; [para 0035]) and one or more of the plurality of upper dies (fig 4:440; [para 0035]) comprise a third hierarchical level.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide additional facilitator die and hierarchical levels in order to enable greater scaling and upward stacking of die.
Regarding claim 6.
Okamoto in view of Hollis teaches the method of claim 1,
Okamoto teaches:
wherein the first hierarchical level and the second hierarchical level (fig 1,2)
Hollis teaches:
a two-level tree configuration (fig 4; [para 0036,0037]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide two level tree hierarchy because the additional levels of hierarchy enable lower capacitance at the lower levels of the hierarchy tree (paragraph 37).
Regarding claim 7.
Okamoto in view of Hollis teaches the method of claim 1,
Okamoto teaches:
wherein the first hierarchical level and the second hierarchical level (fig 1,2)
Okamoto does not teach a both end configuration.
Hollis teaches:
a both-end drive configuration (fig 3; [para 0031,0032]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the memory for both ends in order to increase throughput using bidirectional communication (paragraph 33).
Regarding claim 9.
Okamoto in view of Hollis teaches the method of claim 1, further comprising:
Okamoto teaches:
forming a local memory (fig 10:94; [para 0230]) on the first facilitator die (fig 10:30; [para 0233]),
the local memory (fig 10:94; [para 0230]) configured to receive request and data signals from the bottom die (fig 10:50; [para 0233]).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) in view of Hollis (US 2012/0051152) as applied to claim 1 and further in view of Kwon (US 2018/0226108).
Regarding claim 2
Okamoto in view of Hollis teaches the method of claim 1, above:
Okamoto teaches:
forming a global power line (fig 2:SA_GBL; [para 0084,0142]) , the global power line (fig 2:SA_GBL; [para 0084,0142])coupled to the bottom die (fig 2:50; [para 0107]) and the first facilitator die (fig 2:30; [para 0120]) in the first hierarchical level;
forming a local power line (fig 2:LBL; [para 0084,0109]) , the local power line (fig 2:LBL; [para 0084,0109]) coupled and one or more of the plurality of upper dies (fig 2:40; [para 00109]) in the third hierarchical level;
Hollis teaches:
the bottom die (fig 4:420; [para 0035]) and the first facilitator die (fig 4:420; [para 0035]) in the first hierarchical level; the second facilitator dies (fig 4:422,424; [para 0035]) and one or more of the plurality of upper dies (fig 4:440; [para 0035]) in the third hierarchical level;
and the first facilitator die (fig 4:420; [para 0035]).
Okamoto in view of Hollis does not teach a voltage converter
Kwon teaches:
a global power line comprising a first voltage (fig 14:1.8V; [para 0149]),
the global power line coupled to the bottom die (fig 14:120; [para 0149]) and the facilitator die (fig 14:113c; [para 0148]) in the first hierarchical level;
forming a local power line comprising a second voltage (fig 14:1.2V; [para 0150]) less than the first voltage (fig 14:1.8V; [para 0149]),
the local power line coupled to the facilitator die (fig 14:113c; [para 0148]) and one or more of the plurality of upper dies (fig 14:DIE1-8; [para 0148]) in the second hierarchical level;
and forming a voltage converter (fig 14:160; [para 0153]) on the facilitator die (fig 14:113c; [para 0148]),
the voltage converter (fig 14:160; [para 0153]) coupled to the global power line and the local power line (fig 14).
It would have been obvious to one of ordinary skill in the art to provide a voltage converter in order to provide the driving voltage required by the memory unit (paragraph 153).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) in view of Hollis (US 2012/0051152) as applied to claim 1 and further in view of Kwon (US 2018/0226108).
Regarding claim 3
Okamoto in view of Hollis teaches the method of claim 1, above:
Okamoto teaches:
forming a global signal line (fig 2:SA_GBL; [para 0084,0142]) coupled to the bottom die (fig 2:50; [para 0134]) and the first facilitator die (fig 2:30; [para 0120]) in the first hierarchical level;
forming a local signal bus (fig 2:LBL; [para 0109]) coupled to (fig 2:40; [para 0109]) ;
Hollis teaches:
the bottom die (fig 4:420; [para 0035]) and the first facilitator die (fig 4:420; [para 0035]) in the first hierarchical level;
the second facilitator dies (fig 4:422,424; [para 0035]) and one or more of the plurality of upper dies (fig 4:440; [para 0035]) in the third hierarchical level;
Okamoto in view of Hollis does not teach a serializer
Kwon teaches:
forming a serializer (fig 7:117; [para 0109]) on the first facilitator die (fig 7:113a; [para 0109]),
the serializer (fig 7:117; [para 0109]) coupled to the global signal line (fig 7:DATA; [para 0108]) and the local signal bus (fig 7:DQS; [para 0112]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a seiralizer so that the data realignment circuit may interface communications between the controller operating at high frequency and the memory chips at low frequency (paragraph 90).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) in view of Hollis (US 2012/0051152) as applied to claim 1 and further and further in view of Seok (US 2015/0373848) in view of Kwon (US 2018/0226108).
Regarding claim 4
Okamoto in view of Hollis teaches the method of claim 1, above:
Okamoto teaches:
the bottom die (fig 2,50; [para 0134]) and the first facilitator die (fig 2:30; [para 0120]) in the first hierarchical level;
.
Okamoto in view of Hollis does not teach a common signal line.
Seok teaches:
a common signal line (fig 6: [para 0064]) comprising a fly-by-signal (address, control, and clock signals are combined; [para 0064]),
the common signal line coupled to the first facilitator die (fig 6:630; [para 0064]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a common signal line in order that the command, the address, the control signal, and the clock signal, output can be combined into one line thereby reducing the number of lines to be formed (paragraph 64).
Okamoto in view of Hollis does not teach ESD protection.
Kwon teaches:
forming an electrostatic discharge (ESD) protection circuit (fig 16:174; [para 0168]) on the first facilitator die (fig 16:170; [para 0168]),
the ESD protection circuit (fig 16:174; [para 0168]) coupled to the signal line (fig 16:CH_1; [para 0166]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide ESD protection in order to prevent damage from static discharges.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) in view of Hollis (US 2012/0051152) as applied to claim 1 and further in view of Pawlowski (US 2021/0200632)
Regarding claim 5.
Okamoto in view of Hollis teaches the method of claim 1, above
Okamoto teaches:
wherein the first hierarchical level and the second hierarchical level (fig 1,2)
Okamoto in view of Hollis does not teach a redrive configuration.
Pawlowski teaches:
a stacked semiconductor die method (fig 1; [para 0015]) comprise a redrive configuration (fig 2; [para 0021].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a redrive configuration in order to drive signals to and from the memory dies (paragraph 21)
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) in view of Hollis (US 2012/0051152) as applied to claim 1 and further in view of Jayasena (US 2022/0413849)
Regarding claim 8.
Okamoto in view of Hollis teaches the method of claim 1, above:
Okamoto teaches
forming a near memory processor on the first facilitator die (fig 2:30; [para 0120]),
the near memory processor configured to receive an execution code from the bottom die (fig 2,50; [para 0134]), process the execution code,
and transmit memory data to an upper die (fig 2:41[m]; [para 109]) of the plurality of upper dies (fig 2:40; [para 0109]).
Okamoto in view of Hollis does not teach near memory computing.
Jayasena teaches:
forming a near memory processor (fig 2:142; [para 0033]),
the near memory processor (fig 2:142; [para 0033]) configured to receive an execution code (fig 2:232; [para 0036]),
process the execution code, and transmit memory data to memory (fig 2:128; [para 0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that near memory processing can save time by reducing external communications (i.e., host to memory device communications) and can also conserve power (paragraph 1).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto (US 2025/0329352, JP 2022-151378) in view of Hollis (US 2012/0051152) as applied to claim 1 and further in view of Vergis (US 2018/0061478)
Regarding claim 10.
Okamoto in view of Hollis teaches the method of claim 1, above
Okamoto teaches:
forming the first facilitator die (fig 2:30; [para 0120]),
configured to receive data from the bottom die (fig 2,50; [para 0134]), process the data, and transmit memory data to an upper die (fig 2:41[m]; [para 109]) of the plurality of upper dies (fig 2:40; [para 00109]).
Okamoto in view of Hollis does not teach the facilitator die comprises a controller.
Vergis teaches:
forming a memory controller (fig 1:150; [para 0038])on the first facilitator die (fig 1:140; [para 0038]),
the memory controller (fig 1:150; [para 0038]) configured to receive data, process the data, and transmit memory data ([para 0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a memory controller in the memory device in order to configure the internal execution of commands for the connected memory die.
Response to Arguments
Applicant's arguments filed 6/10/2026have been fully considered but they are not persuasive.
The applicant argues that the prior art does not teach a plurality of second facilitator die and three hierarchical levels.
However, Hollis (US 2012/0051152) figure 4 teaches this element, see the combination above.
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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