Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ryoichi et al., JP 2021-141222A.
Ryoichi et al. shows the invention as claimed including a semiconductor device comprising:
A semiconductor chip (for example, 1) that has a first main electrode on a rear surface thereof and a second main electrode on a front surface thereof (see upper and lower surface electrodes in abstract on first semiconductor element 3a, for example); and
A wiring layer (for example, 4a-4d) electrically connected to at least one of the first main electrode or the second main electrode, the wiring layer including a conductive member disposed on a front surface thereof, wherein the wiring layer includes a first portion that has, on a front surface thereof, a chip area to which the rear surface of the semiconductor chip is bonded, a second portion that has, on a front surface thereof, a terminal area to which an external connection terminal is bonded, and a wiring portion that connects the first portion and the second portion, the wiring portion including the conductive member on a front surface thereof (see figs. and abstract).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryoichi et al., JP 2021-141222A.
Ryochi et al. is applied as above and additionally comprises wherein the conductive member has a flat plate portion that has a flat plate shape extending along the wiring portion. However, Ryochi et al. does not expressly disclose that the conductive member has a width equal to or less than a width of the wiring portion in a direction perpendicular to a direction in which a current in the wiring layer flows in a plan view of the semiconductor device. However, a prima facie case of obviousness exists because where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
With respect to dependent claim 4, note that Ryochi discloses wherein the flat plate portion of the conductive member is directly disposed on the front surface of the wiring portion.
Response to Arguments
Applicant’s arguments with respect to claim(s) 2-4 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
April 23, 2026
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