DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Species I directed to Figs. 1-7 (Claims 1-10) in the reply filed on January 20th, 2026 is acknowledged.
Claim Objections
Claims 4 and 9-10 are objected to because of the following informalities:
Claim 4 recites “a length in the first direction of the first portion” and “a length in the first direction of the second portion” which sounds confusing and should be amended to “a length of the first portion in the first direction” and “a length of the second portion in the first direction”. Appropriate correction is required.
Claim 9 recites limitation “the fourth semiconductor layers” in line 2 which refers back to “a plurality of the fourth semiconductor layers” in line 4 of claim 8 and should be amended to “the plurality of the fourth semiconductor layers” for avoiding confusion. Appropriate correction is required.
Claim 10 recites limitation “the fourth semiconductor layers” in lines 3 and 5 which refers back to “a plurality of the fourth semiconductor layers” in line 4 of claim 8 and should be amended to “the plurality of the fourth semiconductor layers” for avoiding confusion. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2 recites the limitation “the second electrode side” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al. (Pub. No.: US 2019/0140094 A1), hereinafter as Kurokawa and in view of SUZUKI et al. (Pub. No.: US 2011/0291110 A1), hereinafter as Suzuki.
PNG
media_image1.png
600
688
media_image1.png
Greyscale
Regarding claim 1, Kurokawa discloses a semiconductor device in Figs. 1-5, comprising: a first electrode (electrode 72) (see Fig. 1 and [0027]); a second electrode (electrode 70) (see Fig. 1 and [0027]); a third electrode (a gate electrode 26) located
between the first electrode and the second electrode, the third electrode extending in a first direction (y-direction) and including a first portion (a portion of gate electrode 26 not overlapping with p-type region 36 in z-direction in Fig. 3) and a second portion (a portion of gate electrode 26 directly above and overlapping with p-type region 36 in Fig. 2) (see Figs. 1-3, annotated Fig. 4 above and [0034]); a first semiconductor layer (combination of drain region 35 and drift region 34) connected to the first electrode, the first semiconductor layer facing the first portion via an insulating layer (gate insulating layer 24), the first semiconductor layer being of a first conductivity type (n-type) and including silicon and carbon (see Figs. 1, annotated Fig. 4 above and [0024], [0024]); a second semiconductor layer (source region 30) connected to the second electrode, the second semiconductor layer being of the first conductivity type (n-type) and including silicon and carbon (see Fig. 1 and [0029], [0024]); a third semiconductor layer of a second conductivity type (low-density body region 32b of p-type), at least a portion of the third semiconductor layer being located between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer contacting the first and second semiconductor layers (contacting drift region 34 and source region 30), facing the third electrode via the insulating layer (gate insulating layer 24), and including silicon and carbon (see Fig. 1 and [0030]); and a fourth semiconductor layer of the second conductivity type (combination of p-type regions 38 and 36), at least a portion of the fourth semiconductor layer (p-type region 36) being located between the first semiconductor layer and the second portion (see Fig. 2 and annotated Fig. 4 above), the fourth semiconductor layer facing the second portion via the insulating layer (see annotated Fig. 4 above), the fourth semiconductor layer contacting the third semiconductor layer (p-type region 38 contacts the low-density body region 32b) and including silicon and carbon (see Fig. 2, annotated Fig. 4 and [0034-0036]).
Kurokawa fails to discloses the semiconductor device comprising a carrier concentration of the fourth semiconductor layer being greater than a carrier concentration of the third semiconductor layer.
Suzuki discloses a semiconductor device in Figs. 2A-2D comprising a carrier concentration of a fourth semiconductor layer (carrier concentration of p-type deep layer 10) being greater than a carrier concentration of a third semiconductor layer (carrier concentration of p-type base region 3) (see [0039-0040], [0044] and [0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Kurokawa having the carrier concentration of the fourth semiconductor layer (combination of p-type regions 38 and 36) to be greater than the carrier concentration of the third semiconductor layer (low-density body region 32b) as same as the semiconductor device of Suzuki because the modified structure would improve the functionality of the semiconductor device by reducing the electric field concentration in the gate oxide layer at the bottom of the trench and reduce damages of the gate oxide layer at high voltage (see Suzuki and [0051-0052]).
Regarding claim 2, the combination of Kurokawa and Suzuki discloses the device according to claim 1, wherein a surface of the fourth semiconductor layer at the second electrode side contacts the third semiconductor layer and the insulating layer (top surface of p-type region 38 contacts low-density body region 32b and gate insulating layer 24) (see Fig. 1 of Kurokawa).
Regarding claim 3, the combination of Kurokawa and Suzuki discloses the device according to claim 1, wherein a surface of the first semiconductor layer (a top surface of drift region 34 between p-type regions 36) faces the first portion contacts the insulating layer (see Fig. 1 of Kurokawa).
Regarding claim 4, the combination of Kurokawa and Suzuki discloses the device according to claim 1, wherein a length in the first direction of the first portion is not more than a length in the first direction of the second portion (claim fails to define how the length being measured from one end to another end of the first and second portions) (a dimension of length on the first portion of gate electrode 26 can be selected to be equal to a dimension of length on the second portion of gate electrode 26) (see annotated Fig. 4 of Kurokawa above).
Regarding claim 5, the combination of Kurokawa and Suzuki discloses the device according to claim 1, wherein the first portion and the second portion of the third electrode are alternately arranged along the first direction (see annotated Fig. 4 of Kurokawa above).
Regarding claim 6, the combination of Kurokawa and Suzuki discloses the device according to claim 5, wherein the first portion and the second portion are periodically arranged (see annotated Fig. 4 of Kurokawa above).
Regarding claim 7, the combination of Kurokawa and Suzuki discloses the device according to claim 1, wherein the second semiconductor layer extends in the first direction (y-direction) and faces the third electrode via the insulating layer (see Fig. 4 of Kurokawa).
Regarding claim 8, the combination of Kurokawa and Suzuki discloses the device according to claim 1, wherein a plurality of the third electrodes (plurality of gate electrodes 26) is arranged along a second direction (x-direction) crossing the first direction (see Figs. 1 and 5 of Kurokawa), and a plurality of the fourth semiconductor layers (plurality of combination of p-types 38 and 36) is arranged along the first direction (see Figs. 1 and 4 of Kurokawa).
Regarding claim 9, the combination of Kurokawa and Suzuki discloses the device according to claim 8, wherein the fourth semiconductor layers are arranged in a matrix configuration along the first and second directions (see Fig. 5 of Kurokawa).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if amended to overcome the objection under formalities and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having: wherein a carrier concentration of a portion of the first semiconductor layer located between the fourth semiconductor layers next to each other in the second direction is greater than a carrier concentration of a portion of the first semiconductor layer located between the fourth semiconductor layers next to each other in the first direction as recited in claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CUONG B NGUYEN/Primary Examiner, Art Unit 2818