DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 31, 2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s Admitted Prior Art (hereinafter “AAPA” – previously cited reference) in view of US 2019/0140091 A1 to Kinoshita et al. (hereinafter “Kinoshita” – previously cited reference).
Regarding claim 1, AAPA discloses a silicon carbide semiconductor device, comprising:
a silicon carbide semiconductor substrate of a first conductivity type, the silicon carbide semiconductor substrate having a first main surface and a second main surface that are opposite to each other (SiC device 150 having n+ SiC substrate 101 with first and second surfaces; Fig. 9; paragraphs [0006]-[0007]);
a first semiconductor layer of the first conductivity type, provided on the first main surface of the silicon carbide semiconductor substrate, the first semiconductor layer having an impurity concentration that is lower than an impurity concentration of the silicon carbide semiconductor substrate, the first semiconductor layer having a first surface and a second surface that are opposite to each other, the second surface of the first semiconductor layer facing the silicon carbide semiconductor substrate (n- SiC epitaxial layer 102 and n-type region 105 collectively form layer and have lower impurity concentration than n+ substrate 101 and are disposed adjacent thereto as shown in Fig. 9; paragraphs [0006]-[0007]);
a second semiconductor layer of a second conductivity type, provided on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface that are opposite to each other, the second surface of the second semiconductor layer facing the silicon carbide semiconductor substrate (p-type base layer 106, p+ contact region 108, and channel layer 114 collectively form layer disposed upon region 105 as shown in Fig. 9; paragraphs [0006]-[0008]);
a plurality of first semiconductor regions of the first conductivity type, selectively provided on the first surface of the second semiconductor layer (n-type source regions 107 disposed upon layer 114 as shown in Fig. 9; paragraphs [0006]-[0008]);
a plurality of trenches, penetrating respectively through the first semiconductor regions and through the second semiconductor layer and reaching the first semiconductor layer (trenches 116 disposed through regions 107 and layers 106, 114 to reach region 105 as shown in Fig. 9; paragraphs [0006]-[0008]);
a plurality of gate insulating films provided respectively in the trenches (each trench 116 has gate insulating film 109; Fig. 9; paragraphs [0006]-[0008]);
a plurality of gate electrodes, provided respectively in the trenches, via the plurality of gate insulating films (each trench 116 has gate electrode 110; Fig. 9; paragraphs [0006]-[0008]);
a plurality of second semiconductor regions of the second conductivity type, selectively provided in the first semiconductor layer, each of the second semiconductor regions underlying a bottom of one of the trenches (each trench 116 has p+ base region 103 disposed thereunder and within n-type layer having layer 102 and region 105 as shown in Fig. 9; paragraphs [0006]-[0008]);
a plurality of third semiconductor regions of the second conductivity type, selectively provided in the first semiconductor layer and the second semiconductor layer, each between adjacent two of the trenches, the third semiconductor regions being in contact with the second semiconductor layer (p+ base regions 104 disposed between trenches 116, within layer having layer 102 and region 105, and within layer having layers 106, 114 as shown in Fig. 9; paragraphs [0006]-[0007]);
a first electrode that is in contact with the second semiconductor layer and the first semiconductor regions (source electrode 112 in contact with n+ source region 107 and p+ contact region 108 as shown in Fig. 9; paragraphs [0006]-[0008]); and
a second electrode provided on the second main surface of the silicon carbide semiconductor substrate (back electrode 113 on surface of SiC substrate 101 as shown in Fig. 9; paragraphs [0006]-[0008]), wherein the silicon carbide semiconductor device has an active region end portion that is free of the first semiconductor regions (active region end portion 141 free of region 107; Fig. 10; paragraph [0010]), and in the active region end portion, each of the third semiconductor regions is, in a direction diagonal to the first main surface of the silicon carbide semiconductor substrate, separated from each of the two trenches between which said each third semiconductor region is located by a portion of the second semiconductor layer, and is connected to at least one of the second semiconductor regions (base regions 104 separated from sidewall of each trench 116 by base layer 106 in a diagonal direction and connected to at least one base region 103 as shown in Figs. 9-10 and 13).
AAPA fails to disclose each of the third semiconductor regions is, in a direction parallel to the first main surface of the silicon carbide semiconductor substrate, separated from each of the two trenches between which said each third semiconductor region is located by a portion of the second semiconductor layer.
However, Kinoshita discloses each of the third semiconductor regions is, in a direction parallel to the first main surface of the silicon carbide semiconductor substrate, separated from each of the two trenches between which said each third semiconductor region is located by a portion of the second semiconductor layer (base contact region 7b disposed between and spaced apart from all sidewalls of trenches 21a, 21b by portion of p-type base region 6b in a horizontal direction; see annotated Fig. 1 below; paragraphs [0037]-[0038]).
AAPA and Kinoshita are both considered to be analogous to the claimed invention because they are in the same field of insulated-gate semiconductor devices with trenches. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified AAPA to incorporate the teaching of Kinoshita in order to potentially at least provide a reduction in peak electric fields at the trench sidewall thereby mitigating the risk of dielectric breakdown in the gate oxide which improves device reliability.
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Regarding claim 2, AAPA in view of Kinoshita discloses the silicon carbide semiconductor device according to claim 1. AAPA further discloses wherein in the active region end portion, each of the second semiconductor regions is adjacent the bottom of the trench that said each second semiconductor region underlies (each trench 116 has p+ base region 103 disposed thereunder as shown in Fig. 9; paragraphs [0006]-[0008]).
AAPA fails to disclose each of the second semiconductor regions is apart from the bottom of the trench.
However, Kinoshita discloses each of the second semiconductor regions is apart from the bottom of the trench (p+ base regions 5a, 5b, 5c spaced apart from bottom of trenches 10a, 10b by portions of n-type current spreading layer 3; Fig. 1; paragraph [0046]).
AAPA and Kinoshita are both considered to be analogous to the claimed invention because they are in the same field of insulated-gate semiconductor devices with trenches. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified AAPA to incorporate the teaching of Kinoshita in order to potentially at least provide a reduction in peak electric fields at the trench bottom thereby mitigating the risk of dielectric breakdown in the gate oxide which improves device reliability.
Regarding claim 3, AAPA in view of Kinoshita discloses the silicon carbide semiconductor device according to claim 1. AAPA further discloses wherein in the active region end portion, said each third semiconductor region and said sidewall of each of the two trenches are separated from each other by the first semiconductor layer and the second semiconductor layer (base region 104 separated from at least one side of each trench 116 by n-type region 105 and p-type layer 106 as shown in Fig. 9).
Regarding claim 4, AAPA in view of Kinoshita discloses the silicon carbide semiconductor device according to claim 1. AAPA further discloses wherein the trenches are disposed in a striped pattern in a top view of the silicon carbide semiconductor device, and the active region end portion is an end portion of the silicon carbide semiconductor device in a longitudinal direction of the trenches (trenches 116 disposed in striped pattern from top view and active region end portion 141 is disposed at end portion of device 150 in longitudinal direction of trenches 116; Fig. 11).
Regarding claim 5, AAPA in view of Kinoshita discloses the silicon carbide semiconductor device according to claim 1. AAPA further discloses a third semiconductor layer that is of the first conductivity type, and has an impurity concentration higher than that of the first semiconductor layer and lower than that of the silicon carbide semiconductor substrate (n-type region 105 as a part of first semiconductor layer may form a third semiconductor layer by itself which has an impurity concentration higher than the average impurity concentration of first semiconductor layer and lower than that of n+ SiC substrate 101; Fig. 9).
AAPA fails to disclose wherein in the direction parallel to the first main surface of the silicon carbide semiconductor substrate, said each third semiconductor region is separated from said each trench by both the portion of the second semiconductor layer and a portion of the third semiconductor layer.
However, Kinoshita discloses wherein in the direction parallel to the first main surface of the silicon carbide semiconductor substrate, said each third semiconductor region is separated from said each trench by both the portion of the second semiconductor layer and a portion of the third semiconductor layer (base contact region 7b spaced apart from trenches 21a, 21b by portion of p-type base region 6b and n+ source regions 8b, 8c in a horizontal direction; Fig. 1; paragraphs [0037]-[0038]).
AAPA and Kinoshita are both considered to be analogous to the claimed invention because they are in the same field of insulated-gate semiconductor devices with trenches. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified AAPA to incorporate the teaching of Kinoshita in order to potentially at least provide a reduction in peak electric fields at the trench sidewall thereby mitigating the risk of dielectric breakdown in the gate oxide which improves device reliability.
Response to Arguments
Applicant's arguments filed January 22, 2026 have been fully considered. Applicant amended claim 1 and added new claim 5 and provided associated arguments. Specifically, Applicant asserts that Kinoshita cannot be combined with AAPA to disclose amended claim 1 because a skilled artisan would have looked to Kinoshita for the deficiencies in AAPA given that Kinoshita (while reading on the limitation not disclosed by AAPA) does not disclose other limitations that are already disclosed by AAPA (e.g. allegations that the base contact region 7b is not in contact with a second semiconductor layer). However, a skilled artisan would not be looking in the prior art for features already disclosed, but only for features that are not disclosed. Both AAPA and Kinoshita have common ownership (Fuji Electric Co Ltd) and are in the same field of insulated-gate semiconductor devices with trenches having specific n- and p-type doped regions oriented therebetween and so a skilled artisan would naturally look to Kinoshita to disclose deficiencies in AAPA. Further, while Applicant compares Fig. 9 of AAPA to Fig. 2A of Applicant’s invention, Fig. 10 of AAPA is exactly the same as Fig. 2A (which illustrates support for the amended limitations of claim 1) of Applicant’s invention except for a thin strip of semiconductor material between the trench sidewalls and the third semiconductor regions, which by itself renders the amended limitation and new claim 5 obvious and Kinoshita merely provides one example of such structural arrangements in the prior art.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818