DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the objection to the drawings, Applicant’s arguments and/or amendments have resolved the prior issues of claimed subject matter not being shown in the drawing. Accordingly, the objection to the drawings is withdrawn.
RE: the objection to claim(s) 13, Applicant’s arguments and/or amendments have resolved the typographical issues in these claims. Accordingly, the objection to claim(s) 13 is withdrawn.
RE: the rejection of claim(s) 1-14 under 35 USC 112(b), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of indefiniteness. Accordingly, the rejection of claim(s) 1-14 has been withdrawn.
RE: the rejection of claim(s) 1-14 and 20 under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot in view of the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 7, 9-10, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20230288453A1 (“Ziglioli”) in view of US5086018A (“Conru”).
RE: Claim 1, Ziglioli discloses An apparatus (apparatus in FIG. 2), comprising:
a metal leadframe (lead frame 3 formed from conductive metal, [0033]) comprising:
first leads (leads of 4 including combination of portion of 4 covered by 7 in FIG. 2, connection terminals 13, and extensions 23, [0037], [0047]) in a first portion (primary conductor 4, [0033]; primary conductor 4 includes connection terminals 13 and extensions 23, [0047]);
second leads (leads of 5 including portion of 5 covered by 7 in FIG. 2, and secondary conductors 5, each including an IC connection portion 15 and surface mount connection terminal 16, [0040]; conductors 15, 16 of 5 are shown in FIGs. 3a-3c) in a second portion (secondary conductors 5) spaced from the first leads by an opening (FIG. 2 shows an opening separating 4 and 5),
the second leads isolated from the first leads (insulating sheet 8 provides insulation between the primary conductor 4 and the chip 2, [0038],[0039]; overmold housing 7 is insulating, [0030]; accordingly, leads in 5 are insulated from the leads in 4, no current flows from the leads of 4 to leads 5 or vice versa, and leads in 5 are isolated from the leads in 4);
an isolation barrier (8 is insulating, [0039]) mounted to a board side surface (bottom surface of 4 in FIG. 2) of the first portion of the metal leadframe (The insulating layer 8 may be attached to the lead frame with a glue layer, [0031]);
a semiconductor die (IC chip 2 is a semiconductor chip, [0032], [0038]) having a device side surface (upper surface of 2 in FIG. 2) mounted using die attach material (glue layer, [0031]; The chip is attached to the lead frame with a glue layer between the face 9 a and the insulating layer 8, [0031]) to the isolation barrier,
the semiconductor die having a sensor (sensor portion 10, [0031]) on the device side surface facing the first portion of the metal leadframe (The IC chip is oriented such that the active sensing portions faces the primary conductor to be as close as possible to the primary conductor for maximizing the signal measurement, [0039]),
the semiconductor die cantilevered and having bond pads (11, [0031]) on the device side surface aligned with the opening in the metal leadframe (FIG. 2 shows 2 is cantilevered from conductor 4; FIG. 2 shows 11 is aligned with the opening separating 4 and 5);
electrical connections (6, [0041]) coupling the bond pads and second leads in the second portion of the metal leadframe; and
mold compound (7, [0030]) covering the semiconductor die, the electrical connections, the isolation barrier and portions of the first leads and the second leads, the mold compound forming a package body (FIG. 2 shows 7 covering 2, 6, 8, and portions of leads of 4, 5; 7 forms a package body in FIG. 2).
Ziglioli does not explicitly disclose:
the isolation barrier is mounted to the board side surface of the first portion of the metal leadframe via a die attach film, a side surface of the die attach film and a side surface of the isolation barrier being coplanar.
However, Ziglioli discloses The insulating layer 8 may be attached to the lead frame with a glue layer, [0031].
In the same field of endeavor, Conru discloses in FIG. 3:
an isolation barrier (left insulating layer 11, Col. 3, lines 34-35) mounted to a board side surface of a first portion of a metal leadframe (left board side surface of portion of 14) via a die attach film (left adhesive coating 11a, Col. 3, lines 15-30), a side surface of the die attach film and a side surface of the isolation barrier being coplanar (FIG. 3 shows left side surface of left 11a and left side surface of left 11 are coplanar; FIG. 3 also shows right side surface of left 11a and right side surface of 11 are coplanar).
Conru further discloses The layer 11 has adhesive coatings 11a and 11b, which are applied as thin films to the major surfaces of layer 11 and are used to help secure the layer 11 to the lead frame 10 and the chip 12, Col. 3, lines 15-20.
Conru further shows in FIG. 3 the adhesive coating11a is applied to the top surface of the insulating layer 11, and is positioned between the insulating layer 11 and a portion of the leadframe 14.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the glue layer mounting the insulating layer 8 to the lead frame to be an adhesive coating with left and right side surfaces coplanar with respective side surfaces of the insulating layer 8 and positioned between the portion 4 of the leadframe and the insulating layer 8 as taught by Conru in order to help secure the insulating layer 8 to the conductor 4.
RE: Claim 2, the combination of Ziglioli, Conru discloses The apparatus of claim 1, wherein the first portion of the metal leadframe further comprises a conductor (12 in FIG. 3c of Ziglioli,) that is serially coupled between one of the first leads and another one of the first leads (In Ziglioli FIG. 3c shows 12 is serially coupled between one of the leads 13 and another one of the leads 13), and the sensor on the device side surface of the semiconductor die is aligned to the conductor (In Ziglioli, magnetic field sensing portion 10 of the IC chip is positioned preferably in an overlapping relationship with the sensing portion 12 of the primary conductor, [0038]; accordingly, 10 is aligned with 12).
RE: Claim 3, the combination of Ziglioli, Conru discloses The apparatus of claim 2, wherein the sensor is a Hall-effect current sensor, a position sensor, an inductor, a plate of a capacitor, a transducer, or a coil (Ziglioli discloses magnetic field sensing portion 10 is a Hall effect sensor, [0032];10 is positioned overlapping and very close to sensing portion 12 of the primary conductor 4, [0038]; 12 has a reduced conductive cross-sectional area in order to concentrate for the current to be measured (the primary current) and increase the intensity of the magnetic field around the sensing portion 12, [0037]; further, 10 is part of the active layer of chip 2, [0031] and Ziglioli teaches an integrated circuit (IC) chip having an active sensing layer thereon detecting the magnetic field induced by a current, [0002]; accordingly, 10 detects the magnetic field induced by current in the primary conductor 4 and is therefore considered a current sensor).
RE: Claim 4, the combination of Ziglioli, Conru discloses The apparatus of claim 2, wherein the sensor is a Hall-effect current sensor (Ziglioli discloses magnetic field sensing portion 10 is a Hall effect sensor, [0032];10 is positioned overlapping and very close to sensing portion 12 of the primary conductor 4, [0038]; 12 has a reduced conductive cross-sectional area in order to concentrate for the current to be measured (the primary current) and increase the intensity of the magnetic field around the sensing portion 12, [0037]; further, 10 is part of the active layer of chip 2, [0031] and Ziglioli teaches an integrated circuit (IC) chip having an active sensing layer thereon detecting the magnetic field induced by a current, [0002]; accordingly, 10 detects the magnetic field induced by current in the primary conductor 4 and is therefore considered a current sensor).
RE: Claim 7, the combination of Ziglioli, Conru discloses The apparatus of claim 1, wherein the first leads and the second leads extend from the package body and are shaped to form terminals configured for surface mounting to a system board (In FIG. 2 of Ziglioli, 13, 16 extend from 7; 13 are configured for surface mount connection to conductive traces on an external circuit board, [0037]; 16 are arranged in a row presenting contact pads intended for surface mount solder or welding connection, as per se known in the art, to circuit traces of an external circuit board, [0040]).
RE: Claim 9, the combination of Ziglioli, Conru discloses The apparatus of claim 1, wherein the second leads have a first width, and the first leads have a second width that is greater than the first width (In Ziglioli, FIGs. 3a, 3b show 13, 23 have a width greater than width of 15, 16).
RE: Claim 10, the combination of Ziglioli, Conru discloses The apparatus of claim 9, wherein the first leads have the second width that is at least twice the first width (In Ziglioli, FIGs. 3a, 3b show each 13, 23 has a width that is at least twice the width of an individual 15, 16).
RE: Claim 20, Ziglioli discloses A current sensor device (apparatus in FIG. 2), comprising:
a metal leadframe (lead frame 3 formed from conductive metal, [0033]) comprising:
first leads (leads of 4 including combination of portion of 4 covered by 7 in FIG. 2, connection terminals 13, and extensions 23, [0037], [0047]) in a first portion (primary conductor 4, [0033]; primary conductor 4 includes connection terminals 13 and extensions 23, [0047]);
second leads (leads of 5 including portion of 5 covered by 7 in FIG. 2, and secondary conductors 5, each including an IC connection portion 15 and surface mount connection terminal 16, [0040]; conductors 15, 16 of 5 are shown in FIGs. 3a-3c) in a second portion (secondary conductors 5) spaced from the first leads by an opening (FIG. 2 shows an opening separating 4 and 5),
the second leads isolated from the first leads (insulating sheet 8 provides insulation between the primary conductor 4 and the chip 2, [0038],[0039]; overmold housing 7 is insulating, [0030]; accordingly, leads in 5 are insulated from the leads in 4, no current flows from the leads of 4 to leads 5 or vice versa, and leads in 5 are isolated from the leads in 4);
an isolation barrier (8 is insulating, [0039]) mounted to a board side surface (bottom surface of 4 in FIG. 2) of the first portion of the metal leadframe, the isolation barrier cantilevered from the first portion of the metal leadframe (FIG. 2 shows 8 cantilevered from 4);
a semiconductor die (IC chip 2 is a semiconductor chip, [0032], [0038]) having a device side surface (upper surface of 2 in FIG. 2) mounted to the isolation barrier,
the semiconductor die having a Hall-effect device (sensor portion 10, [0031]) configured as a current sensor on the device side surface facing and aligned to the first portion of the leadframe (magnetic field sensing portion 10 is a Hall effect sensor, [0032];10 is positioned overlapping and very close to sensing portion 12 of the primary conductor 4, [0038]; 12 has a reduced conductive cross-sectional area in order to concentrate for the current to be measured (the primary current) and increase the intensity of the magnetic field around the sensing portion 12, [0037]; further, 10 is part of the active layer of chip 2, [0031] and Ziglioli teaches an integrated circuit (IC) chip having an active sensing layer thereon detecting the magnetic field induced by a current, [0002]; accordingly, 10 detects the magnetic field induced by current in the primary conductor 4 and is therefore considered a current sensor; magnetic field sensing portion 10 of the IC chip is positioned preferably in an overlapping relationship with the sensing portion 12 of the primary conductor, [0038]; accordingly, 10 is aligned with 12 which is part of the primary conductor 4, [0033], [0037]),
the semiconductor die cantilevered and having bond pads (11, [0031]) on the device side surface (FIG. 2 shows 2 is cantilevered from conductor 4);
wire bond connections (6, [0041]) coupling the bond pads and second leads in the second portion of the metal leadframe, the wire bond connections extending through the opening in the metal leadframe (FIG. 2 shows 6 extending through the opening in 3 which separates 4 and 5); and
mold compound (7, [0030]) covering the semiconductor die, the electrical connections, the isolation barrier and portions of the first leads and portions of the second leads, the mold compound forming a semiconductor device package (FIG. 2 shows 7 covering 2, 6, 8, and portions of leads of 4, 5; 7 forms a package in FIG. 2).
Ziglioli does not explicitly disclose:
the bond pads on the device side surface are positioned in the opening in the leadframe;
the isolation barrier is mounted to the board side surface of the first portion of the metal leadframe via a die attach film, the die attach film is cantilevered from the first portion of the metal leadframe, a side edge of the isolation barrier and a side edge of the die attach film being coplanar.
However, Ziglioli discloses The insulating layer 8 may be attached to the lead frame with a glue layer, [0031].
In the same field of endeavor, Conru discloses in FIG. 3:
bond pads (5) on the device side surface positioned in the opening in the leadframe (bond pads 5 are in opening of leadframe defined by left lead frame portion 14 and right lead frame portion 14, with left 14 and right 14 extending outward from 17 and downward);
an isolation barrier (left insulating layer 11, Col. 3, lines 34-35) is mounted to the board side surface of the first portion of the metal leadframe (left board side surface of portion of 14) via a die attach film (left adhesive coating 11a, Col. 3, lines 15-30), the die attach film cantilevered from the first portion of the metal leadframe (FIG. 3 shows right end of 11a extends beyond the end of the left 14; Accordingly, the right end of 11a is cantilevered from the left 14), a side edge of the isolation barrier and a side edge of the die attach film being coplanar (FIG. 3 shows left side edge of left 11a and left side edge of left 11 are coplanar; FIG. 3 also shows right side edge of left 11a and right side edge of left 11 are coplanar).
Conru further discloses The layer 11 has adhesive coatings 11a and 11b, which are applied as thin films to the major surfaces of layer 11 and are used to help secure the layer 11 to the lead frame 10 and the chip 12, Col. 3, lines 15-20.
Conru further shows in FIG. 3 the adhesive coating11a is applied to the top surface of the insulating layer 11, and is positioned between the insulating layer 11 and a portion of the leadframe 14.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the lead frame portions 4 and 5 to extend outward and downward, and to modify the glue layer mounting the insulating layer 8 to the lead frame to be an adhesive coating with left and right side edges coplanar with respective side edges of the insulating layer 8 and positioned between the portion 4 of the leadframe and the insulating layer 8 as taught by Conru in order to make the lead frame portions 4, 5, more electrically accessible and to help secure the insulating layer 8 to the conductor 4. As a result, the insulating layer 8 with the adhesive coating applied to its top surface would be cantilevered from the first portion 4 of the metal leadframe.
Claim 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ziglioli in view of Conru as applied to claim 4 above, and further in view of US20050224248A1 (“Gagnon”).
RE: Claim 5, the combination of Ziglioli and Conru does not explicitly disclose The apparatus of claim 4, wherein the sensor is configured to output a signal indicating the strength of a magnetic field corresponding to a current flowing between the one of the first leads and the another one of the first leads.
However Ziglioli discloses The primary conductor 4 comprises a pair of surface mount connection terminals 13 configured for surface mount connection to conductive traces on an external circuit board, and a sensing portion 12 interconnecting the pair of surface mount connection terminals 13. The sensing portion 12 comprises a reduced conductive cross-sectional area in order to concentrate for the current to be measured (the primary current) and increase the intensity of the magnetic field around the sensing portion 12. The reduced cross-sectional area of the sensing portion 12 may for instance be formed by providing a slot 24 in the primary conductor between the connection terminals 13, [0037].
Ziglioli further discloses The magnetic field sensing portion 10 may comprise a Hall effect sensor, [0032].
In the same field of endeavor, Gagnon discloses The Hall effect element 18 generates a voltage output proportional to the magnetic field and therefore proportional to the current flowing through the current conductor portion 14, [0031].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Hall effect sensor to generate a voltage output proportional to the magnetic field and therefore proportional to the current flowing through the current conductor portion as taught by Gagnon to provide a more accurate measurement of the current flowing through the sensing portion 12 in Ziglioli. As a result, the signal output of the Hall effect sensor would indicate the strength of the magnetic field corresponding to the current flowing in 12 between leads 13.
Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ziglioli in view of Conru in view of Gagnon as applied to claim 5 above, and further in view of US 20200066970 A1 (“Hall”).
RE: Claim 6, the combination of Ziglioli, Conru does not explicitly disclose The apparatus of claim 5, and further comprising circuitry on the semiconductor die coupled to and configured to receive the signal output by the sensor and to output a voltage signal on one of the second leads that is proportional to the current flowing in the conductor of the first portion of the metal leadframe.
However, in the same field of endeavor, Gagnon discloses:
circuitry on the semiconductor die coupled to and configured to receive the signal output by the sensor (The Hall effect element 18 generates a voltage output proportional to the magnetic field and therefore proportional to the current flowing through the current conductor portion 14, [0031]; in response to opposite magnetic fields 112 a, 112 b the Hall effect elements 102 a, 102 b generate output voltages 103 a, 103 b having the same polarities, [0047]; The output voltage 103 a is coupled to amplifier 104 a arranged in a non-inverting configuration and the output voltage 103 b is coupled to the amplifier 104, [0047]; the amplifier output voltages 106 a, 106 b are differentially coupled to an amplifier 108 to generate a differential summation, or a difference of the output voltages 106 a, 106 b. Therefore, the output voltages 106 a, 106 b differentially sum to provide a greater output voltage 110 at the output of amplifier 108, [0047]; the summing circuit 100 is diffused into, or otherwise disposed upon, the second surface 76 b of the substrate 76, while the Hall effect elements 78 a, 78 b remain on the first surface 76 a, coupled to the other circuit components though vias or the like, [0048]; accordingly, this circuitry is provided on the substrate 76).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the circuitry on the IC chip 2 as taught by Gagnon to provide a greater output voltage and therefore increase the sensitivity of the current sensor.
In the same field of endeavor, Hall discloses:
circuitry configured to output a voltage signal on one of the second leads that is proportional to the current flowing in the conductor of the first portion of the metal leadframe (One or more bonded wire connections such as bonded wire connection 141 (which may be bonded to contact pads (not shown) on semiconductor die 230) may carry signals from semiconductor die 230 to the outside via lead frame 140, [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to carry the output voltage signal of the circuitry through bond pads 11, through bond wires 6 and to leads in 5 as taught by Hall to make the output voltage signal electrically accessible outside the package. As a result, the circuitry would be configured to output the amplified output voltage signal which is proportional to the current flowing in conductor 12 on the leads in 5.
Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ziglioli in view of Conru as applied to claim 1 above, and further in view of US20070209834A1 (“Kuan”).
RE: Claim 8, the combination of Ziglioli, Conru discloses The apparatus of claim 1, wherein the first leads and the second leads have exposed portions that are coextensive with surfaces of the package body to form terminals of a no lead package (In Ziglioli, FIGs. 1a-1c, 2 show leads of 4, 5 have exposed portions that are coextensive with surfaces of the package body to form terminals of a no lead package).
Additionally, if Ziglioli is considered not to disclose the package is a no lead package:
In the same field of endeavor, Kuan discloses package system 500 also includes a no-lead integrated circuit package 512, such as a quad flat no lead, a small outline no lead or a land grid array, having no-lead pads 514, [0059].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package in FIG. 2 to be no lead package in order to conserve spaced used by the package.
Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ziglioli in view of Conru as applied to claim 1 above, and further in view of US 20200035586 A1 (“Liong”).
RE: Claim 11, the combination of Ziglioli, Conru does not explicitly disclose The apparatus of claim 1, wherein the first leads are configured to be coupled to a voltage that is at least twenty volts.
In the same field of endeavor, Liong discloses the second face 134 of the signal lead 130 can be exposed on a same surface of a COL package as the faces 124a-124g (e.g., as another electrical contacts to a semiconductor die included in the COL package, such for a high voltage signal of 50 V or greater, [0019].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the leads 13 configured to be coupled to a high voltage signal of 50V or greater as taught by Liong to increase the voltage range of the signals coupled to the leads 13.
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ziglioli in view of Conru as applied to claim 2 above, and further in view of US 20200191835 A1 (“Bilbao”).
RE: Claim 12, the combination of Ziglioli, Conru does not explicitly disclose The apparatus of claim 2, wherein the conductor is configured to carry current that is greater than one ampere and up to seventy amperes.
However, in the same field of endeavor, Bilbao discloses The present invention relates in general to the field of current sensors, and more in particular current sensors capable of measuring a relatively high current (e.g. at least 30 Amps), [0001].
Bilbao further discloses a current sensor device 800, in top view and in cross sectional view respectively. The current sensor device 800 is a variant of the current sensor device 100 of FIG. 1(a). The main differences between the current sensor device 800 of FIG. 8(a) and the current sensor device 100 of FIG. 1(a) is that the electrical conductor 803 is not straight but is U-shaped. In the vicinity of the first and second magnetic sensor 811, 812, the electrical conductor 803 has an infinitesimal small beam-shaped conductor portion or a beam shaped conductor portion with an infinitesimally small length and the current to be measured (locally) flows in a direction substantially parallel to said centerline C, [0207].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the sensing portion 12 of the primary conductor 4 to be the beam shaped conductor as taught by Bilbao in order to sense relatively high currents of 30 Amps. As a result, the beam shaped conductor would be configured to carry a current of 30 Amps.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ziglioli in view of Conru as applied to claim 1 above, and further in view of US 20200381342 A1 (“Park”), further in view of US20240110950A1 (“Tanaka”).
RE: Claim 13, the combination of Ziglioli and Conru does not explicitly disclose The apparatus of claim 1, wherein the semiconductor die further comprises a passivation layer over the device side surface, and a distance from the device side surface through the passivation layer, the die attach material, the die attach film, through the isolation barrier, and to the board side surface of the metal leadframe, is less than or equal to 100 microns.
However, in the same field of endeavor, Park discloses passivation layer 112 abuts the active surface of the semiconductor die 108, and the passivation layer 112 has a thickness ranging from 1.0 microns to 1.5 microns, [0023]; and bond pads 114A, 114B are co-planar with the passivation layer 112 as shown in FIG. 1C, [0023].
Park further teaches that a thicker passivation layer 112 can increase the isolation barrier and provide better coverage for thicker metal on the die, [0023].
FIG. 1C shows the passivation layer 112 over the device side surface of the semiconductor die 108 and separating bond pads 114A, 114B from each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a passivation layer over the device side surface, the passivation layer having a larger thickness of 1.5 microns / micrometers as taught by Park in order to increase the isolation barrier and prevent short circuiting.
In the same field of endeavor, Tanaka discloses The adhesive layer 21, the adhesive layer 115, and the adhesive layer 116 have a desired thickness in the range from 1 μm to 50 μm, [0047].
Tanaka further discloses 114 is a semiconductor substrate that supports the magnetoelectric conversion element 20, [0045] and that substrate 114 is adhered to the IC supporting portion 112 via an adhesive layer 115, [0046].
FIG. 1B shows the substrate 114 adhered to the bottom of the IC supporting portion 112 via the adhesive layer 115.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the adhesive layer that is directly on the IC chip 2 (corresponding to the claimed die attach material) and the adhesive layer directly on the insulating film 8 (corresponding to the claimed die attach film) each have a thickness in the range from 1 μm to 50 μm such as 1-30 μm as taught by Tanaka in order to ensure the IC chip and the insulating sheet 8 are well adhered to the lead frame portion 4.
Additionally, Ziglioli discloses insulating sheet 8 is a polyimide, [0039].
Conru teaches The layer 11 can be formed, for example, of the polyimide film sold by the DuPont De Nemours Company under the tradename "Kapton". Such polyimide films are between 1.0 and 2.0 mils, Col. 3, lines 9-14.
1.1 mils is 1.1/1000 inches which is about 28 microns.
It would have been obvious to modify the thickness of the insulating sheet 8 to have a thickness of between 1 and 2 mils such as 1.1 mils as taught by Conru in order to provide sufficient level of isolation.
As a result, the distance from the device side surface through the passivation layer (1.5 microns), the die attach material (bottom glue would be 1-30 microns), the die attach film (upper adhesive would be 1-30 microns), through the isolation barrier (the insulating layer 8 would be 1.1 mils which is about 28 microns), and to a board side surface of the metal leadframe (bottom side of 4 which would be in direct contact with the adhesive layer on the insulating layer 8), would be between about 32 microns to less than about 90 microns which is less than 100 microns.
Claim 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ziglioli in view of Conru as applied to claim 1, further in view of Gagnon, and further in view of Hall.
RE: Claim 14, the combination of Ziglioli and Conru discloses The apparatus of claim 1, wherein the sensor is a Hall-effect device (Ziglioli discloses magnetic field sensing portion 10 is a Hall effect sensor, [0032]).
The combination of Ziglioli and Conru does not explicitly disclose the semiconductor die further comprises:
a precision amplifier coupled to receive a differential voltage from the Hall-effect device, the differential voltage being proportional to a magnetic field corresponding to a current flowing through conductor of the first portion of the metal leadframe; and
an output amplifier coupled to the precision amplifier to boost the differential output of the precision amplifier and to output an output signal that corresponds to the current flowing through the first portion of the metal leadframe,
the output signal coupled to one of the second leads of the second portion of the metal leadframe.
However, in the same field of endeavor, Gagnon discloses:
a semiconductor die (substrate 76 in FIG. 3, [0040]) further comprises:
a precision amplifier (amplifier 108, [0047], FIG. 4) coupled to receive a differential voltage from the Hall-effect device, the differential voltage being proportional to a magnetic field corresponding to a current flowing through conductor of the first portion of the metal leadframe (The Hall effect element 18 generates a voltage output proportional to the magnetic field and therefore proportional to the current flowing through the current conductor portion 14, [0031]; in response to opposite magnetic fields 112 a, 112 b the Hall effect elements 102 a, 102 b generate output voltages 103 a, 103 b having the same polarities, [0047]; The output voltage 103 a is coupled to amplifier 104 a arranged in a non-inverting configuration and the output voltage 103 b is coupled to the amplifier 104, [0047]; the amplifier output voltages 106 a, 106 b are differentially coupled to an amplifier 108 to generate a differential summation, or a difference of the output voltages 106 a, 106 b. Therefore, the output voltages 106 a, 106 b differentially sum to provide a greater output voltage 110 at the output of amplifier 108, [0047]); and
an output amplifier (another amplifier, [0052]; The summing circuit, for example, can include two of the summing circuits 100 of FIG. 4, [0052]; the summing circuit can couple a first two of the Hall effect elements 128 a-128 d with a first summing circuit, such as the summing circuit 100 of FIG. 4, and a second two of the Hall effect elements 128 a-128 d with a second summing circuit, such as the summing circuit 100. With another amplifier, an output of the first summing circuit can be summed with an output of the second summing circuit. As an initial advantage, the four Hall effect elements 128 a-128 d, coupled to a summing circuit as described, in the presence of the current, provide a voltage output four times the magnitude of a voltage output from a single Hall effect element, for example the Hall effect element 18 of FIG. 1, in the presence of the same current. Therefore, the current sensor 120 has four times the sensitivity of the current sensor 10 of FIG. 1, [0052]; the summing circuit 100 is diffused into, or otherwise disposed upon, the second surface 76 b of the substrate 76, while the Hall effect elements 78 a, 78 b remain on the first surface 76 a, coupled to the other circuit components though vias or the like, [0048]; accordingly, this circuitry is provided on the substrate 76) coupled to the precision amplifier to boost the differential output of the precision amplifier and to output an output signal that corresponds to the current flowing through the first portion of the metal leadframe.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuitry in the IC chip 2 to include the Hall effect elements, summing circuits, amplifiers 108, and another amplifier as taught by Gagnon in order to increase the sensitivity of the current sensor as further taught by Gagnon.
In the same field of endeavor, Hall discloses:
the output signal coupled to one of the second leads of the second portion of the metal leadframe (One or more bonded wire connections such as bonded wire connection 141 (which may be bonded to contact pads (not shown) on semiconductor die 230) may carry signals from semiconductor die 230 to the outside via lead frame 140, [0035]).
It would have been obvious to carry the output voltage signal of the circuitry through bond pads 11, through bond wires 6 and to leads in 5 as taught by Hall to make the output voltage signal electrically accessible outside the package. As a result, the output voltage signal would be coupled to the leads in 5.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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