DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claims 1 are objected to because of the following informalities:
Claim 1 recites “the first-conductivity-type regions” in lines 13 and 23 refer back to “a plurality of first-conductivity-type regions” in line 5 and should be amended to “the plurality of first-conductivity-type regions” for avoiding confusion. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites “the impurity of the second semiconductor layer is at least equal to the impurity concentration of the first-conductivity-type regions in lines 22-23 and “the impurity concentration in the second semiconductor layer increasing with reduced distance from the first semiconductor layer” in lines 24-25. It is unclear to the examiner how can the impurity concentration of the second semiconductor layer equal to the impurity concentration of the first-conductivity-type regions when it is increasing to different values as claimed.
Claim 1 recites “the impurity concentration in the second semiconductor layer increasing with reduced distance from the first semiconductor layer” in lines 24-25. It is unclear to the examiner how to determine the reduced distance from the first semiconductor layer when there is no reference location for measuring the reduced distance.
Claims 2-6 are rejected for being depended on claim 1 and having the above issues incorporating into the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kowalik-Seidl et al. (Pub. No.: US 2019/0148484 A1), hereinafter as Kowalik-Seidl.
Regarding claim 1, Kowalik-Seidl discloses a semiconductor device in Figs. 1 and 2A, comprising: a semiconductor substrate (semiconductor body 100) having a first main surface (first side 111) and a second main surface (second side 112) that are opposite to each other (see [0023-0024]); a parallel pn layer (charge compensation structure 121) in which a plurality of first-conductivity-type regions (plurality of regions 134 as n-columns) and a plurality of second-conductivity-type regions (plurality of regions 133 as p-columns) are disposed so as to be adjacent to one another and repeatedly alternate with one another, the parallel pn layer being provided in the semiconductor substrate (see Figs. 1, 2A, [0031], [0033], and [0036]); a device structure (combination of regions 131, 132, and 138 ) provided between the first main surface of the semiconductor substrate (first side 111) and the parallel pn layer (charge compensation structure 121) (see Fig. 1 and [0030]); a first semiconductor layer of a first conductivity type (drain region 135), the first semiconductor layer being provided between the second main surface of the semiconductor substrate (second side 112) and the parallel pn layer (charge compensation structure 121) and having an impurity concentration that is higher than an impurity concentration of the first-conductivity-type regions (impurity concentration of drain region 135 higher than impurity concentration of regions 134) (see Fig. 1 and [0026], [0044], [0047]); a second semiconductor layer of the first conductivity type (buffer region 150), the second semiconductor layer being provided between the first semiconductor layer (drain region 135) and the parallel pn layer (charge compensation structure 121) and having an impurity concentration that is lower than the impurity concentration of the first semiconductor layer (impurity concentration of buffer region 150 lower than impurity concentration of drain region 135) (see Fig. 1 and [0040-0041], [0047]); a first electrode (source metallization 145) provided on the first main surface, the first electrode being electrically connected to the device structure (see Fig. 1 and [0042]); and a second electrode (drain metallization 146) provided on the second main surface, the second electrode being electrically connected to the first semiconductor layer (see Fig. 1 and [0043]), wherein the impurity concentration of the second semiconductor layer is at least equal to the impurity concentration of the first-conductivity-type regions, the impurity concentration in the second semiconductor layer increasing with reduced distance from the first semiconductor layer (due to the 112 rejections presented above and for purpose of rejection, the assumption is made that the impurity concentration of the second semiconductor layer increasing as the depth of the impurity concentration profile approaching the top surface of the first semiconductor layer) (buffer region 150 have impurity concentration increasing from upper sub-region 151 to lower sub-region 153 that adjacent to the top surface of drain region 135) (see Fig. 1 and [0040-0041]).
Regarding claim 2, Kowalik-Seidl discloses the semiconductor device according to claim 1, wherein the second semiconductor layer is constituted by a plurality of first-conductivity-type layers (sub regions 151, 152 and 153) disposed in descending order of impurity concentration from the first semiconductor layer (see Fig. 1 and [0040-0041]), and the impurity concentration of each of the plurality of first-conductivity-type layers increases closer to the first semiconductor layer by a predetermined gradient (the gradient is determined by the increasing rate of three given values of impurity concentration of sub regions 151, 152 and 153) (see [0041]).
Regarding claim 3, Kowalik-Seidl discloses the semiconductor device according to claim 1, wherein a difference of impurity concentrations between an adjacent two of the plurality of first-conductivity-type layers in a depth direction is threefold or less (impurity concentration of sub-region 153 can be less than 3 times higher than 5x1016 cm-3) (see [0041]).
Regarding claim 4, Zeng discloses the semiconductor device according to claim 1, but fails to disclose wherein the impurity concentration of the second semiconductor layer is at least 1/200 times the impurity concentration of the first semiconductor layer at an interface between the second semiconductor layer and the first semiconductor layer (the impurity concentration of sub-region 153 can be 5x1016 cm-3 at the interface and which equal to 1/200 times of the impurity concentration of drain region 135 of 1x1019 cm-3) (see Fig. 1 and [0026], [0041]).
Regarding claim 5, Zeng discloses the semiconductor device according to claim 1, wherein the impurity concentration of the second semiconductor layer at a portion thereof facing the parallel pn layer is relatively low so as to approach the impurity concentration of the first-conductivity-type regions (the impurity concentration of sub-region 151 as approaching to regions 134 is relatively low compare to the impurity concentration of sub-region 153) (see Fig. 1 and [0041]).
Regarding claim 6, Zeng discloses the semiconductor device according to claim 1, wherein the second semiconductor layer is constituted by at least four first-conductivity-type layers that are stacked upon one another (the buffer region 150 may have four different sub-regions) (see [0066]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818