Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, with traverse, of claims 1-20 in the “Response to Restriction Requirement” filed on 01/29/2026 is acknowledged and entered by the Examiner.
Applicant’s arguments, in “Applicant Arguments/Remarks Made” with the reply “Response to Election / Restriction Filed” filed on 08/15/2016”, see “As shown above, Claim 11 recites a first integrated device, a second integrated device and a third integrated device. Claim 1 is supported by FIG. 1. Claim 11 is also supported by FIG. 1, which illustrates three (3) integrated devices” (remarks on page 11) have been fully considered.
The examiner has found the Applicant’s arguments to be persuasive. Therefore, the species restriction requirement between claims 1-10 and 11-20 as set forth in the Office action mailed on 12/02/2025 is hereby withdrawn.
In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a combination or divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 122, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
This office action consider claims 1-26 pending for prosecution, wherein claims 21-26 are withdrawn from further consideration, and claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1-5 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Burghartz et al. (US 5793272 A; hereinafter Burghartz).
Regarding claim 1, Burghartz teaches a device (see the entire document, specifically Fig. 1+; C1 L6+, and as cited below), comprising (see alternative rejection for claim 1, below):
a die substrate (12; Figs. 9-11; see C4 L60-67; see C7 L47-53);
a plurality of interconnects ({104, 26, 110}; Figs. 9-11; see C7 L30-67; see C8 L1-14) located over the die substrate (12; Figs. 9-11; see C4 L60-67; see C7 L47-53),
wherein the plurality of interconnects ({104, 26, 110}; Figs. 9-11; see C7 L30-67; see C8 L1-14) comprise:
a first plurality of plate interconnects ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14);
a second plurality of plate interconnects ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14); and
a plurality of via interconnects ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14) coupled to the first plurality of plate interconnects ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14) and the second plurality of plate interconnects ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14), and
wherein the first plurality of plate interconnects ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14), the plurality of via interconnects ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14), and the second plurality of plate interconnects ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14) are configured to operate as an inductor (see C7 L30-67);
at least one magnetic layer (18’; Figs. 9-11; see C8 L1-14) that surrounds at least part of the plurality of via interconnects ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14) ; and
at least one dielectric layer (14; Figs. 9-11; see C7 L38-46) located over the die substrate (12; Figs. 9-11; see C4 L60-67; see C7 L47-53).
Regarding claim 2, Burghartz teaches all of the features of claim 1.
Burghartz further teaches wherein the plurality of interconnects ({104, 26, 110}; Figs. 9-11; see C7 L30-67; see C8 L1-14) comprises a first via interconnect ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14) and a second via interconnect ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14), and
wherein the at least one magnetic layer (18’; Figs. 9-11; see C7 L30-67; see C8 L1-14) laterally surrounds and touches (i) the first via interconnect ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14), and (ii) the second via interconnect ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14).
Regarding claim 3, Burghartz teaches all of the features of claim 1.
Burghartz further teaches
wherein a plate interconnect ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the first plurality of plate interconnects ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14) includes a first width,
wherein a plate interconnect ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the second plurality of plate interconnects ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14) includes a second width,
wherein a via interconnect ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the plurality of via interconnects ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14) includes a via width, and
wherein the first width (width of {104}; Figs. 10-11; see C7 L30-67; see C8 L1-14) and the second width (width of {110}; Figs. 10-11; see C7 L30-67; see C8 L1-14) are each at least twice as wide as the via width (width of {26}; Figs. 10-11; see C7 L30-67; see C8 L1-14).
Regarding claim 4, Burghartz teaches all of the features of claim 3.
Burghartz further teaches
wherein the first plurality of plate interconnects ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14) are aligned in a first direction,
wherein the second plurality of plate interconnects ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14) are aligned in a second direction, and
wherein an electrical path through the inductor includes a first plate interconnect ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the first plurality of plate interconnects ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14),
a first plurality of via interconnects ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the plurality of via interconnects ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14),
a first plate interconnect ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the second plurality of plate interconnects ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14),
a second plurality of via interconnects ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the plurality of via interconnects ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14),
a second plate interconnect ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the first plurality of plate interconnects ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14),
a third plurality of via interconnects ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the plurality of via interconnects ({26}; Figs. 9-11; see C7 L30-67; see C8 L1-14), and a second plate interconnect ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the second plurality of plate interconnects ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14).
Regarding claim 5, Burghartz teaches all of the features of claim 4.
Burghartz further teaches wherein the first plate interconnect ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the first plurality of plate interconnects ({104}; Figs. 9-11; see C7 L30-67; see C8 L1-14) includes a first slot, and wherein the second plate interconnect ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14) from the second plurality of plate interconnects ({110}; Figs. 9-11; see C7 L30-67; see C8 L1-14) includes a second slot.
Regarding claim 9, Burghartz teaches all of the features of claim 1.
Burghartz further teaches wherein the at least one magnetic layer (18’; Figs. 9-11; see C5 L 38-44; see C8 L1-14) has a relative permeability value that is greater than 1 (magnetic material; see C5 L 38-44; see C8 L1-14).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
3. Claims 1, 6-8, 10, 11-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 20220085143 A1; hereinafter Choi).
Regarding claim 1, Choi teaches a device (see the entire document, specifically Fig. 1A+; [0005+], and as cited below), comprising (see alternative rejection for claim 1, above):
a die substrate (852; see Figs. 8A-8B; see [0054-0055]; a lower level of layer 852);
a plurality of interconnects ({862, 830A, 830B, 863}; see Figs. 8A-8B; see [0052-0055]) located over the die substrate (852; see Figs. 8A-8B; see [0054-0055]),
wherein the plurality of interconnects ({862, 830A, 830B, 863}; see Figs. 8A-8B; see [0052-0055]) comprise:
a first plurality of plate interconnects ({862}; see Figs. 8A-8B; see [0052-0055]);
a second plurality of plate interconnects ({863}; see Figs. 8A-8B; see [0052-0055]); and
a plurality of via interconnects ({830A, 830B}; see Figs. 8A-8B; see [0052-0055]) coupled to the first plurality of plate interconnects ({862}; see Figs. 8A-8B; see [0052-0055]) and the second plurality of plate interconnects ({863}; see Figs. 8A-8B; see [0052-0055]), and
wherein the first plurality of plate interconnects ({862}; see Figs. 8A-8B; see [0052-0055]), the plurality of via interconnects ({830A, 830B }; Figs. 9-11; see C7 L30-67; see C8 L1-14), and the second plurality of plate interconnects ({863}; see Figs. 8A-8B; see [0052-0055]) are configured to operate as an inductor (860; see Figs. 8A-8B; see [0052-0055]);
at least one magnetic layer (310; Figs. 8A-8B in view of Figs. 3A, 3B; [0053] in view of [0036-0038]; see [0053] , where it says the interconnects 830 may be substantially similar to one or more of the interconnects described above. For example, the interconnects 830 may comprise a conductive core that is surrounded by a magnetic sheet. The magnetic sheet may comprise one or more magnetic layers and one or more insulating layers) that surrounds at least part of the plurality of via interconnects ({830A, 830B }; Figs. 9-11; see C7 L30-67; see C8 L1-14); and
at least one dielectric layer (312A; Figs. 8A-8B in view of Figs. 3A, 3B; [0053] in view of [0036-0038]; see [0053] , where it says the interconnects 830 may be substantially similar to one or more of the interconnects described above. For example, the interconnects 830 may comprise a conductive core that is surrounded by a magnetic sheet. The magnetic sheet may comprise one or more magnetic layers and one or more insulating layers) located over the die substrate (852; see Figs. 8A-8B; see [0054-0055]).
Regarding claim 6, Choi teaches all of the features of claim 1.
Choi further comprising a plurality of transistors located in the die substrate (852; see Figs. 8A-8B; see [0054-0055] in view of [0059-0063]).
Regarding claim 7, Choi teaches all of the features of claim 1.
Choi further teaches wherein the at least one magnetic layer (310; Figs. 8A-8B in view of Figs. 3A, 3B; [0053] in view of [0036-0038]; see [0053] , where it says the interconnects 830 may be substantially similar to one or more of the interconnects described above. For example, the interconnects 830 may comprise a conductive core that is surrounded by a magnetic sheet. The magnetic sheet may comprise one or more magnetic layers and one or more insulating layers) includes an insulating layer and/or a dielectric layer.
Regarding claim 8, Choi teaches all of the features of claim 1.
Choi further teaches wherein the at least one magnetic layer (310; Figs. 8A-8B in view of Figs. 3A, 3B; [0053] in view of [0036-0038]; see [0053] , where it says the interconnects 830 may be substantially similar to one or more of the interconnects described above. For example, the interconnects 830 may comprise a conductive core that is surrounded by a magnetic sheet. The magnetic sheet may comprise one or more magnetic layers and one or more insulating layers) includes a non- electrical conducting material.
Regarding claim 10, Choi teaches all of the features of claim 1.
Choi further teaches wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (see [0061-0063]).
Regarding claim 11, Choi teaches a device (see the entire document, specifically Fig. 1A+; [0005+], and as cited below), comprising:
(i) a first integrated device (800/900; Fig. 9 in view of Figs. 8A-8B, 3A-3B; see [0056-0058]; see [0057], where it states the electronic package 900 may be substantially similar to any of the electronic packages described above. Particularly, the electronic package 900 may comprise one or more magnetic interconnects) comprising:
a die substrate (852; see Fig. 9 in view of Figs. 8A-8B, 3A-3B; see [0054-0055]; a lower level of layer 852;);
a plurality of interconnects ({862, 830A, 830B, 863}; see Figs. 8A-8B; see [0052-0055]) located over the die substrate (852; see Fig. 9 in view of Figs. 8A-8B, 3A-3B; see [0054-0055]; a lower level of layer 852; see [0057], where it states the electronic package 900 may be substantially similar to any of the electronic packages described above. Particularly, the electronic package 900 may comprise one or more magnetic interconnects),
wherein the plurality of interconnects ({862, 830A, 830B, 863}; see Figs. 8A-8B; see [0052-0055]) comprise:
a first plurality of plate interconnects ({862}; see Figs. 8A-8B; see [0052-0055]);
a second plurality of plate interconnects ({863}; see Figs. 8A-8B; see [0052-0055]); and
a plurality of via interconnects ({830A, 830B}; see Figs. 8A-8B; see [0052-0055]) coupled to the first plurality of plate interconnects ({862}; see Figs. 8A-8B; see [0052-0055]) and the second plurality of plate interconnects ({863}; see Figs. 8A-8B; see [0052-0055]), and
wherein the first plurality of plate interconnects ({862}; see Figs. 8A-8B; see [0052-0055]), the plurality of via interconnects ({830A, 830B }; Figs. 9-11; see C7 L30-67; see C8 L1-14), and the second plurality of plate interconnects ({863}; see Figs. 8A-8B; see [0052-0055]) are configured to operate as an inductor (860; see Figs. 8A-8B; see [0052-0055]);
at least one magnetic layer (310; Figs. 8A-8B in view of Figs. 3A, 3B; [0053] in view of [0036-0038]; see [0053] , where it says the interconnects 830 may be substantially similar to one or more of the interconnects described above. For example, the interconnects 830 may comprise a conductive core that is surrounded by a magnetic sheet. The magnetic sheet may comprise one or more magnetic layers and one or more insulating layers) that surrounds at least part of the plurality of via interconnects ({830A, 830B }; Figs. 9-11; see C7 L30-67; see C8 L1-14); and
at least one dielectric layer (312A; Figs. 8A-8B in view of Figs. 3A, 3B; [0053] in view of [0036-0038]; see [0053] , where it says the interconnects 830 may be substantially similar to one or more of the interconnects described above. For example, the interconnects 830 may comprise a conductive core that is surrounded by a magnetic sheet. The magnetic sheet may comprise one or more magnetic layers and one or more insulating layers) located over the die substrate (852; see Figs. 8A-8B; see [0054-0055]).
(ii) a second integrated device (993; Fig. 9 in view of Figs. 8A-8B, 3A-3B; see [0058] in view of [0002, 0023]; VR/Voltage Regulator) configured as a power management integrated device, wherein the second integrated device is configured to be electrically coupled to the first integrated device (800/900; Fig. 9 in view of Figs. 8A-8B, 3A-3B; see [0056-0058]; see [0057], where it states the electronic package 900 may be substantially similar to any of the electronic packages described above. Particularly, the electronic package 900 may comprise one or more magnetic interconnects) through a first electrical path (994); and
(iii) a third integrated device (991; Fig. 9 in view of Figs. 8A-8B, 3A-3B; see [0056]) configured to be electrically coupled to the first integrated device (800/900; Fig. 9 in view of Figs. 8A-8B, 3A-3B; see [0056-0058]; see [0057], where it states the electronic package 900 may be substantially similar to any of the electronic packages described above. Particularly, the electronic package 900 may comprise one or more magnetic interconnects) through a second electrical path (992).
Regarding claim 12, Choi teaches all of the features of claim 11.
Choi further teaches wherein the plurality of interconnects ({862, 830A, 830B, 863}; see Figs. 8A-8B; see [0052-0055]) comprises a first via interconnect ({830A}; Figs. 9-11; see C7 L30-67; see C8 L1-14)and a second via interconnect ({830B }; Figs. 9-11; see C7 L30-67; see C8 L1-14), and wherein the at least one magnetic layer (310; Figs. 8A-8B in view of Figs. 3A, 3B; [0053] in view of [0036-0038]; see [0053] , where it says the interconnects 830 may be substantially similar to one or more of the interconnects described above. For example, the interconnects 830 may comprise a conductive core that is surrounded by a magnetic sheet. The magnetic sheet may comprise one or more magnetic layers and one or more insulating layers) laterally surrounds and touches (i) the first via interconnect ({830A}; Figs. 9-11; see C7 L30-67; see C8 L1-14), and (ii) the second via interconnect ({830B}; Figs. 9-11; see C7 L30-67; see C8 L1-14).
Regarding claim 13, Choi teaches all of the features of claim 11.
Choi further teaches wherein a plate interconnect ({862}; see Figs. 8A-8B; see [0052-0055]) from the first plurality of plate interconnects ({862}; see Figs. 8A-8B; see [0052-0055]) includes a first width, wherein a plate interconnect from the second plurality of plate interconnects ({863}; see Figs. 8A-8B; see [0052-0055]) includes a second width, wherein a via interconnect ({830A}; see Figs. 8A-8B; see [0052-0055]) from the plurality of via interconnects ({830A, 830B}; see Figs. 8A-8B; see [0052-0055]) includes a via width, and wherein the first width (width of {862}; see Figs. 8A-8B; see [0052-0055]) and the second width (width of {863}; see Figs. 8A-8B; see [0052-0055]) are each at least twice as wide as the via width (width of {830A}; see Figs. 8A-8B; see [0052-0055]).
Regarding claim 14, Choi teaches all of the features of claim 13.
Choi further teaches wherein the first plurality of plate interconnects ({862}; see Figs. 8A-8B; see [0052-0055]) are aligned in a first direction, wherein the second plurality of plate interconnects ({863}; see Figs. 8A-8B; see [0052-0055]) are aligned in a second direction, and wherein an electrical path through the inductor includes a first plate interconnect from the first plurality of plate interconnects ({862}; see Figs. 8A-8B; see [0052-0055]), a first plurality of via interconnects from the plurality of via interconnects ({830A, 830B}; see Figs. 8A-8B; see [0052-0055]), a first plate interconnect from the second plurality of plate interconnects ({863}; see Figs. 8A-8B; see [0052-0055]), a second plurality of via interconnects from the plurality of via interconnects ({830A, 830B}; see Figs. 8A-8B; see [0052-0055]), a second plate interconnect from the first plurality of plate interconnects ({862}; see Figs. 8A-8B; see [0052-0055]), a third plurality of via interconnects from the plurality of via interconnects ({830A, 830B}; see Figs. 8A-8B; see [0052-0055]), and a second plate interconnect from the second plurality of plate interconnects ({863}; see Figs. 8A-8B; see [0052-0055]).
Regarding claim 15, Choi teaches all of the features of claim 14.
Choi further teaches wherein the first plate interconnect ({862}; see Figs. 8A-8B; see [0052-0055]) from the first plurality of plate interconnects ({862}; see Figs. 8A-8B; see [0052-0055]) includes a first slot, and wherein the second plate interconnect ({863}; see Figs. 8A-8B; see [0052-0055]) from the second plurality of plate interconnects ({863}; see Figs. 8A-8B; see [0052-0055]) includes a second slot.
Regarding claim 16, Choi teaches all of the features of claim 11.
Choi further comprising a plurality of transistors located in the die substrate (852; see Figs. 8A-8B; see [0054-0055] in view of [0059-0063]).
Regarding claim 17, Choi teaches all of the features of claim 11.
Choi further teaches wherein the at least one magnetic layer (310; Figs. 8A-8B in view of Figs. 3A, 3B; [0053] in view of [0036-0038]; see [0053] , where it says the interconnects 830 may be substantially similar to one or more of the interconnects described above. For example, the interconnects 830 may comprise a conductive core that is surrounded by a magnetic sheet. The magnetic sheet may comprise one or more magnetic layers and one or more insulating layers) includes an insulating layer, a dielectric layer and/or a non-electrical conducting material, and wherein the at least one magnetic layer (310; Figs. 8A-8B in view of Figs. 3A, 3B; [0053] in view of [0036-0038]; see [0053] , where it says the interconnects 830 may be substantially similar to one or more of the interconnects described above. For example, the interconnects 830 may comprise a conductive core that is surrounded by a magnetic sheet. The magnetic sheet may comprise one or more magnetic layers and one or more insulating layers) has a relative permeability value that is greater than 1 (magnetic material; see [0053] in view of [0036-0038]).
Regarding claim 19, Choi teaches all of the features of claim 11.
Choi further teaches wherein the first integrated device (800/900; Fig. 9 in view of Figs. 8A-8B, 3A-3B; see [0056-0058]; see [0057], where it states the electronic package 900 may be substantially similar to any of the electronic packages described above. Particularly, the electronic package 900 may comprise one or more magnetic interconnects) and the second integrated device (993; Fig. 9 in view of Figs. 8A-8B, 3A-3B; see [0058] in view of [0002, 0023]; VR/Voltage Regulator) are part of a power distribution network (PDN) ([0002, 0023, 0058, 0060]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
4. Claim 18 is rejected under 35 U.S.C.103 as being unpatentable over Choi et al. (US 20220085143 A1; hereinafter Choi, in view of the following statement.
Regarding claim 18, Choi teaches all of the features of claim 11.
Choi further teaches wherein the first electrical path (994; Fig. 9 in view of Figs. 8A-8B, 3A-3B; see [0056-0058]) is configured as an electrical path for power having a first voltage, and wherein the second electrical path (992; Fig. 9 in view of Figs. 8A-8B, 3A-3B; see [0056-0058]) is configured as an electrical path for power having a second voltage that (see below for “is different than”) the first voltage.
As noted above, Choi does not expressly disclose “wherein the first electrical path is configured as an electrical path for power having a first voltage, and wherein the second electrical path is configured as an electrical path for power having a second voltage that is different than the first voltage”.
However, it has been held that “wherein the first electrical path is configured as an electrical path for power having a first voltage, and wherein the second electrical path is configured as an electrical path for power having a second voltage that is different than the first voltage” will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such wherein the first electrical path is configured as an electrical path for power having a first voltage, and wherein the second electrical path is configured as an electrical path for power having a second voltage that is different than the first voltageis critical, “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation”. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). In this case, there is nothing in the present application to indicate that the claimed containing wherein the first electrical path is configured as an electrical path for power having a first voltage, and wherein the second electrical path is configured as an electrical path for power having a second voltage that is different than the first voltageis critical and will achieve unexpected results over the range outside of the claimed range. Therefore, it would have been obvious wherein the first electrical path is configured as an electrical path for power having a first voltage, and wherein the second electrical path is configured as an electrical path for power having a second voltage that is different than the first voltage as claimed in device because wherein the first electrical path is configured as an electrical path for power having a first voltage, and wherein the second electrical path is configured as an electrical path for power having a second voltage that is different than the first voltage can be optimized during routine experimentation depending upon a particular application which is desired.
The applicants have not established the criticality (see next paragraph below) of said first predetermined amount.
The specification contains no disclosure of either the critical nature of the claimed distance or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Conclusion
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898
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