DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 12/15/2025 in response to the Office Action mailed on 09/17/2025 is
being acknowledged and entered into the record. The present Non-Final rejection is made by taking into fully consideration all the amendments.
Response to Arguments
Applicant’s arguments, see pages 8-9 of the remarks, filed on 12/15/2025, with respect to 112(b) rejection of Claims 2, 4, 5, 7, 11, and 12 have been fully considered and are persuasive. The rejection of claims 2, 4, 5, 7, 11, and 12 has been withdrawn.
On pages 10-11 of the remarks, filed on 12/15/2025, with respect to the 102 rejection of Claim 1 and 103 rejection of Claim 15, Applicant argues that the thermal conductive layer 106 in Tain is located over a top and side surface of the substrate 102 and thus covers a larger area of surface of the substrate than that of the heat conduction adjusting layer 3 of the present application, and the thermal conductive layer 106 and the connecting circuit 114 are not arranged side-by-side. Applicant further argues that the other cited documents also fail to disclose or suggest "the heat conduction adjusting laver 3 is arranged side-by-side with the circuit module 212 located on the surface of the substrate". These arguments are fully considered but are not persuasive. MPEP § 2111 discusses proper claim interpretation, including giving claims their broadest reasonable interpretation in light of the specification during examination. Under broadest reasonable interpretation, the words of a claim must be given their plain meaning unless such meaning is inconsistent with the specification, and it is improper to import claim limitations from the specification into the claim. As such, the BRI of the claim language of claim 1 does not limit the extent of the thermal conductive layer on the substrate or exclude its placement on a side of the substrate. Further, while Fig. 5 of Tain shows the circuit module 114 embedded into the substrate 102, paragraph 0021 states that the circuit module 114 can be disposed on a surface of the substrate 102. Therefore, a person of ordinary skill in the art would have recognized that when the circuit module 114 is disposed on the surface of the substrate 102, the heat conduction adjusting layer 106 will be arranged side-by-side with the circuit module 114 located on the surface of the substrate 102. Therefore, Tain is still relied upon to teach some of the limitations of Claim 1 and Claim 15.
On page 11 of the remarks, filed on 12/15/2025, with respect to the 102 rejection of Claim 1 and 103 rejection of Claim 15, Applicant argues that Tain does not disclose any description of the specific structural composition and connection relationship for the signal lines 134 which was mapped onto the external circuit of the base of the present application recited in previous Claim 8 and present amended Claims 1 and 15. This argument is fully considered and is persuasive. However, Examiner wishes to point out that signal lines 134 was erroneously cited in place of the thermal conductive elements 136 of the base 133. Paragraph 0030 of Tain explicitly teaches the thermal conductive elements 136 refer to connecting circuits disposed in the base 133. Therefore, Tain is still relied upon to teach some of the limitations of Claim 1 and Claim 15 with appropriate corrections made in the rejection below .
On page 11 of the remarks, filed on 12/15/2025, with respect to the 102 rejection of Claim 1 and 103 rejection of Claim 15, Applicant argues that the prior art of record fails to disclose or suggest the technical features of "wherein the conductive structure 4 comprises a connection pad 41 and a conductive bump 42, the connection pad 41 is provided on a surface, close to the base 1, of the substrate 211 of the chip unit 21 closest to the base 1 in the chipset 2, the conductive bump 42 is located between the connection pad 41 and the external circuit 11 of the base, both ends of the conductive bump 42 are in contact with the connection pad 41 and the external circuit 11, respectively" of the present application. This argument is fully considered and is persuasive. Therefore, the rejection of Claims 1 and 15 is withdrawn. However, upon further consideration, a new ground of 103 rejections are made for Claims 1 and 15 in view of previously applied reference and newly found prior art reference of Hsu. Hsu teaches the newly added limitations of claims 1 and 15 as outlined in the rejection below.
On page 11 of the remarks, filed on 12/15/2025, with respect to the 102 rejection of Claim 1, Applicant argues that while the amended claim can reduce the difference of heat conduction rates between the circuit interconnection region and the non-circuit interconnection region and achieve better circuit connections, there are no technical inspirations in "Tain" or/and other cited documents to teach how to achieve the aforementioned technical effects. These arguments are fully considered but are not persuasive. According to MPEP § 2112.01 (I), “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established”. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). As such, the claimed semiconductor structure is substantially similar in structure to that of Tain and would therefore result in the claimed properties. Therefore, Tain is still relied upon to teach some of the limitations of Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitations are limitations not explicitly disclosed in the primary
reference but disclosed in the secondary reference(s).
Claims 1 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Tain et al. (US 20090294947 A1), in view of Hsu (US 20060163722 A1).
Regarding Claim 1, Tain et al. discloses a semiconductor structure, comprising:
a base 133 (Fig. 5: 133, paragraph 0048);
a chipset disposed at one side of the base 133 and comprising multiple chip units 500 arranged at intervals along a direction perpendicular to the base 133 (annotated Fig. 5: chipset, 500, 133, paragraph 0048),
wherein each of the chip units 500 comprises a substrate 102 and a circuit module 114 disposed on a surface of the substrate 102 (annotated Fig. 5: 500, 102, 114, paragraph 0021),
Note that while Fig. 5 shows the circuit module 114 as an interconnect located in the substrate 102, paragraph 0021 mentions that circuit module 114 can be located on the surface of the substrate 102.
the substrate 102 comprises a circuit interconnection region 118 and a non-circuit interconnection region distributed adjacently (annotated Fig. 5: 102, 118, non-circuit interconnection region, paragraph 0021),
the circuit module 114 is disposed on a surface of the circuit interconnection region 118 (annotated Fig. 5: 114, 118, paragraph 0021),
Since the circuit module 114 can be located on the surface of the substrate 102 according to paragraph 0021, the circuit module 114 will be disposed on a surface of the circuit interconnection region 118.
and two adjacent ones of the chip units 500 are electrically connected through the circuit module 114 (see annotated Fig. 5: 500, 114, paragraph 0021);
and a heat conduction adjusting layer 106 in contact with at least one of the substrates 102 for reducing difference of heat conduction rates between surfaces of the substrates 102 (annotated Fig. 5: 106, paragraph 0023, 0048).
wherein the heat conduction adjusting layer 106 is located on one side of the substrate 102 away from the base 133 and is arranged side-by-side with the circuit module 114 located on the surface of the substrate 102 (Fig. 5: 133, 106, 102, 114, paragraph 0030);
Note that while Fig. 5 shows the circuit module 114 embedded into the substrate 102, paragraph 0021 states that the circuit module 114 can be disposed on a surface of the substrate 102. Therefore, a person of ordinary skill in the art would have recognized that when the circuit module 114 is disposed on the surface of the substrate 102, the heat conduction adjusting layer 106 will be arranged side-by-side with the circuit module 114 located on the surface of the substrate 102.
wherein the base 133 comprises an external circuit 136 (Fig. 5: 136, paragraph 0030),
the semiconductor structure further comprises a conductive structure located between the chipset and the base, one end of the conductive structure is electrically connected with any one of the chip units, and another end is connected with the external circuit of the base:
wherein the conductive structure comprises a connection pad and a conductive bump, the connection pad is provided on a surface, close to the base, of the substrate of the chip unit closest to the base in the chipset, the conductive bump is located between the connection pad and the external circuit of the base, both ends of the conductive bump are in contact with the connection pad and the external circuit, respectively.
Hsu teaches a semiconductor structure comprising the following limitations not disclosed in Tain et al.
the semiconductor structure further comprises a conductive structure 200, 20a located between the chipset 20 and the base 26, one end of the conductive structure 200, 20a is electrically connected with any one of the chip units 20, and another end is connected with the external circuit 250 of the base 26 (Fig. 3C: 200, 20a, 250, 26, paragraph 0024, 0030, 0033),
wherein the conductive structure 200, 20a comprises a connection pad 200 and a conductive bump 20a, the connection pad 200 is provided on a surface, close to the base of the substrate of the chip unit closest to the base 26 in the chipset 20, the conductive bump 20a is located between the connection pad 200 and the external circuit of the base 250, both ends of the conductive bump 20a are in contact with the connection pad 200 and the external circuit 250, respectively (Fig. 3C: 200, 20a, 250, 26, paragraph 0024, 0030, 0033).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Tain et al. and Hsu in order to come up with the claimed invention as recited in Claim 1. By doing so, the conductive structure would create a direct electrical connection between the chip set and the external circuit of the base.
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Annotated Fig. 5 of Tain et al. (US 20090294947 A1)
Regarding Claim 9, Tain et al. discloses the semiconductor structure of claim 1, wherein a concave part 132 depressed inwards in the direction perpendicular to the substrate 102 is disposed in a surface of the substrate 102 facing away from the base 133, and the heat conduction adjusting layer 106 is located at least in the concave part 132 (Fig. 5: 132, 133, 102, paragraph 0038).
Regarding Claim 10, Tain et al. discloses the semiconductor structure of claim 1, wherein the heat conduction adjusting layer 106 is disposed on a surface of the substrate 102 facing away from the base 133 (see Fig. 5: 106, 102, 133).
Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Tain et al. (US 20090294947 A1), in view of Hsu (US 20060163722 A1), as applied to Claim 1 above, further in view of Wang (CN 110943001 A).
Regarding Claim 2, Tain et al. teaches the semiconductor structure of claim 1, wherein the heat conduction adjusting layer 106 is disposed in the circuit interconnection region 118 of the substrate 102 (see Fig. 5: 106, 118), but fails to teach a heat conduction rate of the heat conduction adjusting layer 106 is lower than a heat conduction rate of the circuit interconnection region of the substrate 102.
However, Wang discloses a semiconductor structure, wherein a heat conduction rate of the heat conduction adjusting layer 4 is lower than a heat conduction rate of the circuit interconnection region of the substrate 1 (Fig. 1: 1, 4, page 6, lines 19-31, page 3, line 23-26, page 5, lines 13-23).
Note that the middle portion of the substrate 1 housing the chips 3 is interpreted as the circuit interconnect region of the substrate 1. Additionally, the high thermal conductivity substrate 1 is made of silicon carbide (page 3, lines 23-24), which has a high thermal conductivity of 120 W m-1 K-1 (See Silicon Carbide Engineering Properties. Datasheet [online]. Accuratus Ceramic Corporation,
November 2002 [retrieved on 09-03-2025]. Retrieved from the Internet: <URL:
https://accuratus.com/silicar.html>). Furthermore, the heat conduction adjusting layer 4 is a thermal resistance layer formed of Polymethylmethacrylate (PMMA) (see page 5, lines 13-23), therefore has a lower heat conduction rate and a lower thermal conductivity of [Symbol font/0x7E]0.17 W m-1 K-1 (see Properties of PMMA. Datasheet [online]. PolyPlasty.cz, August 2020 [retrieved on 09-03-2025]. Retrieved from the Internet: <URL: https://www.polyplasty.cz/polymethylmethakrylat.html>). Therefore, the heat conduction rate of the heat conduction adjusting layer 4 will be lower than the heat conduction rate of the circuit interconnection region of the substrate 1.
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of both Tain et al. and Wang in order to have the heat conduction rate of the heat conduction adjusting layer to be lower than the heat conduction rate of the circuit interconnection region of the substrate. Doing so would effectively dissipate the heat generated by the chipset, as recognized by Wang (page 2, lines 16-20).
Note that Claim 2 is examined based on the interpretation provided under the 112(b) rejection above.
Regarding Claim 5, Tain et al. teaches the semiconductor structure of claim 1, wherein the heat conduction adjusting layer 106 is located at least on a surface of the circuit interconnection region 118 of the substrate 102 in the chip unit farthest away from the base 133 (i.e., the third adjusting part in annotated Fig. 5: 106, 133, 118, 102), but fails to teach a heat conduction rate of the heat conduction adjusting layer is lower than a heat conduction rate of the circuit interconnection region of the substrate 102 in the chip unit farthest away from the base 133.
However, Wang discloses a semiconductor structure, wherein a heat conduction rate of the heat conduction adjusting layer 4 is lower than a heat conduction rate of the circuit interconnection region of the substrate 1 (See rejection of Claim 2 above, Fig. 1: 1, 4, page 6, lines 19-31, page 3, line 23-26, page 5, lines 13-23).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of both Tain et al. and Wang in order to have the heat conduction rate of the heat conduction adjusting layer to be lower than the heat conduction rate of the circuit interconnection region of the substrate in the chip unit farthest away from the base. Doing so would effectively dissipate the heat generated by the chipset, as recognized by Wang (page 2, lines 16-20).
Note that Claim 5 is examined based on the interpretation provided under the 112(b) rejection above.
Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Tain et al. (US 20090294947 A1), in view of Hsu (US 20060163722 A1), as applied to Claim 1 above, further in view of Wang (CN 110943001 A), and Kim et al. (US 20230124783 A1).
Regarding Claim 4, Tain et al. teaches the semiconductor structure of claim 1, wherein the heat conduction adjusting layer 106 comprises a first adjusting part and a second adjusting part, the first adjusting part is located on a surface of the circuit interconnection region 118 of the substrate 102, the second adjusting part is located on a surface of the non-circuit interconnection region of the substrate 102,
Tain et al. fails to explicitly teach a heat conduction rate of the first adjusting part is lower than a heat conduction rate of the circuit interconnection region of the substrate, and a heat conduction rate of the second adjusting part is greater than a heat conduction rate of the non-circuit interconnection region of the substrate.
However, Wang discloses a semiconductor structure, wherein a heat conduction rate of the first adjusting part (of the heat conduction adjusting layer 4) is lower than a heat conduction rate of the circuit interconnection region of the substrate 1 (Fig. 1: 1, 4, page 6, lines 19-31, page 3, line 23-26, page 5, lines 13-23 in English Translation of Wang).
Note that the middle portion of the substrate 1 housing the chips 3 is interpreted as the circuit interconnect region of the substrate 1 and the portion of the heat conduction adjusting layer 4 overlapping the chips 3 is interpreted as the first adjusting part. Moreover, the high thermal conductivity substrate 1 is made of silicon carbide (page 3, lines 23-24 in English Translation of Wang), which has a high thermal conductivity of 120 W m-1 K-1 (See Silicon Carbide Engineering Properties. Datasheet [online]. Accuratus Ceramic Corporation, November 2002 [retrieved on 09-03-2025]. Retrieved from the Internet: <URL: https://accuratus.com/silicar.html>). Furthermore, the heat conduction adjusting layer 4 is a thermal resistance layer formed of Polymethylmethacrylate (PMMA) (see page 5, lines 13-23 in English Translation of Wang et al.), therefore has a lower heat conduction rate and a lower thermal conductivity of [Symbol font/0x7E]0.17 W m-1 K-1 (see Properties of PMMA. Datasheet [online]. PolyPlasty.cz, August 2020 [retrieved on 09-03-2025]. Retrieved from the Internet: <URL: https://www.polyplasty.cz/polymethylmethakrylat.html>). Therefore, the heat conduction rate of the heat conduction adjusting layer 4 will be lower than the heat conduction rate of the circuit interconnection region of the substrate 1.
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of both Tain et al. and Wang in order to have the heat conduction rate of the first adjusting part to be lower than the heat conduction rate of the circuit interconnection region of the substrate. Doing so would effectively dissipate the heat generated by the chipset, as recognized by Wang et al. (page 4, lines 16-20 in English Translation of Wang et al.).
Furthermore, Kim et al. discloses a semiconductor structure, comprising a heat conduction adjusting layer 700 with a second adjusting part disposed in the non-circuit interconnection region of the substrate 101 (see annotated Fig. 1A:700, 101, paragraph 0029, 0031, 0051-0053). Further, Kim et al. teaches the substrate 101 is made of silicon (paragraph 0031), which has a thermal conductivity of 264 W m-1 K-1, and the heat conduction adjusting layer 700 is made of copper (paragraph 0053), which has a thermal conductivity of 413 W m-1 K-1 (See Thermal conductivity of Metal and Alloys. Datasheet [online]. Engineering Toolbox, May 2006 [retrieved on 09-04-2025]. Retrieved from the Internet: <URL: https://www.engineeringtoolbox.com/thermal-conductivity-metals-d_858.html>). Therefore, a heat conduction rate of the second adjusting part 700 will be greater than a heat conduction rate of the non-circuit interconnection region of the substrate 101.
Therefore, a person of ordinary skill in the art would have combined the teachings of Tain et al. and Kim et al., in order to have a heat conduction rate of the second adjusting part to be greater than a heat conduction rate of the non-circuit interconnection region of the substrate. Doing so would enable an efficient packaging of semiconductor chips within a smaller footprint together with an efficient cooling system, as recognized by Kim et al. (paragraph 0004).
Note that Claim 4 is examined based on the interpretation provided under the 112(b) rejection above.
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Regarding Claim 7, Tain et al. teaches the semiconductor structure of claim 1, wherein the heat conduction adjusting layer 106 comprises a third adjusting part and a fourth adjusting part, the third adjusting part is located at least on a surface of the circuit interconnection region 118 of the substrate 102 in the chip unit farthest away from the base 133, the fourth adjusting part is located at least on a surface of the circuit interconnection region 118 of the substrate 102 in the chip unit closest to the base 133 (see annotated Fig. 5 above).
Tain et al. fails to teach a heat conduction rate of the third adjusting part is lower than a heat conduction rate of the circuit interconnection region of the substrate in the chip unit farthest away from the base, and a heat conduction rate of the fourth adjusting part is greater than a heat conduction rate of the circuit interconnection region of the substrate in the chip unit closest to the base.
However, Wang discloses a semiconductor structure, wherein a heat conduction rate of the heat conduction adjusting layer 4 is lower than a heat conduction rate of the circuit interconnection region of the substrate 1 (See rejection of Claim 2, Fig. 1: 1, 4, page 6, lines 19-31, page 3, line 23-26, page 5, lines 13-23 in English Translation of Wang).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of both Tain et al. and Wang in order to have the heat conduction rate of the third adjusting part of Tian et al. to be lower than the heat conduction rate of the circuit interconnection region of the substrate in the chip unit farthest away from the base of Tain et al. Doing so would effectively dissipate the heat generated by the chipset, as recognized by Wang (page 2, lines 16-20).
Furthermore, Kim et al. discloses a semiconductor structure, comprising a heat conduction adjusting layer 700 with a fourth adjusting part disposed in the circuit interconnection region of the substrate 101 (see annotated Fig. 1A:700, 101, paragraph 0029, 0031, 0051-0053). Further, Kim et al. teaches the substrate 101 is made of silicon (paragraph 0031), which has a thermal conductivity of 264 W m-1 K-1, and the heat conduction adjusting layer 700 is made of copper (paragraph 0053), which has a thermal conductivity of 413 W m-1 K-1 (See Thermal conductivity of Metal and Alloys. Datasheet [online]. Engineering Toolbox, May 2006 [retrieved on 09-04-2025]. Retrieved from the Internet: <URL: https://www.engineeringtoolbox.com/thermal-conductivity-metals-d_858.html>). Therefore, a heat conduction rate of the second adjusting part 700 will be greater than a heat conduction rate of the non-circuit interconnection region of the substrate 101.
Therefore, a person of ordinary skill in the art would have combined the teachings of Tain et al., and Kim et al. in order to have a heat conduction rate of the fourth adjusting part of Tain et al. to be greater than a heat conduction rate of the circuit interconnection region of the substrate in the chip unit closest to the base of Tain et al. Doing so would enable an efficient packaging of semiconductor chips within a smaller footprint together with an efficient cooling system, as recognized by Kim et al. (paragraph 0004).
Note that Claim 7 is examined based on the interpretation provided under the 112(b) rejection above.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Tain et al. (US 20090294947 A1), in view of Hsu (US 20060163722 A1), further in view of Wang (CN 110943001 A), as applied to Claim 2 above, further in view of Lee et al. (US 20220223494 A1).
The combination of Tain et al. and Wang fails to teach the semiconductor structure of claim 2, further comprising: an adhesive layer located between two adjacent ones of the chip units and filling up a gap between the two adjacent chip units, wherein the heat conduction rate of the heat conduction adjusting layer is lower than a heat conduction rate of the adhesive layer.
However, Lee et al. teaches a semiconductor structure comprising an adhesive layer 339 located between two adjacent ones of the chip units 261 and filling up a gap between the two adjacent chip units 261 (Fig. 5D: 339, 261, paragraph 0144).
Therefore, a person of ordinary skill in the art would have combined the teachings of Tain et al., Wang and Lee et al. in order to have an adhesive layer located between two adjacent ones of the chip units and filling up a gap between the two adjacent chip units. Doing so would ensure strong adhesion between the stacked chip units.
Lee et al. further teaches the adhesive layer 339 includes silver paste (paragraph 0144), which has a thermal conductivity of around 9.1 W m-1 K-1 (see Technical Notes, PELCO® High Performance Silver Paste. Datasheet [online]. Ted Pella, Inc., January 2022 [retrieved on 09-04-2025]. Retrieved from the Internet: <URL: https://www.tedpella.com/SEMmisc_html/SEMpaint.aspx#16047>). Furthermore, the heat conduction adjusting layer 4 of Wang is a thermal resistance layer formed of Polymethylmethacrylate (PMMA) (see page 5, lines 13-23), therefore has a lower heat conduction rate facilitated by a lower thermal conductivity of [Symbol font/0x7E]0.17 W m-1 K-1 (see Properties of PMMA. Datasheet [online]. PolyPlasty.cz, August 2020 [retrieved on 09-03-2025]. Retrieved from the Internet: <URL: https://www.polyplasty.cz/polymethylmethakrylat.html>). Therefore, a person or ordinary skill in the art would have recognized that when the adhesive layer of Lee et al. is disposed in the semiconductor structure of Tain et al./Wang, the heat conduction rate of the heat conduction adjusting layer will be lower than a heat conduction rate of the adhesive layer.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tain et al. (US 20090294947 A1), in view of Hsu (US 20060163722 A1), further in view of Wang (CN 110943001 A), as applied to Claim 5 above, further in view of Lee et al. (US 20220223494 A1).
The combination of Tain et al. and Wang fails to teach the semiconductor structure of claim 2, further comprising: an adhesive layer located between two adjacent ones of the chip units and filling up a gap between the two adjacent chip units, wherein the heat conduction rate of the heat conduction adjusting layer is lower than a heat conduction rate of the adhesive layer.
However, Lee et al. teaches a semiconductor structure comprising an adhesive layer 339 located between two adjacent ones of the chip units 261 and filling up a gap between the two adjacent chip units 261 (Fig. 5D: 339, 261, paragraph 0144).
Therefore, a person of ordinary skill in the art would have combined the teachings of Tain et al., Wang and Lee et al. in order to have an adhesive layer located between two adjacent ones of the chip units and filling up a gap between the two adjacent chip units. Doing so would ensure strong adhesion between the stacked chip units.
Lee et al. further teaches the adhesive layer 339 includes silver paste (paragraph 0144), which has a thermal conductivity of around 9.1 W m-1 K-1 (see Technical Notes, PELCO® High Performance Silver Paste. Datasheet [online]. Ted Pella, Inc., January 2022 [retrieved on 09-04-2025]. Retrieved from the Internet: <URL: https://www.tedpella.com/SEMmisc_html/SEMpaint.aspx#16047>). Furthermore, the heat conduction adjusting layer 4 of Wang is a thermal resistance layer formed of Polymethylmethacrylate (PMMA) (see page 5, lines 13-23), therefore has a lower heat conduction rate facilitated by a lower thermal conductivity of [Symbol font/0x7E]0.17 W m-1 K-1 (see Properties of PMMA. Datasheet [online]. PolyPlasty.cz, August 2020 [retrieved on 09-03-2025]. Retrieved from the Internet: <URL: https://www.polyplasty.cz/polymethylmethakrylat.html>). Therefore, a person or ordinary skill in the art would have recognized that when the adhesive layer of Lee et al. is disposed in the semiconductor structure of Tain et al./Wang, the heat conduction rate of the heat conduction adjusting layer will be lower than a heat conduction rate of the adhesive layer.
Claims 15-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tain et al. (US 20090294947 A1), in view of Wirtz et al. (US 20210066246 A1) and Hsu (US 20060163722 A1).
Regarding Claim 15, Tain et al. discloses a forming method of a semiconductor structure, comprising:
providing a base 133 (Fig. 5: 133, paragraph 0048);
forming a chipset at one side of the base 133 (annotated Fig. 5: chipset, 500, 133, paragraph 0048),
wherein the chipset comprises multiple chip units 500 arranged at intervals along a direction perpendicular to the base 133 (annotated Fig. 5: chipset, 500, 133, paragraph 0048),
each of the chip units 500 comprises a substrate 102 and a circuit module 114 disposed on a surface of the substrate 102 (annotated Fig. 5: 500, 102, 114, paragraph 0021),
Note that while Fig. 5 shows the circuit module 114 as an interconnect located in the substrate 102, paragraph 0021 mentions that circuit module 114 can be located on the surface of the substrate 102.
the substrate 102 comprises a circuit interconnection region 118 and a non-circuit interconnection region distributed adjacently (annotated Fig. 5: 102, 118, non-circuit interconnection region, paragraph 0021),
the circuit module 114 is disposed on a surface of the circuit interconnection region 118 (annotated Fig. 5: 114, 118, paragraph 0021),
Since the circuit module 114 can be located on the surface of the substrate 102 according to paragraph 0021, the circuit module 114 will be disposed on a surface of the circuit interconnection region 118.
and two adjacent ones of the chip units 500 are electrically connected through the circuit module 114 (see annotated Fig. 5: 500, 114, paragraph 0021);
forming a heat conduction adjusting layer 106 at one side of at least one of the substrates 102 (annotated Fig. 5: 106, 102, paragraph 0023, 0048),
wherein the heat conduction adjusting layer 106 is in contact with the at least one of the substrates 102 for reducing difference of heat conduction rates between surfaces of the substrates 102 (annotated Fig. 5: 106, 102, paragraph 0023, 0048);
and connecting the chipset comprising the heat conduction adjusting layer fixedly with the base by a thermal compression bond process;
wherein the heat conduction adjusting layer 106 is located on one side of the substrate 102 away from the base 133 and is arranged side-by-side with the circuit module 114 located on the surface of the substrate 102 (Fig. 5: 133, 106, 102, 114, paragraph 0030);
Note that while Fig. 5 shows the circuit module 114 embedded into the substrate 102, paragraph 0021 states that the circuit module 114 can be disposed on a surface of the substrate 102. Therefore, a person of ordinary skill in the art would have recognized that when the circuit module 114 is disposed on the surface of the substrate 102, the heat conduction adjusting layer 106 will be arranged side-by-side with the circuit module 114 located on the surface of the substrate 102.
wherein the base 133 comprises an external circuit 136 (Fig. 5: 136, paragraph 0030),
the semiconductor structure further comprises a conductive structure located between the chipset and the base, one end of the conductive structure is electrically connected with any one of the chip units, and another end is connected with the external circuit of the base:
wherein the conductive structure comprises a connection pad and a conductive bump, the connection pad is provided on a surface, close to the base, of the substrate of the chip unit closest to the base in the chipset, the conductive bump is located between the connection pad and the external circuit of the base, both ends of the conductive bump are in contact with the connection pad and the external circuit, respectively.
Wirz et al. teaches a forming method of a semiconductor structure, comprising the following limitation not disclosed in Tain et al.:
and connecting the chipset 300 fixedly with the base 100 by a thermal compression bond process (see Fig. 1F: 300, 100, paragraph 0038).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of both Tain et al. and Wirz et al. in order to connect the chipset of Tain et al. comprising the heat conduction adjusting layer fixedly with the base by a thermal compression bond process. Doing so would enable the bonding of multiple, stacked semiconductor die. in 3D semiconductor assemblies of semiconductor die using smaller conductive elements at reduced pitches, as recognized by Wirz et al. (paragraph 0003).
Hsu teaches a semiconductor structure comprising the following limitations not disclosed in Tain et al.
the semiconductor structure further comprises a conductive structure 200, 20a located between the chipset 20 and the base 26, one end of the conductive structure 200, 20a is electrically connected with any one of the chip units 20, and another end is connected with the external circuit 250 of the base 26 (Fig. 3C: 200, 20a, 250, 26, paragraph 0024, 0030, 0033),
wherein the conductive structure 200, 20a comprises a connection pad 200 and a conductive bump 20a, the connection pad 200 is provided on a surface, close to the base of the substrate of the chip unit closest to the base 26 in the chipset 20, the conductive bump 20a is located between the connection pad 200 and the external circuit of the base 250, both ends of the conductive bump 20a are in contact with the connection pad 200 and the external circuit 250, respectively (Fig. 3C: 200, 20a, 250, 26, paragraph 0024, 0030, 0033).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Tain et al. and Hsu in order to come up with the claimed invention as recited in Claim 1. By doing so, the conductive structure would create a direct electrical connection between the chip set and the external circuit of the base.
Regarding Claim 16, Tain et al. discloses the forming method of claim 15, wherein forming a heat conduction adjusting layer 114 at one side of at least one of the substrates 102 comprises:
forming a concave part 132 depressed inwards in the direction perpendicular to the substrate 102 in a surface of the substrate 102 facing away from the base 133 (Fig 5: 132, 102, 133, Fig. 4A: 132, 102, paragraph 0038);
and forming the heat conduction adjusting layer 106 at least in the concave part 132 (Fig. 4C: 106, 132, paragraph 0040).
Regarding Claim 17, Tain et al. discloses the forming method of claim 15, wherein forming a heat conduction adjusting layer 106 at one side of at least one of the substrates 102 comprises: forming
the heat conduction adjusting layer 106 on a surface of the substrate 102 facing away from the base 133 (see annotated Fig. 5: 106, 102, 132).
Regarding Claim 19, while Tain et al. fails to explicitly teach a memory comprising the semiconductor structure of claim 1, it does teach that the semiconductor structure of claim 1 is relevant for integrated circuits (paragraph 0005). Furthermore, Wirz et al. teaches a memory comprising a semiconductor structure (paragraph 0003).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of both Tain et al. and Wirz et al. in order to have a memory comprising the semiconductor structure of claim 1.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Tain et al. (US 20090294947 A1), in view of Wirtz et al. (US 20210066246 A1) and Hsu (US 20060163722 A1), as applied to Claim 15 above, further in view of Ku (US 20160056128 A1).
Tain et al. fails to disclose the forming method of claim 15, wherein forming a heat conduction adjusting layer at one side of the substrate comprises: forming the heat conduction adjusting layer at one side of the substrate before forming the circuit module.
However, Ku discloses a forming method of a semiconductor structure, wherein forming a heat conduction adjusting layer 30 at one side of the substrate 10 comprises: forming the heat conduction adjusting layer at 30 one side of the substrate before forming the circuit module 32 (Fig. 1: 10, 30, 32, paragraph 0015).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of both Tain et al. and Ku in order to form the heat conduction adjusting layer at one side of the substrate before forming the circuit module. Doing so would enable effective thermal management from early on by ensuring the heat conduction adjusting layer is in place before the heat-generating components such as the circuit module is formed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 06/05/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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