Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/22/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 23, 25-26 and 27 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by Yang (Pub. No.: US 2016/0005648).
Re claim 23, Yang, FIG. 1 [as shown below] teaches a semiconductor die comprising:
a die body (130/132) comprising a semiconductor substrate (130), a device region (T+131) over the semiconductor substrate; and
a semiconductor device (T) having an active region [A], wherein the active region is formed in the device region;
a first metal interconnect [FMI] over on a frontside surface of the device region (T+131); and
a carbon allotrope layer (115/117/113/119) that covers at least a portion of the frontside surface such that the carbon allotrope layer covers the semiconductor device (T+131) and the first metal interconnect [FMI].
Re claim 25, Yang, FIG. 1 [as shown below] teaches the semiconductor die of claim 23 wherein the carbon allotrope layer comprises graphene layers (115).
Re claim 26, Yang, FIG. 1 [as shown below] teaches the semiconductor die of claim 23 wherein the carbon allotrope layer comprises layers, films, flakes, fibers or sheets of a carbon allotrope (115).
Re claim 27, Yang, FIG. 1 [as shown below] teaches the semiconductor die claim 26 wherein the carbon allotrope comprises graphene, graphite, single-walled or multi-walled carbon nanotubes, or their combination (115).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 14-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOTANI (Pub No.: US 2018/0068923) in view of Nakano (Pub. No.: US 2020/0211996).
Re claim 1, KOTANI, FIG. 10B teaches a semiconductor die comprising:
a die body comprising a semiconductor substrate (10), a semiconductor device region (11/21/22) over the semiconductor substrate, and at least one via (50) within the semiconductor substrate and the semiconductor device region of the die body, wherein the at least one via comprises at least one semiconductor wall structure (52, [0044]) defining an interior cavity and wherein the semiconductor device region has an active region (22) of a transistor (31/21/33); and
a carbon allotrope structure (53, [0045]) filling at least a portion of the interior cavity, wherein the carbon allotrope structure extends above and below an interface between the semiconductor substrate (10) and the semiconductor device region (11/21/22).
KOTANI fails to teach wherein the at least one via comprises at least one conductive wall structure defining an interior cavity.
Nakano teaches wherein the at least one via comprises at least one conductive wall structure (504, FIG. 15, [0073]) defining an interior cavity.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of utilizing the conductive adhesives for mechanical and electrical connection between semiconductor device components as taught by Nakano, [0001].
Re claim 2, in the combination, KOTANI, FIG. 10B teaches the semiconductor die of claim 1 wherein the carbon allotrope structure comprises a first carbon allotrope dispersed in one of a foam, an aerogel, a polymer, or a silicon-based membrane (53, [0044]).
Re claim 3, in the combination, KOTANI, FIG. 10B teaches the semiconductor die of claim 2 wherein the at least one conductive wall structure (52) comprises a top side adjacent a frontside surface of the semiconductor device region (11/21/22).
Re claim 14, in the combination, KOTANI, FIG. 10B teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 90% of the interior cavity (53).
Re claim 15, in the combination, KOTANI, FIG. 10B teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 75% of the interior cavity (53).
Re claim 16, in the combination, KOTANI, FIG. 10B teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 50% of the interior cavity (53).
Re claim 17, in the combination, KOTANI, FIG. 10B teaches the semiconductor die of claim 1 wherein at least 20% of the volume percentage of the carbon allotrope structure filling the interior cavity (53) extends above the interface formed between the semiconductor substrate (10) and the semiconductor device region.
Re claim 18, in the combination, KOTANI, FIG. 10B teaches the semiconductor die of claim 1 wherein the semiconductor substrate comprises silicon carbide (SiC) (10).
Re claim 19, in the combination, KOTANI, FIG. 10B teaches the semiconductor die of claim 1 wherein the semiconductor device region comprises gallium nitride (GaN) (11/21/22, [0043]).
Re claim 20, in the combination, KOTANI, FIG. 10B teaches the semiconductor die of claim 1 wherein the semiconductor substrate (10) comprises silicon carbide (SiC) and the semiconductor device region comprises gallium nitride (GaN) (11/21/22).
Re claim 21, in the combination, KOTANI, FIG. 10B teaches the semiconductor die of claim 1 wherein the semiconductor device region (11/21/22, [0043]) comprises one or more layers of gallium nitride (GaN), aluminum gallium nitride (AlGaN), and aluminum nitride (AIN), and wherein the semiconductor substrate comprises one of sapphire, silicon carbide (SiC), gallium arsenide (GaAs), or silicon (Si).
Claim(s) 23 and 25-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOTANI (Pub No.: US 2018/0068923) in view of Yang.
Re claim 23, KOTANI, FIG. 10B teaches a semiconductor die comprising:
a die body comprising a semiconductor substrate, a semiconductor device region (11/21/22) over the semiconductor substrate; and
a semiconductor device having an active region (22), wherein the active region is formed in the device region;
a first metal interconnect (31/32/33) on a frontside surface of the semiconductor device region.
KOTANI fails to teach a carbon allotrope layer that is on and covers at least a portion of the frontside surface such that the carbon allotrope layer covers the semiconductor device and the first metal interconnect.
Yang, FIG. 1 [as shown below] teaches a carbon allotrope layer (115/117/113/119) that covers at least a portion of the frontside surface such that the carbon allotrope layer covers the semiconductor device (T+131) and the first metal interconnect [FMI].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of catalytically growing a graphene layer on an exposed surface of the metal line as taught by Yang, Abstract.
Re claim 25, in the combination, Yang, FIG. 1 [as shown below] teaches the semiconductor die of claim 23 wherein the carbon allotrope layer comprises graphene layers (115).
Re claim 26, in the combination, Yang, FIG. 1 [as shown below] teaches the semiconductor die of claim 23 wherein the carbon allotrope layer comprises layers, films, flakes, fibers or sheets of a carbon allotrope (115).
Re claim 27, in the combination, Yang, FIG. 1 [as shown below] teaches the semiconductor die claim 26 wherein the carbon allotrope comprises graphene, graphite, single-walled or multi-walled carbon nanotubes, or their combination (115).
Re claim 28, KOTANI, FIG. 10B teaches the semiconductor die of claim 26 wherein the carbon allotrope (53) is functionalized with an oxide, reduced oxide, fluoride, chloride, bromide, iodide, metals, metal oxides, metalloid oxides, or mixtures thereof (out of barrier layer 22 of device layers (11/21/22)).
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI (Pub. No.: US 2023/0399455) Nakano.
Re claim 1, LI, FIGS. 15 and 17-18 teaches a semiconductor die comprising:
a die body comprising a semiconductor substrate (1, ¶ [0082]), a semiconductor device region (2/3/4/5, [0081]) over the semiconductor substrate, and at least one via (8/7) within the semiconductor substrate and the semiconductor device region of the die body, wherein the at least one via comprises at least one conductive wall structure (6) defining an interior cavity and wherein the semiconductor device region has an active region of a transistor (3/4/5); and
a carbon allotrope structure (“a diamond film or graphene” of 8+6, [0153]) filling at least a portion of the interior cavity, wherein the carbon allotrope structure extends above and below an interface between the semiconductor substrate (1) and the semiconductor device region (2/3/4/5).
LI fails to teach a carbon allotrope structure filling at least a portion of the interior cavity.
Nakano teaches a carbon allotrope structure filling at least a portion of the interior cavity (504, FIG. 15, [0073]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of utilizing the conductive adhesives for mechanical and electrical connection between semiconductor device components as taught by Nakano, [0001].
Re claim 2, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the carbon allotrope structure comprises a first carbon allotrope dispersed in one of a foam, an aerogel, a polymer, or a silicon-based membrane (“a diamond film or graphene” of 8+6).
Re claim 3, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 2 wherein the at least one conductive wall structure (7/6) comprises a top side adjacent a frontside surface of the semiconductor device region (2/3/4/5).
Re claim 4, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 3 further comprising a first conductive layer (6) over a backside surface of the semiconductor substrate (1) and forming at least a portion of the at least one conductive wall structure of the at least one via (7).
Re claim 5, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 4 wherein the first conductive layer comprises gold (Au) [0116].
Re claim 6, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 5 further comprising a first metal interconnect over the frontside surface (41 of FIG. 19) of the semiconductor device region (2/3/4/5) and in electrical contact with the top side of the at least one conductive wall.
Claim(s) 7-12-16 and 18-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI/Nakano and further in view of Yang.
Re claim 7, LI/Nakano teach all the limitation of claim 6.
LI fails to teach a carbon allotrope layer that covers at least a portion of the frontside surface such that the carbon allotrope layer covers the semiconductor device and the first metal interconnect.
Yang, FIG. 1 teaches a carbon allotrope layer (115/117/113/119) that covers at least a portion of the frontside surface such that the carbon allotrope layer covers the semiconductor device (T) and the first metal interconnect [FMI].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of catalytically growing the graphene layer as taught by Yang, Abstract.
Re claim 8, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die claim 7 wherein the thickness of the carbon allotrope layer is in the range of 5 µm to 500 µm ([0143], note that the thickness of 8 is about the same as the thickness of substrate 1).
Re claim 9, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 7 wherein the carbon allotrope layer comprises graphene layers (“a diamond film or graphene” of 8).
Re claim 10, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 7 wherein the carbon allotrope layer comprises layers, films, flakes, fibers or sheets of a second carbon allotrope (“a diamond film or graphene” of 8).
Re claim 11, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die claim 10 wherein each of the first carbon allotrope and the second carbon allotrope comprises graphene, graphite, single-walled or multi-walled carbon nanotubes, or their combination (“a diamond film or graphene” of 8).
Re claim 12, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 10 wherein each of the first carbon allotrope and the second carbon allotrope (8) is functionalized with an oxide, reduced oxide, fluoride, chloride, bromide, iodide, metals (6), metal oxides, metalloid oxides, or mixtures thereof.
Re claim 13, in the combination, LI, FIGS. 15 and 17-18 teaches he apparatus of claim 1 wherein the carbon allotrope structure comprises a graphene foam [0113].
Re claim 14, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 90% of the interior cavity (almost filled up with 100% of the cavity).
Re claim 15, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 75% of the interior cavity (almost filled up with 100% of the cavity).
Re claim 16, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 50% of the interior cavity (almost filled up with 100% of the cavity).
Re claim 18, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the semiconductor substrate comprises silicon carbide (SiC) (1, [0082]).
Re claim 19, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the semiconductor device region comprises gallium nitride (GaN) (201 of 2, FIG. 5, [0085]).
Re claim 20, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the semiconductor substrate comprises silicon carbide (SiC) and the semiconductor device region comprises gallium nitride (GaN) (201 of 2, FIG. 5, [0085]).
Re claim 21, in the combination, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the semiconductor device region comprises one or more layers of gallium nitride (GaN) (201 of 2, FIG. 5, [0085]), aluminum gallium nitride (AlGaN), and aluminum nitride (AlN), and wherein the semiconductor substrate comprises one of sapphire, silicon carbide (SiC), gallium arsenide (GaAs), or silicon (Si) (1, [0082]).
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of KOTANI.
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Re claim 1, Yang, FIG. 1 [as shown above] teaches a semiconductor die comprising:
a die body [DB] comprising a semiconductor substrate (130), a device region [DR] over the substrate, and at least one via (113/117/115/103, note that the metal layer 101 may be any of the metal layers 141 to 149 shown in FIG. 1) within the semiconductor substrate (130) and the device region of the die body [DR], wherein the at least one via comprises at least one conductive wall structure (inner wall of 113, ¶ [0032]) defining an interior cavity; and
a carbon allotrope structure (115/117/113/119, note that “The bottom part 115 of the barrier layer may be made of the graphene material which has superior conductivity”, [0036], and graphene is an allotrope of carbon) filling at least a portion of the interior cavity, wherein the carbon allotrope structure (115/117/113/119) extends above and below an interface between the semiconductor substrate (130) and the device region [DR].
Yang fails to teach wherein the carbon allotrope structure extends below an interface between the semiconductor substrate and the semiconductor device region.
KOTANI, FIG. 10B teaches a semiconductor device region (11/21/22) and wherein the semiconductor device region has an active region (22) of a transistor; wherein the carbon allotrope structure extends below an interface between the semiconductor substrate (10) and the semiconductor device region (11/21/22).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving the heat dissipation layer is formed of a material containing carbon, as taught by KOTANI, [0011].
Re claim 2, in the combination, Yang, FIG. 2h teaches the semiconductor die of claim 1 wherein the carbon allotrope structure comprises a first carbon allotrope (115) dispersed in one of a foam, an aerogel, a polymer, or a silicon-based membrane (107, [0029]).
Re claim 3, in the combination, Yang, FIG. 2h teaches the semiconductor die of claim 2 wherein the at least one conductive wall structure (113) comprises a top side adjacent a frontside surface of the semiconductor device region [DR].
Re claim 4, in the combination, Yang, FIG. 2h teaches the semiconductor die of claim 3 further comprising a first conductive layer over (103) a backside surface of the semiconductor substrate and forming at least a portion of the at least one conductive wall structure of the at least one via (113/117/115/103).
Re claim 5, in the combination, Yang, FIG. 2h teaches the semiconductor die of claim 4 wherein the first conductive layer comprises gold (Au) (103, [0027]).
Re claim 6, in the combination, Yang, FIG. 2h teaches the semiconductor die of claim 5 further comprising a first metal interconnect (128) over the frontside surface of the semiconductor device region and in electrical contact with the top side of the at least one conductive wall (113).
Re claim 7, in the combination, Yang, FIG. 1 [as shown above] and 2h teaches the semiconductor die of claim 6 further comprising:
a carbon allotrope layer (115) that covers at least a portion of the frontside surface of the semiconductor device region such that the carbon allotrope layer (115, note that the metal layer 101 may be any of the metal layers 141 to 149 shown in FIG. 1) covers the transistor (T) and the first metal interconnect [FMI].
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Yang.
Re claim 23, LI, FIGS. 15 and 17-18 teaches a semiconductor die comprising:
a die body comprising a semiconductor substrate (1), a semiconductor device region (2/3/4/5) over the semiconductor substrate; and
a semiconductor device having an active region (form underneath gate 4 between 3 and 5, FIG. 5), wherein the active region is formed in the device region;
a first metal interconnect (41, FIG. 19) over on a frontside surface of the semiconductor device region; and
a carbon allotrope layer (“a diamond film or graphene” of 8+6).
Li fails to teach a carbon allotrope layer that covers at least a portion of the frontside surface such that the carbon allotrope layer covers the semiconductor device and the first metal interconnect.
Yang, FIG. 1 teaches a carbon allotrope layer (115/117/113/119) that covers at least a portion of the frontside surface such that the carbon allotrope layer covers the semiconductor device (T) and the first metal interconnect [FMI].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of catalytically growing the graphene layer as taught by Yang, Abstract.
Claim(s) 8 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang.
Yang differs from the claim invention by not disclosing wherein the thickness of the carbon allotrope layer is in the range of 5 µm to 500 µm.
However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOTANI/Nakano in view of Kane (Patent No.: US 1322702).
KOTANI/Nakano teaches all the limitation of claim 1.
KOTANI/Nakano fails to teach the limitation of claim 22.
Kane teaches wherein the semiconductor die is a monolithic microwave integrated circuit (MMIC) (OTHER PUBLICATIONS, Bessemoulin, et al.; “0.1-μm GaAs PHEMT W-Band Low Noise Amplifier MMIC using Coplanar Waveguide Technology”; Page 2).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching in desirable for a manufacturing process flow to be scalable for mass production as taught by Kane, BACKGROUND.
Response to Arguments
Applicant's arguments with respect to claims 1 and 23 on the remarks filed on 04/22/2026 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
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/TONY TRAN/Primary Examiner, Art Unit 2893
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