Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-12, 14-16 and 18-21 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LI (Pub. No.: US 2023/0399455).
Re claim 1, LI, FIGS. 15 and 17-18 teaches a semiconductor die comprising:
a die body comprising a semiconductor substrate (1, ¶ [0082]), a semiconductor device region (2/3/4/5, [0081]) over the semiconductor substrate, and at least one via (8/7) within the semiconductor substrate and the semiconductor device region of the die body, wherein the at least one via comprises at least one conductive wall structure (6) defining an interior cavity and wherein the semiconductor device region has an active region of a transistor (3/4/5); and
a carbon allotrope structure (“a diamond film or graphene” of 8+6, [0153]) filling at least a portion of the interior cavity, wherein the carbon allotrope structure extends above and below an interface between the semiconductor substrate (1) and the semiconductor device region (2/3/4/5).
Re claim 2, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the carbon allotrope structure comprises a first carbon allotrope dispersed in one of a foam, an aerogel, a polymer, or a silicon-based membrane (“a diamond film or graphene” of 8+6).
Re claim 3, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 2 wherein the at least one conductive wall structure (7/6) comprises a top side adjacent a frontside surface of the semiconductor device region (2/3/4/5).
Re claim 4, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 3 further comprising a first conductive layer (6) over a backside surface of the semiconductor substrate (1) and forming at least a portion of the at least one conductive wall structure of the at least one via (7).
Re claim 5, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 4 wherein the first conductive layer comprises gold (Au) [0116].
Re claim 6, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 5 further comprising a first metal interconnect over the frontside surface (41 of FIG. 19) of the semiconductor device region (2/3/4/5) and in electrical contact with the top side of the at least one conductive wall.
Re claim 8, LI, FIGS. 15 and 17-18 teaches the semiconductor die claim 7 wherein the thickness of the carbon allotrope layer is in the range of 5 µm to 500 µm ([0143], note that the thickness of 8 is about the same as the thickness of substrate 1).
Re claim 9, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 7 wherein the carbon allotrope layer comprises graphene layers (“a diamond film or graphene” of 8).
Re claim 10, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 7 wherein the carbon allotrope layer comprises layers, films, flakes, fibers or sheets of a second carbon allotrope (“a diamond film or graphene” of 8).
Re claim 11, LI, FIGS. 15 and 17-18 teaches the semiconductor die claim 10 wherein each of the first carbon allotrope and the second carbon allotrope comprises graphene, graphite, single-walled or multi-walled carbon nanotubes, or their combination (“a diamond film or graphene” of 8).
Re claim 12, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 10 wherein each of the first carbon allotrope and the second carbon allotrope (8) is functionalized with an oxide, reduced oxide, fluoride, chloride, bromide, iodide, metals (6), metal oxides, metalloid oxides, or mixtures thereof.
Re claim 14, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 90% of the interior cavity (almost filled up with 100% of the cavity).
Re claim 15, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 75% of the interior cavity (almost filled up with 100% of the cavity).
Re claim 16, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 50% of the interior cavity (almost filled up with 100% of the cavity).
Re claim 18, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the semiconductor substrate comprises silicon carbide (SiC) (1, [0082]).
Re claim 19, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the semiconductor device region comprises gallium nitride (GaN) (201 of 2, FIG. 5, [0085]).
Re claim 20, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the semiconductor substrate comprises silicon carbide (SiC) and the semiconductor device region comprises gallium nitride (GaN) (201 of 2, FIG. 5, [0085]).
Re claim 21, LI, FIGS. 15 and 17-18 teaches the semiconductor die of claim 1 wherein the semiconductor device region comprises one or more layers of gallium nitride (GaN) (201 of 2, FIG. 5, [0085]), aluminum gallium nitride (AlGaN), and aluminum nitride (AlN), and wherein the semiconductor substrate comprises one of sapphire, silicon carbide (SiC), gallium arsenide (GaAs), or silicon (Si) (1, [0082]).
Claim(s) 23, 25-26 and 27 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by Yang (Pub. No.: US 2016/0005648).
Re claim 23, Yang, FIG. 1 [as shown below] teaches a semiconductor die comprising:
a die body (130/132) comprising a semiconductor substrate (130), a device region (T+131) over the semiconductor substrate; and
a semiconductor device (T) having an active region [A], wherein the active region is formed in the device region;
a first metal interconnect [FMI] over on a frontside surface of the device region (T+131); and
a carbon allotrope layer (115/117/113/119) that covers at least a portion of the frontside surface such that the carbon allotrope layer covers the semiconductor device (T+131) and the first metal interconnect [FMI].
Re claim 25, Yang, FIG. 1 [as shown below] teaches the semiconductor die of claim 23 wherein the carbon allotrope layer comprises graphene layers (115).
Re claim 26, Yang, FIG. 1 [as shown below] teaches the semiconductor die of claim 23 wherein the carbon allotrope layer comprises layers, films, flakes, fibers or sheets of a carbon allotrope (115).
Re claim 27, Yang, FIG. 1 [as shown below] teaches the semiconductor die claim 26 wherein the carbon allotrope comprises graphene, graphite, single-walled or multi-walled carbon nanotubes, or their combination (115).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of SUNG (Pub. No.: US 2020/0328189).
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Re claim 1, Yang, FIG. 1 [as shown above] teaches a semiconductor die comprising:
a die body [DB] comprising a semiconductor substrate (130), a device region [DR] over the substrate, and at least one via (113/117/115/103, note that the metal layer 101 may be any of the metal layers 141 to 149 shown in FIG. 1) within the semiconductor substrate (130) and the device region of the die body [DR], wherein the at least one via comprises at least one conductive wall structure (inner wall of 113, ¶ [0032]) defining an interior cavity; and
a carbon allotrope structure (115/117/113/119, note that “The bottom part 115 of the barrier layer may be made of the graphene material which has superior conductivity”, [0036], and graphene is an allotrope of carbon) filling at least a portion of the interior cavity, wherein the carbon allotrope structure (115/117/113/119) extends above and below an interface between the semiconductor substrate (130) and the device region [DR].
Yang fails to teach wherein the carbon allotrope structure extends below an interface between the semiconductor substrate and the semiconductor device region.
SUNG, FIG. 8 [flip it upside down] teaches a semiconductor device region (100, note that the semiconductor die 100 includes millions of transistors wherein the active region formed underneath of the gates of the transistors, [0028]) and wherein the semiconductor device region has an active region of a transistor; wherein the carbon allotrope structure extends below an interface between the semiconductor substrate (201/202) and the semiconductor device region (100).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving the removal of heat from SiPs as taught by SUNG, [0004].
Re claim 2, Yang, FIG. 2h teaches the semiconductor die of claim 1 wherein the carbon allotrope structure comprises a first carbon allotrope (115) dispersed in one of a foam, an aerogel, a polymer, or a silicon-based membrane (107, [0029]).
Re claim 3, Yang, FIG. 2h teaches the semiconductor die of claim 2 wherein the at least one conductive wall structure (113) comprises a top side adjacent a frontside surface of the semiconductor device region [DR].
Re claim 4, Yang, FIG. 2h teaches the semiconductor die of claim 3 further comprising a first conductive layer over (103) a backside surface of the semiconductor substrate and forming at least a portion of the at least one conductive wall structure of the at least one via (113/117/115/103).
Re claim 5, Yang, FIG. 2h teaches the semiconductor die of claim 4 wherein the first conductive layer comprises gold (Au) (103, [0027]).
Re claim 6, Yang, FIG. 2h teaches the semiconductor die of claim 5 further comprising a first metal interconnect (128) over the frontside surface of the semiconductor device region and in electrical contact with the top side of the at least one conductive wall (113).
Re claim 7, Yang, FIG. 1 [as shown above] and 2h teaches the semiconductor die of claim 6 further comprising:
a carbon allotrope layer (115) that covers at least a portion of the frontside surface of the semiconductor device region such that the carbon allotrope layer (115, note that the metal layer 101 may be any of the metal layers 141 to 149 shown in FIG. 1) covers the transistor (T) and the first metal interconnect [FMI].
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI in view of Yang.
Re claim 23, LI, FIGS. 15 and 17-18 teaches a semiconductor die comprising:
a die body comprising a semiconductor substrate (1), a semiconductor device region (2/3/4/5) over the semiconductor substrate; and
a semiconductor device having an active region (form underneath gate 4 between 3 and 5, FIG. 5), wherein the active region is formed in the device region;
a first metal interconnect (41, FIG. 19) over on a frontside surface of the semiconductor device region; and
a carbon allotrope layer (“a diamond film or graphene” of 8+6).
Li fails to teach a carbon allotrope layer that covers at least a portion of the frontside surface such that the carbon allotrope layer covers the semiconductor device and the first metal interconnect.
Yang, FIG. 1 teaches a carbon allotrope layer (115/117/113/119) that covers at least a portion of the frontside surface such that the carbon allotrope layer covers the semiconductor device (T) and the first metal interconnect [FMI].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of catalytically growing the graphene layer as taught by Yang, Abstract.
Claim(s) 1-7 and 9-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi (Pub. No.: US 2014/0140008) in view of SUNG.
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Re claim 1, Yamaguchi, FIG. 16D [flip it upside down] teaches a semiconductor die comprising:
a die body comprising a substrate (20), a semiconductor device region (54/16) over the substrate, and at least one via (14) within the semiconductor substrate and the semiconductor device region of the die body, and wherein the semiconductor device region has an active region of a transistor (note that chip 54 had millions of transistors in there, [0133]); and
a carbon allotrope structure (14) filling at least a portion of the interior cavity, wherein the carbon allotrope structure extends above and below an interface between the substrate (20) and the device region (54/16).
Yamaguchi fails to teach a semiconductor substrate; and wherein the at least one via comprises at least one conductive wall structure defining an interior cavity.
SUNG teaches a semiconductor substrate (201/202, FIG. 8 [as shown above]); and wherein the at least one via comprises at least one conductive wall structure (602, [0062]) defining an interior cavity.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing dissipating of heat as taught by SUNG, [0002].
Re claim 2, in the combination, Yamaguchi, FIG. 16D [flip it upside down] teaches the semiconductor die of claim 1 wherein the carbon allotrope structure comprises a first carbon allotrope (14) dispersed in one of a foam, an aerogel, a polymer, or a silicon-based membrane (16, [0150]).
Re claim 3, in the combination, SUNG, FIG. 8 [flip it upside down] teaches the semiconductor die of claim 2 wherein the at least one conductive wall structure (602) comprises a top side adjacent a frontside surface of the semiconductor device region (100).
Re claim 4, in the combination, Yamaguchi, FIG. 16D [flip it upside down] teaches the semiconductor die of claim 3 further comprising a first conductive layer over (12a) a backside surface of the semiconductor substrate and forming at least a portion of the at least one conductive wall structure (of 16 and 20 right next to 14) of the at least one via (14).
Re claim 5, in the combination, Yamaguchi, FIG. 16D [flip it upside down] teaches the semiconductor die of claim 4 wherein the first conductive layer comprises gold (Au) (12a of FIG. 4B, ¶¶ [0057]-[0059]).
Re claim 6, in the combination, Yamaguchi, FIG. 16D [flip it upside down] teaches the semiconductor die of claim 5 further comprising a first metal interconnect (52) over the frontside surface of the semiconductor device region and in electrical contact with the top side of the at least one conductive wall (of 16 and 20 right next to 14).
Re claim 7, in the combination, Yamaguchi, FIG. 16D [flip it upside down] teaches the semiconductor die of claim 6 further comprising:
a carbon allotrope layer (14/16/56/58/50) that covers at least a portion of the frontside surface of the semiconductor device region (54+16) such that the carbon allotrope layer covers the transistor semiconductor device (54, note that there are millions of transistor in the CPU of the chip) and the first metal interconnect (52).
Re claim 9, in the combination, Yamaguchi, FIG. 16D [flip it upside down] teaches the semiconductor die of claim 7 wherein the carbon allotrope layer comprises graphene layers (graphene 14 of 14/16/56/58/50).
Re claim 10, in the combination, Yamaguchi, FIG. 16D [flip it upside down] teaches the semiconductor die of claim 7 wherein the carbon allotrope layer comprises layers, films, flakes, fibers or sheets of a second carbon allotrope (14).
Re claim 11, in the combination, Yamaguchi, FIG. 16D [flip it upside down] teaches the semiconductor die claim 10 wherein each of the first carbon allotrope and the second carbon allotrope comprises graphene, graphite, single-walled or multi-walled carbon nanotubes (14), or their combination.
Re claim 12, in the combination, Yamaguchi, FIG. 16D [flip it upside down] teaches the semiconductor die of claim 10 wherein each of the first carbon allotrope and the second carbon allotrope is functionalized with an oxide, reduced oxide, fluoride, chloride, bromide, iodide, metals, metal oxides, metalloid oxides, or mixtures thereof (28, [0106]).
Re claim 13, in the combination, Yamaguchi teaches the apparatus of claim 1 wherein the carbon allotrope structure comprises a graphene foam (20, [0050]).
Re claim 14, in the combination, Yamaguchi teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 90% of the interior cavity (cavities form between 14 of FIG. 9A).
Re claim 15, in the combination, Yamaguchi teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 75% of the interior cavity (cavities form between 14 of FIG. 9A).
Re claim 16, in the combination, Yamaguchi teaches the semiconductor die of claim 1 wherein the carbon allotrope structure fills at least 50% of the interior cavity (cavities form between 14 of FIG. 9A).
Re claim 17, Y in the combination, Yamaguchi teaches the semiconductor die of claim 1 wherein at least 20% of the volume percentage of the carbon allotrope structure filling the interior cavity extends above the interface formed between the semiconductor substrate and the semiconductor device region (said the interface for this claim starting from bottom of 16 go up).
Re claim 18, in the combination, Yamaguchi teaches the semiconductor die of claim 1 wherein the semiconductor substrate comprises silicon carbide (SiC) (101/105, [0028]).
Claim(s) 23 and 25-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi in view of Yang.
Re claim 23, Yamaguchi, FIG. 16D teaches a semiconductor die comprising:
a die body comprising a substrate (20), a semiconductor device region (54+16) over the substrate; and
a semiconductor device (54) formed in the device region;
a first metal interconnect (52) over a frontside surface of the device region; and
a carbon allotrope layer (14/16/56/58/50) that covers at least a portion of the frontside surface such that the carbon allotrope layer covers the semiconductor device (54) and the first metal interconnect (52).
Li fails to teach a semiconductor substrate.
Yang, FIG. 1 teaches a semiconductor substrate (130, FIG. 1).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of catalytically growing the graphene layer as taught by Yang, Abstract.
Re claim 25, Yamaguchi, FIG. 16D teaches the semiconductor die of claim 23 wherein the carbon allotrope layer comprises graphene layers (14).
Re claim 26, Yamaguchi, FIG. 16D teaches the semiconductor die of claim 23 wherein the carbon allotrope layer comprises layers, films, flakes, fibers or sheets of a carbon allotrope (14).
Re claim 27, Yamaguchi, FIG. 16D teaches the semiconductor die claim 26 wherein the carbon allotrope comprises graphene, graphite, single-walled or multi-walled carbon nanotubes (14), or their combination.
Re claim 28, Yamaguchi, FIG. 14D teaches the semiconductor die of claim 26 wherein the carbon allotrope is functionalized with an oxide, reduced oxide, fluoride, chloride, bromide, iodide, metals, metal oxides, metalloid oxides, or mixtures thereof (28, [0106]).
Claim(s) 8 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang.
Yang differs from the claim invention by not disclosing wherein the thickness of the carbon allotrope layer is in the range of 5 µm to 500 µm.
However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997).
Claim(s) 19-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi/SUNG in view of Kane (Patent No.: US 1322702).
Yamaguchi/SUNG teaches all the limitation of claim 1.
Yamaguchi fails to teach the limitation of claim 19-22.
Kane teaches wherein the semiconductor device region comprises gallium nitride (GaN); wherein the semiconductor substrate comprises silicon carbide (SiC) and the semiconductor device region comprises gallium nitride (GaN); wherein the semiconductor device region comprises one or more layers of gallium nitride (GaN), aluminum gallium nitride (AlGaN), and aluminum nitride (AlN) and wherein the semiconductor substrate comprises one of sapphire, silicon carbide (SiC), gallium arsenide (GaAs), or silicon (Si) (col. 7, lines 17-30); and wherein the semiconductor die is a monolithic microwave integrated circuit (MMIC) (OTHER PUBLICATIONS, Bessemoulin, et al.; “0.1-μm GaAs PHEMT W-Band Low Noise Amplifier MMIC using Coplanar Waveguide Technology”; Page 2).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching in desirable for a manufacturing process flow to be scalable for mass production as taught by Kane, BACKGROUND.
Response to Arguments
Applicant's arguments with respect to claims 1 and 23 on the remarks filed on 12/29/2025 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893