DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claim 1 in the Applicant’s response dated 20 March 2026. The claim amendments have been addressed below.
The Examiner acknowledges the amendments to withdrawn claim 15 in the Applicant’s response dated 20 March 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chih-Yu Chang et al. (US 2021/0217847 A1; hereinafter “Chang”) in view of Masayoshi Iwayama et al. (US 2011/0062421 A1; hereinafter “Iwayama”).
Regarding Claim 1, Chang teaches a ferroelectric field effect transistor comprising:
a substrate (1, Fig. 1B, para [0021] describes a substrate 1);
a source protruding from an upper surface of the substrate in a first direction (EP1, Fig. 1C, para [0032] describes a first epitaxial region EP1 comprising a suitable source/drain material which can be seen protruding from an upper surface of the substrate in a first direction);
a drain protruding from the upper surface of the substrate in the first direction (EP1*, Fig. 1C, para [0032] describes a second epitaxial region EP1* comprising a suitable source/drain material which can be seen protruding from an upper surface of the substrate in a first direction);
a channel spaced apart from the upper surface of the substrate and extending between and connecting to the source and the drain in a second direction different from the first direction (11A-X, Fig. 1C, para [0021] describes nanosheet channels 11A-X or 11B-X or 11C-X, which can be seen extending between and connecting to the source EP1 and drain EP1* in a second direction and spaced apart from substrate 1);
a ferroelectric film surrounding at least a portion of an outer surface of the channel (12, Fig. 1B, para [0042] and para [0043] describes a ferroelectric film 12 surrounding channel layer 11 wherein ferroelectric film may be comprised of a hafnium oxide doped with silicon); and
a gate electrode surrounding the ferroelectric film such that ferroelectric film is between the gate electrode and the outer surface of the channel (13, Fig. 1B, para [0027] describes a metal gate layer surrounding nanosheet channels wherein gate electrodes 13 can be seen surrounding ferroelectric films 12 in Fig. 1B resulting in the ferroelectric film 12 being between the fate electrode 13 and the outer surface of the channel 11A-X).
Chang fails to explicitly disclose wherein a portion of the channel surrounded by the gate electrode has curved cross-sections having a plurality of different curvatures.
However, Iwayama teaches a similar semiconductor device wherein a portion of the channel surrounded by the gate electrode has curved cross-sections having a plurality of different curvatures (12b, Fig. 1 and Fig. 2A, para [0033] describes an Si nano-wire acting as a channel wherein a first portion of the channel 12b-2 surrounded by a gate electrode 18 has a different radius of curvature than curved cross-sections of a continuously changing radius of curvature section 12b-1 of the channel 12b under the gate electrode 18).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chang with Iwayama to further disclose a ferroelectric field effect transistor comprising a channel which has a plurality of different curvatures in a section surrounded by a gate electrode in order to provide the advantage of enabling an inner channel width to be reduced and provide a lightly doped outer channel region so that parasitic resistance in a semiconductor device can be reduced (Iwayama, para [0041] and para [0042]).
Regarding Claim 3, the combination of Chang and Iwayama discloses the ferroelectric field effect transistor of claim 1, wherein the channel has a tapered shape (Iwayama, 12b-1, Fig. 2A, para [0042] describes a portion 12b-1 of the channel nano-wire 12b that has a taper shape as shown in Fig. 2A).
Regarding Claim 4, the combination of Chang and Iwayama discloses the ferroelectric field effect transistor of claim 1, wherein the channel comprises
a first channel having a first radius (Iwayama, 12b-2, Fig. 2A, para [0042] describes a first region 12b-2 of a channel 12b having a first radius as can be seen in Fig. 2A), and
a second channel having a second radius different from the first radius (Iwayama, 12b-1, Fig. 2A, para [0042] describes a second region 12b-1 of a channel 12b having a second radius at an outermost portion underneath gate electrode 18 wherein said outermost portion has a radius that is different than the first radius of first region 12b-2 as can be seen in Fig. 2A).
Regarding Claim 5, the combination of Chang and Iwayama discloses all the limitations of claim 4.
The combination of Chang and Iwayama teach the ferroelectric field effect transistor of claim 4, wherein
the ferroelectric film (Chang, 12, Fig. 1B) comprises
a first ferroelectric film surrounding an outer circumferential surface of the first channel (Chang, 12, Fig. 1B, para [0026] describes ferroelectric films 12 surrounding nanosheet channel layers 11 wherein upon combining Chang with Iwayama the resulting first channel of Iwayama would be surrounded by the ferroelectric film of Chang thereby being a first ferroelectric film portion), and
a second ferroelectric film surrounding an outer circumferential surface of the second channel (Chang, 12, Fig. 1B, para [0026] describes ferroelectric films 12 surrounding nanosheet channel layers 11 wherein upon combining Chang with Iwayama the resulting second channel of Iwayama would be surrounded by the ferroelectric film of Chang thereby being a second ferroelectric film portion), and
the gate electrode surrounds both the first ferroelectric film and the second ferroelectric film (Chang, 13, Fig. 1B, para [0026] describes a metal gate layer 13 surrounding semiconductor channel nanosheet layers 11 wherein said channel layers are surrounded by ferroelectric film 12, thereby resulting in metal gate layers surrounding first and second ferroelectric films as shown in Fig. 1B and Fig. 1C).
Regarding Claim 6, the combination of Chang and Iwayama teach the ferroelectric field effect transistor of claim 5, wherein
the channel further comprises a third channel having a third radius (Iwayama, TR, annotated Fig. 2A depicts a portion of the channel 12b comprising a third channel having a third radius TR) different from the first radius and the second radius (Iwayama, FR, SR and TR, annotated Fig. 2A depicts wherein the first radius FR, second radius SR and third radius TR are all different from each other),
the ferroelectric film (Chang, 12, Fig. 1B) further comprises a third ferroelectric film surrounding an outer circumferential surface of the third channel (Chang, 12, Fig. 1B, para [0026] describes ferroelectric films 12 surrounding nanosheet channel layers 11 wherein upon combining Chang with Iwayama the resulting third channel of Iwayama would be surrounded by the ferroelectric film of Chang thereby being a third ferroelectric film portion), and
the gate electrode surrounds the first ferroelectric film, the second ferroelectric film, and the third ferroelectric film (Chang, 13, Fig. 1B, para [0026] describes a metal gate layer 13 surrounding semiconductor channel nanosheet layers 11 wherein said channel layers are surrounded by ferroelectric film 12, thereby resulting in metal gate layers surrounding first, second and third ferroelectric films as shown in Fig. 1B and Fig. 1C).
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Regarding Claim 7, the combination of Chang and Iwayama teach the ferroelectric field effect transistor of claim 1, wherein a ratio of a thickness of the ferroelectric film (Chang, 12, Fig. 8, para [0026] describes wherein a thickness of the ferroelectric film 12 is less than 5 nm therefore having a radius of less than 2.5 nm) to a radius of the channel (Iwayama, 12b, Fig. 1 and Fig. 2A, para [0041] describes wherein a thickness of the channel 12b is several nm and the thickness is less than the source/drain region which may be set to 10 nm, resulting in a radius less than 5 nm at most) is greater than 0 and less than or equal to 2 (upon combining the ferroelectric layer of Chang with the channel layer of Iwayama, the ratio of the radius of the ferroelectric film (less than 2.5 nm, using approximately 2.5 nm in this example), and the radius of the body (less than 5 nm, using approximately 2.5 nm in this example) would be greater than 0 and less than 2, approximately 1 in the current example).
Regarding Claim 8, the combination of Chang and Iwayama teach the ferroelectric field effect transistor of claim 1, wherein the ferroelectric film comprises
an oxide of at least one of Si, Al, Hf, or Zr (Chang, 12, Fig. 1B, para [0042] and para [0043] describes a ferroelectric film which may be comprised of a hafnium oxide), and
dopant including at least one of Si, Al, Y, La, Gd, Mg, Ca, Sr Ba, Ti, Zr, Hf, and N, and MgZnO, AlScN, BaTiO3, Pb(Zr, Ti)O3, SrBiTaO7, or polyvinylidene fluoride (PVDF) (Chang, 12, Fig. 8, para [0042] and para [0043] describes a ferroelectric film 12 which may be comprised of a hafnium oxide doped with silicon).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chih-Yu Chang et al. (US 2021/0217847 A1; hereinafter “Chang”) in view of Masayoshi Iwayama et al. (US 2011/0062421 A1; hereinafter “Iwayama”) in further view of Erica J. Thompson et al. (US 2019/0393350 A1; hereinafter “Thompson”).
Regarding Claim 2, the combination of Chang and Iwayama discloses all the limitations of claim 1.
The combination of Chang and Iwayama discloses the ferroelectric field effect transistor of claim 1, wherein the channel has an elliptical pillar shape (Chang, 11A-X, Fig. 1C, para [0018] describes wherein the nanowires comprising channels 11A-X may having an elliptical cross section constituting an elliptical pillar shape as they extend in a lengthwise direction)
Chang and Iwayama fail to explicitly disclose the ferroelectric field effect transistor of claim 1, wherein the channel has a continuously changing radius in an azimuth direction different from the first direction and the second direction
However, Thompson teaches a similar semiconductor device wherein the channel has a continuously changing radius in an azimuth direction different from the first direction and the second direction (Thompson, 118a and 118b, Fig. 1, para [0017], para [0032], and para [0042] describes wherein the nanowire channel section 118 has a body portion 118a that is continuous with the end portion 118b wherein the radius changes from a body portion 118a to an end portion 118b in an azimuth direction different from a first direction and a second direction).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chang and Iwayama with Thompson to further disclose a ferroelectric field effect transistor comprising a channel which has a continuously changing radius in an azimuth direction different from a first direction and a second direction in order to provide the advantage of reducing shape irregularities in a nanowire channel which comprises different radii of curvature wherein said irregularities can result in reduce device performance or result in inconsistent device performance (Thompson, para [0020] and para [0036]).
Response to Arguments
Applicant’s arguments with respect to claims 1-8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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