DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species A3, B1, C2, D1, E1, F1, and G2 in the reply filed on 11/30/2025 is acknowledged. Claims 10, 11, and 27-46 are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 12, 15, 16, 18-20, and 23-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lan (CN110993758).
Regarding claim 1, Lan discloses a micro-LED (Fig. 1) comprising a first type semiconductor layer (26, 30, and the space between in Fig. 1);
a first type cap layer (22) formed on the first type semiconductor layer; and
a light emitting layer (23) formed on the first type cap layer; wherein
the first type semiconductor layer comprises a mesa structure (see Fig. 1), a trench (intervening space), and an ion implantation fence (30; which is considered an ion implantation fence as it can form a buffer against ion implantations) separated from the mesa structure, the trench extending up through the first type semiconductor layer and extending up into at least part of the first type cap layer; and the ion implantation fence is formed around the trench and the trench is formed around the mesa structure, wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure (silicon oxynitride for the ion implantation fence).
Regarding claim 2, Lan further discloses wherein a top surface of the ion implantation fence lower than a top surface of the first semiconductor layer (as Applicant didn’t claim topmost surface, the lateral surfaces along the side of the fence may be considered top surfaces, some of which are lower than a top surface of the first semiconductor layer (see Fig. 1).
Regarding claim 3, Lan further discloses wherein a bottom surface of the ion implantation fence is aligned with, higher than, or lower than a bottom surface of the first type semiconductor layer (see Fig. 1).
Regarding claim 4, Lan further discloses wherein a top surface of the ion implantation fence is lower than a top surface of the trench (see Fig. 1).
Regarding claim 5, Lan further discloses wherein the trench extends up through the first type cap layer (See Fig. 1).
Regarding claim 6, Lan further discloses wherein the trench extends up into at least a part of the light emitting layer (See Fig. 1).
Regarding claim 7, Lan further discloses a second type cap layer (24) formed on a top surface of the light emitting layer, and a second type semiconductor layer (26, which contains germanium, a semiconductor) formed on the second type cap layer, wherein a conductive type of the second type semiconductor layer is different from the conductive type of the first type semiconductor layer.
Regarding claim 8, Lan further discloses wherein the trench further extends up through the first type cap layer, the light emitting layer, and into an interior of the second type cap layer (see Fig. 1, the examiner notes that the second type cap layer is across two mesas).
Regarding claim 9, Lan further discloses wherein the trench further extends up through the second type cap layer and into an interior of the second type semiconductor layer.
Regarding claim 12, Lan further discloses wherein a width of the trench is not greater than 50% of a width of the mesa structure (see Fig. 1).
Regarding claim 15, Lan further discloses wherein a thickness of the first type semiconductor layer is greater than a thickness of the light emitting layer (See Fig. 1).
Regarding claim 16, Lan further discloses a bottom isolation layer (10) filled in the trench.
Regarding claims 18-19, these claims are directed to the method of manufacturing the device and do not necessitate a structure that in its final form is different from that of Lan (e.g., there is not requirement that the implanted ion remain in the structure).
Regarding claim 20, Lan further discloses wherein a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure (see Fig. 1).
Regarding claim 23, Lan further discloses a integrated circuit (IC) backplane (10) formed under the first type semiconductor layer and a connection structure (“a through hole extending to the driving circuit to electrically connect the light emitting chip and the driving circuit”) electrically connecting the IC backplane with the first type semiconductor layer.
Regarding claim 24, Lan further discloses wherein the connection structure is a connection pillar (“a through hole extending to the driving circuit to electrically connect the light emitting chip and the driving circuit”).
Regarding claim 25, Lan further discloses a bottom contact (21) formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure being connected with the bottom contact and a bottom surface of the connection structure being connected with the IC backplane.
Regarding claim 26, Lan further discloses a micro-LED array panel, comprising a plurality of micro-LEDs according to claim 1 (“a display array of a micro light-emitting diode, which is suitable for manufacturing the display array of the micro light-emitting diode shown in fig. 1”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lan as applied to claim 12 above.
Regarding claim 13, Lan does not explicitly disclose that the width of the trench is not greater than 200 nm.
However, the width of the trench is a result effective variable as too great a width will reduce pixel density of the display and too small a width will not allow enough room for the light absorbing layer. As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form the width of the trench to not be greater than 200 nm as where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05(II)(A)).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lan as applied to claim 1 above, and further in view of Lin et al. (US 2014/0150858 A1).
Regarding claim 14, Lan differs from the claimed invention by the substitution of one of the claimed materials with a different material. However, AlInP and the corresponding function of absorbing light was known in the art (¶ 0114 of Lin). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known compound of AlInP as taught by Lin for material of Lan and the results of the substitution would have been predictable in absorbing light. (see MPEP § 2143(I)(B)).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lan as applied to claim 16 above, and further in view of Fujii (US 2008/0079783 A1).
Regarding claim 17, Lan does not disclose that it’s circuit board 10 comprises one of the claimed compounds. However, SiO2 and its corresponding function of being used in a circuit board was known in the art (¶ 0086 of Fujii). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to use SiO2 as a top layer of the printed circuit board 10 of Lan and the results would have been predictable at serving as the top electrical insulating layer of the circuit board (in which the through hole for the connection is made).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lan as applied to claim 20 above.
Regarding claim 21, Lan does not explicitly disclose that the width of the ion implantation fence is not greater than 200 nm, that the diameter of the mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 100 nm.
However, the width ion implantation fence is a result effective variable as too great a width will reduce pixel density of the display and too small a width will not allow enough room for the light absorbing layer to absorb light. As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form the width of the ion implantation fence to not be greater than 200 nm as where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05(II)(A)).
Further, the diameter of the mesa structure is a result effective variable as too great a diameter will reduce pixel density of the display and too small a diameter will not emit a sufficient amount of light. As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form the diameter of the mesa structure to not be greater than 2500 nm as where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05(II)(A)).
Further, the thickness of the first type semiconductor layer is a result effective variable as too great a thickness will create an unnecessarily large voltage drop across the layer and too small a thickness will not introduce a sufficient amount of charge carriers. As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form the thickness of the first type semiconductor layer to not be greater than 100 nm as where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05(II)(A)).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lan as applied to claim 7 above, and further in view of David (US 2019/0041699 A1) and Hsu (US 2012/0161100 A1).
Regarding claim 22, Lan differs from the claimed invention by not disclosing one of the claimed compositions for the first type semiconductor layer which Lan discloses is a transparent conductor. However, GaN and the corresponding function of a transparent conductor was known in the art (¶ 0190 of David). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known compound of GaN as taught by David for compound of Lan and the results of the substitution would have been predictable at forming a transparent conductor. (see MPEP § 2143(I)(B)).
Lan also differs from the claimed invention by not disclosing one of the claimed compositions for the second type semiconductor layer which Lan discloses is an N-type electrode. However, GaN and the corresponding function an N-type electrode was known in the art (¶ 0020 of Hsu). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known compound of GaN as taught by Hsu for compound of Lan and the results of the substitution would have been predictable at forming an N-type conductive layer. (see MPEP § 2143(I)(B)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A CULBERT/ Examiner, Art Unit 2815
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