DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s request for continued examination (RCE) filed 1/16/26 has been entered and considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 7, 10, 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (9,502,584 B1) in view of Tsai et al (US 2020/0328125 A1), further in view of Korec et al (US 2008/0246086 A1).
Regarding claim 1, Chang et al discloses a method of fabricating a semiconductor device (Figures 1A-1G), comprising: providing a first isolation feature (Figure 1D, reference 100) in a substrate (Figure 1D, reference 102), wherein the first isolation feature (Figure 1D, reference 102 middle) defines and isolates a cathode region (Figure 1D, reference 20) of a Schottky barrier diode (SBD) (Figure 1D, reference 100; column 5, lines 18-23) from an anode region (Figure 1D, reference 10) of the SBD (Figure 1D, reference 100; column 5, lines 18-23); forming a patterned resist protective oxide (RPO) layer (Figure 1F, reference 116) over the first isolation feature (Figure 1F, reference 110).
However, Chang et al does not disclose forming a first metal contact that extends through the patterned RPO layer and partially through the first isolation feature.
Tsai et al discloses forming a first metal contact (Figure 1C, reference 230; paragraph 0051) that extends through the patterned RPO layer (Figure 1C, reference 120) and partially through the first isolation feature (Figure 1C, reference 140).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Chang et al with the teachings of Tsai et al for the purpose of forming a metal contact through the RPO layer and partial through the first isolation feature, in order to continue with the formation of interconnect structures in semiconductor devices.
Chang et al and Tsai et al disclose the above claimed subject matter.
However, Chang et al and Tsai et al do not disclose wherein lateral surfaces of the first metal contact interface with portions of both the patterned RPO layer and the first isolation feature.
Korec et al discloses wherein lateral surfaces of the first metal contact interface (Figure 15, reference 28) with portions of both the patterned RPO layer (Figure 15, reference 108) and the first isolation feature (Figure 15, reference 19).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Chang et al and Tsai et al with the teachings of Korec et al for the purpose of forming a metal contact wherein lateral surfaces interface with portions of both the patterned RPO layer and the first isolation feature in order reduce the capacitance between the gate and drain in a semiconductor device.
Regarding claim 2, Chang et al discloses wherein the first isolation feature (Figure 1G, reference 100; middle and right) surrounds the anode region (Figure 1G, reference 10) of the SBD (Figure 1G, reference 100).
Regarding claim 7, Chang et al discloses further comprising: prior to forming the patterned RPO layer (Figure 1F, reference 116), forming an N+ region (Figure 1E, reference 114) in the cathode region (Figure 1E, reference 120) and a P+ region (Figure 1E, reference 112) in the anode region (Figure 1E, reference 10); and after forming the patterned RPO layer (Figure 1F, reference 116), forming a second metal contact (Figure 1G, reference 118) that contacts the N+ region (Figure 1G, reference 114) and a third metal contact (Figure 1G, reference 120) that contacts the P+ region (Figure 1G, reference 112).
Regarding claim 10, Chang et al discloses further comprising providing a second isolation feature (Figure 1G, reference 110 left and right) in the substrate (Figure 1G, reference 102), wherein the second isolation feature (Figure 1G, reference 110 left and right) surrounds the SBD (Figure 1G, reference 100).
Regarding claim 17, Chang et al discloses a Schottky barrier device (SBD) (Figure 1G, reference 100; column 5, lines 18-23), comprising: an isolation feature (Figure 1G, reference 110) in a substrate (Figure 1G, reference 102), wherein the isolation feature (Figure 1G, reference 110) defines and isolates a cathode region (Figure 1G, reference 20) of the SBD (Figure 1G, reference 100; column 5, lines 18-23) from an anode region (Figure 1G, reference 110) of the SBD (Figure 1G, reference 100; column 5, lines 18-23); a patterned resist protective oxide (RPO) layer (Figure 1G, reference 116) disposed over the isolation feature (Figure 1G, reference 110).
However, Chang et al does not disclose a metal contact that extends through the patterned RPO layer and partially through the isolation feature.
Tsai et al discloses forming a metal contact (Figure 1C, reference 230; paragraph 0051) that extends through the patterned RPO layer (Figure 1C, reference 120) and partially through the first isolation feature (Figure 1C, reference 140).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Chang et al with the teachings of Tsai et al for the purpose of forming a metal contact through the RPO layer and partial through the first isolation feature, in order to continue with the formation of interconnect structures in semiconductor devices.
Chang et al and Tsai et al disclose the above claimed subject matter of claim 17.
However, Chang et al and Tsai et al do not disclose wherein lateral surfaces of the metal contact interfacing with portions of the patterned RPO layer and portions of the isolation feature.
Korec et al discloses wherein lateral surfaces of the metal contact interfacing (Figure 15, reference 28) with portions of the patterned RPO layer (Figure 15, reference 108) and portions of the isolation feature (Figure 15, reference 19).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Chang et al and Tsai et al with the teachings of Korec et al for the purpose of forming a metal contact wherein lateral surfaces interface with portions of the patterned RPO layer and the isolation feature in order reduce the capacitance between the gate and drain in a semiconductor device.
Regarding claim 20, Chang et al in view of Tsai et al discloses wherein the metal contact (Figure 1C, reference 230) extends into the isolation feature (Figure 1C, reference 140) by a first distance, wherein a depth of the isolation feature (Figure 1C, reference 140) is equal to a second distance, and wherein the first distance is in a range of between about 0.3-0.5 times the second distance (Figure 1C, reference 140 left, middle and right; Tsai et al).
Claim(s) 3-6 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (9,502,584 B1) and Tsai et al (US 2020/0328125 A1) in view of Korec et al (US 2008/0246086 A1), further in view of Kuo et al (11,710,783 B2).
Chang et al, Tsai et al and Korec et al disclose all of the above claimed subject matter.
However, Chang et al, Tsai et al and Korec et al do not disclose wherein the RPO layer includes a multi-layer dielectric stack (claim 3), wherein the RPO layer includes a first oxide layer, a nitride layer disposed over the first oxide layer, and a second oxide layer disposed over the nitride layer (claims 4 and 18), wherein forming the first metal contact comprises: performing a three-step etch process to form an opening that extends through the patterned RPO layer and extends into the first isolation feature; and depositing a metal layer within the opening to provide the first metal contact (claim 5) nor wherein the RPO layer includes a first oxide layer, a nitride layer disposed over the first oxide layer, and a second oxide layer disposed over the nitride layer, wherein a first step of the three-step etch process etches a portion of the second oxide layer, wherein a second step of the three-step etch process etches a portion of the nitride layer, and wherein a third step of the three-step etch process etches a portion of the first oxide layer and a portion of the first isolation feature to form the opening (claim 6).
Kuo et al discloses wherein the RPO layer includes a multi-layer dielectric stack (Figure 1, reference 104), wherein the RPO layer (Figure 1, reference 104) includes a first oxide layer (Figure 1, reference 112), a nitride layer (Figure 1, reference 116) disposed over the first oxide layer (Figure 1, reference 112), and a second oxide layer (Figure 1, reference 114) disposed over the nitride layer ((Figure 1, reference 116), wherein forming the first metal contact comprises: performing a three-step etch process to form an opening that extends through the patterned RPO layer and extends into the first isolation feature; and depositing a metal layer within the opening to provide the first metal contact (Figure 1, reference 104; column 4, lines 34-62) and wherein the RPO layer includes a first oxide layer, a nitride layer disposed over the first oxide layer, and a second oxide layer disposed over the nitride layer, wherein a first step of the three-step etch process etches a portion of the second oxide layer, wherein a second step of the three-step etch process etches a portion of the nitride layer, and wherein a third step of the three-step etch process etches a portion of the first oxide layer and a portion of the first isolation feature to form the opening (Figure 1, reference 104; column 4, lines 34-62).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Chang et al and Tsai et al with the teachings of Kuo et al, for the purpose of forming a multilayer RPO made up of ONO material etched back by multiple processes providing a contact opening to an isolation feature in order to assist in formation of bases with low resistances in semiconductor devices.
Allowable Subject Matter
8. Claims 8, 9 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
9. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest a method of fabricating a semiconductor device, comprising: further comprising: forming a first metal interconnect layer that electrically couples the first metal contact and the second metal contact; and forming a second metal interconnect layer that electrically couples to the third metal contact (claim 8) further comprising forming a plurality of metal contacts that extend through the patterned RPO layer and partially through the first isolation feature, wherein the plurality of metal contacts surrounds the anode region of the SBD (claim 9) and further comprising: a metal interconnect layer that electrically couples the metal contact to another metal contact in contact with an N+ region in the cathode region of the SBD (claim 19) incorporated into the claims from which they depend from, further incorporated into independent claims 1 and 17 and in the context of their recited process and apparatus, along with their depending claims.
10. Claims 11-16 are allowed over the prior art of record.
11. The following is an examiner’s statement of reasons for allowance: The prior art does not disclose nor fairly suggest a method, comprising: patterning the multi-layer dielectric stack to remove portions of the multi- layer dielectric stack from over the anode region, the cathode region, and the second isolation feature, while the patterned multi-layer dielectric stack remains disposed over the first isolation feature; and performing a multi-step etch process to the patterned multi-layer dielectric stack to form a plurality of openings that extend through the patterned multi-layer dielectric stack and partially through the first isolation feature on multiple sides of the anode region as described in independent claim 11 and in the context of its recited process, along with its depending claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/MONICA D HARRISON/Primary Examiner, Art Unit 2815
mdh
January 27, 2026