DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 03/06/2026 has been entered. Claims 8 and 14-20 are canceled. Claims
21-22 are new. Claims 1-7, 9-13 and 21-22 are pending.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 03/06/2026, have been fully considered, the arguments are not persuasive and some of them are moot because do not apply to new ground of rejections with new references, US 20180061805 A1 to Fang and US 20230378107 A1 to Mao, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-7 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, it recites the limitation “a polyimide layer covering… …a plane along the top surfaces of the first and second metal pillars parallel to a plane along a bottom surface of the semiconductor die”. It is not clear what means the element “a plane along the top surfaces of the first and second metal pillars”. The limitation is not explained and it does not show in the drawings. Therefore, it is indefinite. For the examination purpose, the limitation “a polyimide layer covering… …a plane along the top surfaces of the first and second metal pillars parallel to a plane along a bottom surface of the semiconductor die” is interpreted as “a polyimide layer covering… …regions outside of the of the region between the first and second metal pillars parallel to a plane along a bottom surface of the semiconductor die”.
Regarding claims 2-7 and 9, those are rejected under 35 U.S.C. 112 (b), because of their dependency status from claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Fay et al. (US 20140015124 A1, hereinafter Fay, of the record) in view of Mao et al. (US 20230378107 A1, hereinafter Mao).
Re: Independent Claim 1, Fay discloses a semiconductor package, comprising:
a semiconductor die (102 in [0009], Fig. 7) including circuitry (circuitry of semiconductor die 102 in [0009], Fig. 7);
a first metal pillar (104-1 a conductive element a copper material 106 in [0009], Fig. 7-Annotated) coupled to the circuitry (bond pad 112 is in electrical contact with circuitry of semiconductor die 102 through conductive via 120 in [0009], Fig. 4C) and extending away from the semiconductor die (102);
a second metal pillar (104-2 a conductive element a copper material 106 in [0009], Fig. 7-Annotated) coupled to the circuitry (in [0009], Fig. 4C) and extending away from the semiconductor die (102), a distance (a distance of about 100 microns between two conductive pillars in [0042], Fig. 6B-Annotated) between the first (104-1) and second metal (104-2) pillars not exceeding 100 microns;
a polyimide layer (218 photo definable material polyimide in [0034], Fig. 7-Annotated) covering side surfaces portions (Fig. 7-Annotated) of the first (104-1) and second (104-2) metal pillars and covering a region between (Fig. 7-Annotated) the first (104-1) and second (104-2) metal pillars, regions outside (Fig. 7-Annotated) of the region between the first (104-1) and second (104-2) metal pillars parallel to a plane along a bottom surface of the semiconductor die (102), the polyimide layer (218) in the region between the first (104-1) and second (104-2) metal pillars having a thickness not exceeding 15 microns (an initial thickness t1 of about 5 microns of layer 218, then after treatment resulting in a thickness t3 less than t1 in [0034,0037] Fig. 4B, 4C) and lacking a boundary (there is not a boundary in the polyimide layer Fig. 7-Annotated) between separate applications of polyimide to the region;
a mold compound (150 in [0044], Fig. 7-Annotated) covering the polyimide layer (218) in the region between (Fig. 7-Annotated) the first (104-1) and second (104-2) metal pillars; and
conductive terminals (108,110 in [0042], Fig. 7-Annotated) coupled (in [0042], Fig. 7-Annotated) to the first (104-1) and second (104-2) metal pillars and exposed to an exterior of the mold compound (150).
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Fay’s Figure 7-Annotated.
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Fay’s Figure 6B-Annotated.
Fay does not expressly disclose a polyimide layer covering only a portion of top surfaces of the first and second metal pillars.
However, in the same semiconductor device field of endeavor, Mao discloses a polyimide layer (116 a polyimide layer in [0022], Fig. 1) covering only a portion (one portion of 114 metal pad is covered by 116 in Fig. 1-Annotated) of top surfaces of the first metal pillar (114 a conductive pad in [0022], Fig. 1).
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Mao’s Figure 1-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Mao’s feature of a polyimide layer covering only a portion of top surface of the first metal pillar to Fay’s device to obtain a polyimide layer covering only a portion of top surfaces of the first and second metal pillars to reroute input/output (I/O) pads of an originally designed circuit via a wafer-level metal distribution process and a micro bump process so that the circuitry can be adapted for different packaging forms ([0015], Mao).
Re: Claim 2, Fay modified by Mao discloses the semiconductor package of claim 1, wherein the first metal pillar is coupled to a metal layer (112 in [0009], Fig. 4B, C, Fay) and the metal layer (112, Fay) is coupled to the circuitry (bond pad 112 is in electrical contact with circuitry of semiconductor die 102 through conductive via 120 in [0009], Fig. 4C, Fay), and wherein the polyimide layer at least partially covers (Figs. 4B, C, Fay) the metal layer (112, Fay).
Re: Claim 3, Fay modified by Mao discloses the semiconductor package of claim 2, wherein the metal layer (112, Fay) has a thickness ranging between 4 microns and 25 microns (112 having a thickness of about 6 microns, Fig. 6B-Annotated, Fay), the first and second metal pillars have thicknesses ranging from 10 microns to 80 microns (104-1, 104-2 having a thickness of less than 20 microns, Fig. 6A-Annotated, Fay), and solder bumps on the first and second metal pillars have thicknesses ranging from 10 microns to 60 microns (110 having a thickness of more than 10 microns, Fig. 6A-Annotated, Fay).
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Fay’s Figure 6A-Annotated.
Re: Claim 7, Fay modified by Mao discloses the semiconductor package of claim 1,
Fay modified by Mao does not expressly disclose wherein the polyimide layer in the region between the first and second metal pillars has a thickness ranging between 5 microns and 15 microns.
However, the Applicant has not presented persuasive evidence that the claimed
“thickness of the polyimide layer in the region between the first and second metal pillars ranging between 5 microns and 15 microns” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed range of the thickness of the polyimide layer in the region between the first and second metal pillars ranging between 5 microns and 15 microns). Also, the applicant has not shown that the claimed “difference of thickness of the polyimide layer in the region between the first and second metal pillars ranging between 5 microns and 15 microns” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Fay discloses “an initial thickness t1 of about 5 microns of layer 218, then after treatment resulting in a thickness t3 less than t1 in [0034,0037] Fig. 4B, 4C”, therefore, the thickness is a result effective variable. It has been held that is not inventive to discover the optimum thickness of the polyimide layer in the region between the first and second metal pillars by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the thickness of the polyimide layer in the region between the first and second metal pillars ranging between 5 microns and 15 microns to improve the electrical characteristics of the device using a passivation/protection layer with a desired thickness.
Claim(s) 4-5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Fay in view of Mao and further in view of Lin (US 20240071885 A1, hereinafter Lin, of the record).
Re: Claim 4, Fay modified by Mao discloses the semiconductor package of claim 3, wherein the semiconductor die includes vias (120 in [0042], Fig. 6A, Fay) having diameters in the range of 0.5 microns to 10 microns (120 having a thickness of less than 10 microns, Fig. 6A-Annotated, Fay).
Fay modified by Mao does not expressly disclose wherein the semiconductor die includes tungsten or copper-filled vias.
However, in the same semiconductor device field of endeavor, Lin discloses wherein the semiconductor die (120 in [0026], Fig. 2b) includes tungsten or copper-filled vias (130 conductive vias made of Cu, in [0026], Fig. 2b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lin’s feature of wherein the semiconductor die includes tungsten or copper-filled vias to the combination of Fay and Mao to improve the electrical connections ([0026], Lin).
Re: Claim 5, Fay modified by Mao and Lin discloses the semiconductor package of claim 4,
Fay modified by Lin does not expressly disclose wherein the semiconductor package is a quad flat no lead (QFN) type package.
However, in the same semiconductor device field of endeavor, Lin discloses wherein the semiconductor package is a quad flat no lead (QFN) type package (420 a quad flat non-leaded package (QFN) in [0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lin’s feature of wherein the semiconductor package is a quad flat no lead (QFN) type package to the combination of Fay and Mao to reduce the manufacturing cost of the devices that results in a lower cost for consumers ([0073], Lin).
Claim(s) 6 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Fay in view of Mao and further in view of Kouno (US 20080191357 A1, hereinafter Kouno, of the record).
Re: Claim 6, Fay modified by Mao discloses the semiconductor package of claim 1,
Fay modified by Mao does not expressly disclose wherein the polyimide layer has a depression in the region between the first and second metal pillars.
However, in the same semiconductor device field of endeavor, Kouno discloses wherein the polyimide layer (12 a polyimide resin in [0079], Fig. 1) has a depression (Fig. 1) in the region between the first and second metal pillars (11 two columnar electrodes at left and right side in [0079], Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kouno’s feature of wherein the polyimide layer has a depression in the region between the first and second metal pillars to the combination of Fay and Mao to prevent the electromigration ([0079], Kouno).
Claim(s) 9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Fay in view of Mao and further in view of Nanba (US 20120104602 A1, hereinafter Nanba, of the record).
Re: Claim 9, Fay modified by Mao discloses the semiconductor package of claim 1,
Fay modified by Mao does not expressly disclose wherein the mold compound has a filler size ranging from 10 microns to 30 microns.
However, in the same semiconductor device field of endeavor, Nanba discloses wherein the mold compound (7 bonding resin layer in [0086], Fig. 1A) has a filler size ranging from 10 microns to 30 microns (7 having a thickness of 30 microns in [0086], Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Nanba’s feature of wherein the mold compound has a filler size ranging from 10 microns to 30 microns to the combination of Fay and Mao to protect the electrical connections ([0086], Nanba).
Claim(s) 10 and 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Fay in view of Fang et al. (US 20180061805 A1, hereinafter Fang).
Re: Independent Claim 10, Fay discloses a semiconductor package, comprising:
a semiconductor die (102 in [0009], Fig. 7) including circuitry (circuitry of semiconductor die 102 in [0009], Fig. 7);
a first metal pillar (104-1 a conductive element a copper material 106 in [0009], Fig. 7-Annotated) pillar, a second metal pillar (104-2 a conductive element a copper material 106 in [0009], Fig. 7-Annotated), and a third metal pillar (104-3 a conductive element a copper material 106 in [0009], Fig. 7-Annotated) coupled to the circuitry (bond pad 112 is in electrical contact with circuitry of semiconductor die 102 through conductive via 120 in [0009], Fig. 4C) and extending away from the semiconductor die (102) a distance (a distance of about 100 microns between two conductive pillars in [0042], Fig. 6B-Annotated) between the first (104-1) metal pillar and the second (104-2) metal pillar equal to or less than 100 microns (Fig. 6B-Annotated);
a polyimide layer (218 photo definable material polyimide in [0034], Fig. 7-Annotated) covering portions (Fig. 7-Annotated) of the first (104-1), second (104-2) and third (104-3) metal pillars and covering a region between (Fig. 7-Annotated) the first (104-1) and second (104-2) metal pillars and a region between (Fig. 7-Annotated) the second (104-2) and third (104-3) metal pillars, the polyimide layer (218) in the region between the first (104-1) and second (104-2) metal pillars lacking a boundary (there is not a boundary in the polyimide layer Fig. 7-Annotated) between separate applications of polyimide (218) to the region;
a mold compound (150 in [0044], Fig. 7-Annotated) covering the polyimide layer (218); and
conductive terminals (108,110 in [0042], Fig. 7-Annotated) coupled to the first (104-1), second (104-2), and third (104-3) metal pillars and exposed to an exterior of the mold compound (150).
Fay does not expressly disclose a distance between the second metal pillar and the third metal pillar more than 100 microns and wherein the polyimide layer in the region between the first and second metal pillars has a thickness ranging between 5 microns and 15 microns.
However, in the same semiconductor device field of endeavor, Fay discloses wherein the polyimide layer in the region between the first and second metal pillars has a thickness ranging between 5 microns and 15 microns, by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II). (see rejection of claim 8).
Still, Fay does not expressly disclose a distance between the second metal pillar and the third metal pillar more than 100 microns.
However, in the same semiconductor device field of endeavor, Fang discloses a distance between the second metal pillar (14-R a conductive pillar in [0039], Fig. 1-Annotated) and the third metal pillar (15-L a conductive pillar in [0039], Fig. 1-Annotated) greater (Fig. 1-Annotated) than the distance between the first metal pillar (14-L a conductive pillar in [0039], Fig. 1-Annotated) and the second metal pillar (14-R a conductive pillar in [0039], Fig. 1-Annotated).
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Fang’s Figure 1-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Fang’s feature of a distance between the second metal pillar and the third metal pillar greater than the distance between the first metal pillar and the second metal pillar to Fay’s device to ensure that all the upper surfaces of the conductive pillars are exposed ([0003], Hu).
Still, Fay modified by Fang does not expressly disclose a distance between the second metal pillar and the third metal pillar more than 100 microns.
However, the Applicant has not presented persuasive evidence that the claimed
“distance between the second metal pillar and the third metal pillar more than 100 microns” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed range of the distance between the second metal pillar and the third metal pillar more than 100 microns). Also, the applicant has not shown that the claimed “difference of distance between the second metal pillar and the third metal pillar more than 100 microns” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Fay modified by Fang discloses “a distance between the second metal pillar and the third metal pillar greater than the distance between the first metal pillar and the second metal pillar in Fig. 1” and “a distance of about 100 microns between the first and the second conductive pillars in [0042], Fig. 6B-Annotated”, therefore, the distance between the second metal pillar and the third metal pillar is a result effective variable. It has been held that is not inventive to discover the optimum distance between the second metal pillar and the third metal pillar by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a distance between the second metal pillar and the third metal pillar more than 100 microns to ensure that all the upper surfaces of the conductive pillars are exposed ([0003], Fang).
Re: Claim 12, Fay modified by Fang discloses the semiconductor package of claim 10, wherein the first metal pillar is coupled to a metal layer (112 in [0009], Fig. 4B, C, Fay) and the metal layer (112, Fay) is coupled to the circuitry (bond pad 112 is in electrical contact with circuitry of semiconductor die 102 through conductive via 120 in [0009], Fig. 4C, Fay), and wherein the polyimide layer at least partially covers (Figs. 4B, C, Fay) the metal layer (112, Fay).
Claim(s) 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Fay in view of Fang and further in view of Lin et al. (US 20240071885 A1, hereinafter Lin, of the record).
Re: Claim 11, Fay modified by Hu discloses the semiconductor package of claim 10,
Fay modified by Fang does not expressly disclose wherein the semiconductor package is a quad flat no lead (QFN) type package.
However, in the same semiconductor device field of endeavor, Lin discloses wherein the semiconductor package is a quad flat no lead (QFN) type package (420 a quad flat non-leaded package (QFN) in [0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lin’s feature of wherein the semiconductor package is a quad flat no lead (QFN) type package to Fay’s device to reduce the manufacturing cost of the devices that results in a lower cost for consumers ([0073], Lin).
Claim(s) 13 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Fay in view of Fang and further in view of Nanba (US 20120104602 A1, hereinafter Nanba, of the record).
Re: Claim 13, Fay modified by Fang discloses the semiconductor package of claim 10,
Fay modified by Fang does not expressly disclose wherein the mold compound has a filler size ranging from 10 microns to 30 microns.
However, in the same semiconductor device field of endeavor, Nanba discloses wherein the mold compound (7 bonding resin layer in [0086], Fig. 1A) has a filler size ranging from 10 microns to 30 microns (7 having a thickness of 30 microns in [0086], Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Nanba’s feature of wherein the mold compound has a filler size ranging from 10 microns to 30 microns to the combination of Fay and Fang to protect the electrical connections ([0086], Nanba).
Claim(s) 21-22 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Fay in view Fang and further in view of Hu et al. (US 20150279776 A1, hereinafter Hu, of the record).
Re: New Claim 21, Fay modified by Fang discloses the semiconductor package of claim 10
Fay modified by Fang does not expressly disclose wherein the polyimide layer covers part, but not all, of a circumference of a top surface of the first and second metal pillars.
However, in the same semiconductor device field of endeavor, Hu discloses wherein the polyimide layer (110 a polyimide in [0016], Fig. 2) covers part, but not all, of a circumference of a top surface (108-1-top, Fig. 2-Annotated) of the first metal pillar (108-1 conductive pillar in [0016], Fig. 2-Annotated) and part (Fig. 2-Annotated), but not all, of a circumference of a top surface (108-2-top, Fig. 2-Annotated) of the second metal pillar (108-2 conductive pillar in [0016], Fig. 2-Annotated).
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Hu’s Figure 2-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hu’s feature of wherein the polyimide layer covers part, but not all, of a circumference of a top surface of the first metal pillar and part, but not all, of a circumference of a top surface of the second metal pillar to the combination of Fay and Fang to tune the electrical properties ([0016], Hu).
Re: New Claim 22, Fay modified by Fang discloses the semiconductor package of claim 10
Fay modified by Fang does not expressly disclose wherein the polyimide layer covers part, but not all, of a circumference of a top surface of the first and second metal pillars and wherein the polyimide layer covers all of a circumference of a top surface of the third metal pillar.
However, in the same semiconductor device field of endeavor, Hu discloses wherein the polyimide layer (110 a polyimide in [0016], Fig. 2) covers part, but not all, of a circumference of a top surface (108-1-top, Fig. 2-Annotated) of the first metal pillar (108-1 conductive pillar in [0016], Fig. 2-Annotated) and part (Fig. 2-Annotated), but not all, of a circumference of a top surface (108-2-top, Fig. 2-Annotated) of the second metal pillar (108-2 conductive pillar in [0016], Fig. 2-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hu’s feature of wherein the polyimide layer covers part, but not all, of a circumference of a top surface of the first metal pillar and part, but not all, of a circumference of a top surface of the second metal pillar to the combination of Fay and Fang to tune the electrical properties ([0016], Hu).
Still, Fay modified by Fang and Hu does not expressly disclose wherein the polyimide layer covers all of a circumference of a top surface of the third metal pillar.
However, one of ordinary skill in the art looking to obtain different patterned/configurations to form the conductive pillars covered by a polyimide layer for improving electrical characteristics of the device, and finding in Hu’ invention, two different patterned/configurations to form the conductive pillars covered by a polyimide layer, one of them as showed in Fig. 2 (a polyimide layer covering covers part, but not all, of a circumference of a top surface of the metal pillar) and the other one as showed in Fig. 4C (a polyimide layer covering all of a circumference of a top surface of the metal pillar). It would have been able to obvious to try to choose one of two possible options, the first one is forming all conductive pillars with the same patterned (a polyimide layer covering partially the circumference of a top surface of the metal pillars), the second one is forming some conductive pillars with one patterned (a polyimide layer covering partially the circumference of a top surface of the metal pillars) and other group of conductive pillars with another patterned (a polyimide layer covering all circumference of a top surface by a polyimide layer), this last option allows to create an alternative/flexible configuration and improving the electrical connections of the device, Hu, [0016, 0021] (see MPEP 2143.1 (e)).
The combination of Fay modified by Fang and Hu results in wherein the polyimide layer covers all of a circumference of a top surface of the third metal pillar.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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