Prosecution Insights
Last updated: July 17, 2026
Application No. 18/162,079

WIRE BONDED SEMICONDUCTOR DEVICE PACKAGE

Final Rejection §103
Filed
Jan 31, 2023
Examiner
CHOUDHRY, MOHAMMAD M
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
575 granted / 702 resolved
+13.9% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
33 currently pending
Career history
736
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
93.6%
+53.6% vs TC avg
§102
1.6%
-38.4% vs TC avg
§112
1.0%
-39.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 702 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-7, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Shibuya et al. (US 2019/0206768, hereinafter Shibuya) in view of Somma et al. (US 2019/0287880, hereinafter Somma). With respect to claim 1, Shibuya discloses an apparatus (Fig. 22), comprising: a metal leadframe (Para 0004; 0031; 0038; ; 0054 – leadframe strip 1800) comprising: a die pad (1804) in a central portion of the metal leadframe (1804 is in the central portion of the leadframe) and having a thickness that is the same as a full thickness of the metal leadframe (Fig. 22); leads (1806) spaced from the die pad (1806’s are spaced apart from 1804), the leads comprising: an interior end (see below) spaced from the die pad by an opening (interior end is spaced apart from 1804) in the metal leadframe and having the full thickness (see below); a central portion connected to the interior end (see below) and extending away from the die pad having a partial thickness that is less than the full thickness (see below – central portion extends away from 1804 and has a partial thickness less that the full thickness); and an exterior end (see below) having the full thickness extending from the central portion and away from the die pad (see below – exterior end has the full thickness and extends from the central portion away from 1804), the exterior end having a board side surface (Para 0031; 0033; 0052); PNG media_image1.png 660 832 media_image1.png Greyscale and a side surface orthogonal to the board side surface (Para 0031 – leadframe mounted to a PCB – it’s obvious that the side surface of the exterior end is perpendicular to PCB side surface/lower side of the exterior end); a semiconductor die (2200) mounted to the die pad (see above) by die attach material (Para 0056 -1900 of Fig. 19); wire bonds (2202) coupling to the semiconductor die to the interior ends of leads of the metal leadframe (Fig. 22 – 2202 couples the die to the interior ends of 1806’s ); and mold compound (Para 0005; 0057 – 2204 of Fig. 22) covering the semiconductor die, the die pad, the wire bonds, the interior ends of the leads, the central portion of the leads, and portions of the exterior ends of the leads to form a semiconductor device package (Para 0026; 0033 & Fig. 22), and the board side surface of the exterior ends and the side surface visible from the mold compound (Fig. 22 – lower surface and side surface of the exterior end is visible from the mold compound 2204), the side surface of the exterior ends and a side surface of the apparatus formed by the mold compound being coplanar (Fig. 22- the side surface of 2204 & exterior end is coplanar - Para 0026). Shibuya does not explicitly disclose having bond pads on a device side surface facing away from the die pad; the wire bonds couple to the semiconductor devices via coupling bond pads; and forming terminals for the semiconductor device package. In an analogous art, Somma discloses having bond pads on a device side surface facing away from the die pad (Para 0036; 0061 bond pads); the wire bonds couple to the semiconductor devices via coupling bond pads (Para 0036 and 0050; 0061); and forming terminals for the semiconductor device package (Para 0007 -0008; terminals). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Shibuya’s apparatus by having Somma’s disclosure in order to provide connection points for electrical signals, power and ground between a die and other components. With respect to claim 2, Shibuya discloses wherein the interior ends of the leads have a board side surface exposed from the mold compound (Para 0026-0028 and 0032-0033). With respect to claim 3, Shibuya discloses wherein the central portion of the leads have the partial thickness that is one-half the full thickness of the metal leadframe (Para 0042 – recess in leadframe can be half the thickness of the leadframe). With respect to claim 4, Shibuya discloses wherein the central portion of the leads have the partial thickness that is less than one-half of the full thickness of the metal leadframe (Para 0042 – recess in leadframe can be less than half the thickness of the leadframe). With respect to claim 5, Shibuya discloses wherein the semiconductor device package is a leaded semiconductor device package and the leads extend beyond the semiconductor device package (Para 0002; and 0055-0056). With respect to claim 6, Shibuya discloses wherein the die pad has a board side surface exposed from the mold compound (Para 0028; and 0036-0037). With respect to claim 7, Shibuya discloses wherein the apparatus is a quad flat no-lead (QFN) semiconductor device package (Para 0002; and 0031; QFN). With respect to claim 12, Shibuya discloses wherein the metal leadframe is a copper leadframe (Para 0004; 0031; 0038; 0054 – copper leadframe). With respect to claim 13, Shibuya discloses wherein the metal leadframe is a copper leadframe, an Alloy 42 leadframe, a steel leadframe or a stainless steel leadframe (Para 0004; 0031; 0038; 0054 – copper leadframe). Claims 8-11, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shibuya/Somma in view of Chien-Hung et al. (US 2003/0006055, hereinafter Chien). With respect to claim 8, Shibuya/Somma does not explicitly disclose wherein the apparatus is a small outline no-lead (SON) semiconductor device package. In an analogous art, Chien discloses wherein the apparatus is a small outline no-lead (SON) semiconductor device package (Para 0001). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Shibuya/Somma’s apparatus by having Chien’s disclosure in order to miniaturize the size of a semiconductor device to provide a thin profile of the device. With respect to claim 9, Shibuya/Somma does not explicitly disclose wherein the full thickness of the metal leadframe is between 0.2-0.5 millimeters. In an analogous art, Chien discloses wherein the full thickness of the metal leadframe is between 0.2-0.5 millimeters (Para 0024; 0.2mm). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Shibuya/Somma’s apparatus by having Chien’s disclosure in order to miniaturize the size of a semiconductor device to provide a thin profile of the device. With respect to claim 10, Shibuya/Somma does not explicitly disclose wherein the central portion of the leads has a curved surface. In an analogous art, Chien discloses wherein the central portion of the leads has a curved surface (central portion of 240 of Fig. 4 is curved). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Shibuya/Somma’s apparatus by having Chien’s disclosure in order to accommodate different components of a semiconductor device to minimize the size of the device. With respect to claim 11, Shibuya/Somma does not explicitly disclose wherein the leads are partially etched or stamped. In an analogous art, Chien discloses wherein the leads are partially etched or stamped (Para 0024 – partially etched). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Shibuya/Somma’s apparatus by having Chien’s disclosure in order to accommodate different components of a semiconductor device to minimize the size of the device. With respect to claim 14, Shibuya/Somma does not explicitly disclose wherein the wire bonds are formed from bond wires of gold, aluminum, silver, copper, or palladium coated copper. In an analogous art, Chien discloses wherein the wire bonds are formed from bond wires of gold, aluminum, silver, copper, or palladium coated copper (Para 0021; gold wire). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Shibuya/Somma’s apparatus by having Chien’s disclosure in order to improve electrical conductivity and reliability of a semiconductor device. With respect to claim 20, Shibuya discloses an apparatus (Fig. 22), comprising: a leadframe (Para 0004; 0031; 0038; ; 0054 – leadframe strip 1800) having a die pad (1804) in a central portion (1804 is in the central portion of the leadframe), and having leads (1806) spaced from the die pad (1806’s are spaced apart from 1804), the leadframe having a full thickness (see below) and a partial thickness that is less than the full thickness (see below), the lead comprising: interior end having the full thickness spaced from the die pad (see below); a central portion having the partial thickness connected to the interior end and extending away from the die pad (see below); and an exterior end connected to the central portion and position away from the die pad (see below); PNG media_image1.png 660 832 media_image1.png Greyscale die attach material (Para 0056 -1900 of Fig. 19) over the die pad; a semiconductor die (2200) mounted to the die pad using the die attach material (see above), the semiconductor die having bond pads on a device side surface facing away from the die pad; wire bonds (2202) coupling to the semiconductor die to interior ends of the leads of the copper leadframe (Fig. 22 – 2202 couples the die to the interior ends of 1806’s); and mold compound (Para 0005; 0057 – 2204 of Fig. 22) covering the semiconductor die, the wire bonds, portions of the interior ends of the leads, and portions of the exterior ends of the leads to form a semiconductor device package (Para 0026; 0033 & Fig. 22), and a board side surface and a side surface orthogonal to the board side surface (Para 0031; 0033; 0052 – leadframe mounted to a PCB – it’s obvious that the side surface of the exterior end is perpendicular to PCB side surface/lower side of the exterior end) of the exterior ends of the leads visible from the mold compound (Para 0026). Shibuya does not explicitly disclose having bond pads on a device side surface facing away from the die pad; the wire bonds couple to the semiconductor devices via coupling bond pads; and forming surface mount terminals of the semiconductor device package due to the visible exterior ends of the leads. In an analogous art, Somma discloses having bond pads on a device side surface facing away from the die pad (Para 0036; 0061 bond pads); the wire bonds couple to the semiconductor devices via coupling bond pads (Para 0036 and 0050; 0061); and forming surface mount terminals of the semiconductor device package due to the visible exterior ends of the leads (Para 0007 -0008; terminals). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Shibuya’s apparatus by having Somma’s disclosure in order to provide connection points for electrical signals, power and ground between a die and other components. Shibuya/Somma does not explicitly disclose that the wire bonds comprising bond wires of gold, silver, aluminum, copper, or palladium coated copper. In an analogous art, Chien discloses that the wire bonds comprising bond wires of gold, silver, aluminum, copper, or palladium coated copper (Para 0021; gold wire). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Shibuya/Somma’s apparatus by having Chien’s disclosure in order to improve electrical conductivity and reliability of a semiconductor device. Response to Arguments Applicant's arguments filed 02/25/2026 have been considered, however they are not persuasive. Applicant argues that prior art does not explicitly disclose the amended limitations of claim 1. Examiner respectfully disagrees because Shibuya discloses an exterior end (see below) having the full thickness extending from the central portion and away from the die pad (see below – exterior end has the full thickness and extends from the central portion away from 1804), the exterior end having a board side surface (Para 0031; 0033; 0052); PNG media_image1.png 660 832 media_image1.png Greyscale and a side surface orthogonal to the board side surface (Para 0031 – leadframe mounted to a PCB – it’s obvious that the side surface of the exterior end is perpendicular to PCB side surface/lower side of the exterior end); a semiconductor die (2200) mounted to the die pad (see above) by die attach material (Para 0056 -1900 of Fig. 19); wire bonds (2202) coupling to the semiconductor die to the interior ends of leads of the metal leadframe (Fig. 22 – 2202 couples the die to the interior ends of 1806’s ); and mold compound (Para 0005; 0057 – 2204 of Fig. 22) covering the semiconductor die, the die pad, the wire bonds, the interior ends of the leads, the central portion of the leads, and portions of the exterior ends of the leads to form a semiconductor device package (Para 0026; 0033 & Fig. 22), and the board side surface of the exterior ends and the side surface visible from the mold compound (Fig. 22 – lower surface and side surface of the exterior end is visible from the mold compound 2204), the side surface of the exterior ends and a side surface of the apparatus formed by the mold compound being coplanar (Fig. 22- the side surface of 2204 & exterior end is coplanar - Para 0026). Applicant further argues that prior art does not explicitly disclose the amended limitations of claim 20. Examiner respectfully disagrees because Shibuya discloses an apparatus (Fig. 22), comprising: a leadframe (Para 0004; 0031; 0038; ; 0054 – leadframe strip 1800) having a die pad (1804) in a central portion (1804 is in the central portion of the leadframe), and having leads (1806) spaced from the die pad (1806’s are spaced apart from 1804), the leadframe having a full thickness (see below) and a partial thickness that is less than the full thickness (see below), the lead comprising: interior end having the full thickness spaced from the die pad (see below); a central portion having the partial thickness connected to the interior end and extending away from the die pad (see below); and an exterior end connected to the central portion and position away from the die pad (see below); PNG media_image1.png 660 832 media_image1.png Greyscale and mold compound (Para 0005; 0057 – 2204 of Fig. 22) covering the semiconductor die, the wire bonds, portions of the interior ends of the leads, and portions of the exterior ends of the leads to form a semiconductor device package (Para 0026; 0033 & Fig. 22), and a board side surface and a side surface orthogonal to the board side surface (Para 0031; 0033; 0052 – leadframe mounted to a PCB – it’s obvious that the side surface of the exterior end is perpendicular to PCB side surface/lower side of the exterior end) of the exterior ends of the leads visible from the mold compound (Para 0026). Therefore, the rejection has been maintained. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M CHOUDHRY/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jan 31, 2023
Application Filed
Nov 28, 2025
Non-Final Rejection mailed — §103
Feb 25, 2026
Response Filed
May 29, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
94%
With Interview (+11.9%)
2y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 702 resolved cases by this examiner. Grant probability derived from career allowance rate.

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