DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention II in the reply filed on 7/16/2025 is acknowledged. The traversal is on the ground(s) that there is not a search burden since the claims are a device and a method of making the device.
This is not found persuasive because there is a serious search and/or examination burden due to at least the inventions having acquired a separate status in the art in view of their different classification and the inventions requiring a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search queries). The requirement is still deemed proper and is therefore made FINAL.
Claims 1-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 7/16/2025. The examiner notes the typographical error in the grouping of claims of the restriction requirement mailed 5/16/2025. Specifically, claim 12 is included in Invention II and not included in Invention I, as outlined in the restriction requirement. Claim 12 is not considered withdrawn because it is clearly drawn to the carrier structure of Invention II and the claim from which 13-20 depend.
The examiner additionally notes what appears to be a typographical error in Applicant's election, where Applicant further asserts "claims 10-13 are dependent on claim 1,” in association with arguments against the restriction requirement. The examiner attempted to contact Applicant’s representative on 8/15/2025 to clarify the remarks, however no return phone call was received.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 12 and 16, the limitation “and/or” renders the claim indefinite because it is not clear if the claim requires “and” or if it requires “or.”
Regarding claim 13, the limitations “each first internal interconnection line,” and “any two adjacent first internal interconnection lines,” are unclear as to how they are related to the “at least one first internal interconnection line,” as previously recited because the limitations do not have proper antecedent basis. It is additionally unclear as to if the plural recitation of “any two adjacent first internal interconnection lines” is intended to further specify plural first internal interconnection lines or if the claim merely requires “at least one.”
Regarding claim 14, the limitation “each fine line interconnection layer” is unclear as to how they are related to the “at least one fine line interconnection layer,” as previously recited because the limitation does not have proper antecedent basis.
Regarding claim 14, the limitations “a second insulating material” and “at least one second internal interconnection line,” are unclear because a first insulating material and a first internal interconnection line is not recited in claim 12 from the claim depends.
Regarding claim 14, the limitations “each second internal interconnection line” and “any two adjacent second internal interconnection lines,” are unclear as to how they are related to the “at least one second internal interconnection line,” as previously recited because the limitation does not have proper antecedent basis. It is additionally unclear as to if the plural recitation of “any two adjacent second internal interconnection lines” is intended to further specify plural second internal interconnection lines or if the claim merely requires “at least one.”
Regarding claim 15, the limitations “each build-up layer,” “the build-up layer adjacent to the core layer,” and “the outermost build-up layer,” are unclear as to how they are related to the “at least one build-up layer,” as previously recited because the limitations do not have proper antecedent basis.
Regarding claim 15, the limitations “a fourth insulating material” and “at least one third internal interconnection line,” are unclear because a first or second insulating material and a first or second internal interconnection line is not recited in claim 12 from the claim depends.
Regarding claim 15, the limitations “at least parts of the third internal interconnection lines” and “at least parts of the third internal interconnection lines of the outermost build-up layer” are unclear as to how they are related to the “at least one third internal interconnection line,” as previously recited because the limitation does not have proper antecedent basis. It is additionally unclear as to if the plural recitation of “third internal interconnection lines” is intended to further specify plural third internal interconnection lines or if the claim merely requires “at least one.”
Regarding claim 16, the limitation “is consistent” is a relative term which renders the claim indefinite because the term is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Regarding claim 16, the limitation “that of the second insulating material,” is unclear as to what “that” refers to.
Regarding claim 16, the limitation “the fine line interconnection layer” is unclear as to how iot is related to the “at least one fine line interconnection layer,” as previously recited because the limitation does not have proper antecedent basis. It is additionally unclear as to if the singular recitation is intended to further specify a single element or if the claim still requires “at least one.”
Regarding claim 16, the limitation “the third insulating material is an insulating material whose thermal expansion coefficient is consistent with that of the second insulating material of the fine line interconnection layer and/or the fourth insulating material of the build-up layer; or, the third insulating material is an insulating material whose thermal expansion coefficient is adjustable; and preferably, the thermal expansion coefficient of the third insulating material is between 2*10-6/°C and 20*10-6/°C or is adjustable to be between 2*10-6/°C and 20*10-6/°C,” is unclear what is required of the alternative in the instance of “or” of line 5. It is further unclear as to how the adjustability in lines 6-7 is related to the adjustability of line 9. It is further unclear because the phrase "preferably" renders the claim indefinite as to whether the limitations following the phrase are a required part of the claimed invention. See MPEP § 2173.05(d).
Regarding claim 17, the limitation “is determined based on requirements of an application scene to which the prepared carrier structure is applicable, and is preferably set between 50 μm and 1000 μm” is unclear because the claim references features of an undefined “scene” which lies outside the bounds of the claim. Further the phrase "preferably" renders the claim indefinite as to whether the limitations following the phrase are a required part of the claimed invention. See MPEP § 2173.05(d).
Regarding claim 18, the limitations “preferably” and “such as” render the claim indefinite as to whether the limitations following the phrase are a required part of the claimed invention. See MPEP § 2173.05(d).
Regarding claim 18, the limitation “plastic packaging material” (line 4) is unclear as to how it is related to “a plastic packaging material” recited in line 2.
Regarding claim 20, the limitation “the chip” is unclear as to how it is related to “at least one chip” previously recited because the limitation does not have proper antecedent basis. It is additionally unclear as to if the singular recitation is intended to further specify a single element or if the claim still requires “at least one.”
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McLellan (US 2018/0096938; herein “McLellan”).
Regarding claim 12, McLellan discloses in Fig. 3 and related text a carrier structure suitable for chiplet fine lines, comprising:
a pin interconnection layer (e.g. 115/210/205/207, see [0029], [0030]);
at least one fine line interconnection layer (e.g. 110/105/177/180/195, see [0029], [0030]) disposed on a first side of the pin interconnection layer;
a core (65) layer disposed on a side of the at least one fine line interconnection layer away from the pin interconnection layer, wherein a second electrically conductive structure (230, see [0031]) is formed in the core layer, and the core layer is interconnected with the at least one fine line interconnection layer and/or the pin interconnection layer through the second electrically conductive structure; and
at least one build-up layer (e.g. 70/75/80/85/120/125/130/135/140/145/150, see [0029]) disposed on a side of the core layer away from the at least one fine line interconnection layer, wherein the at least one build-up layer is connected with the fine line interconnection layer through the second electrically conductive structure, and BGA openings (opening filled with 45, see [0025]) are formed in an outermost build-up layer.
Regarding claim 13, McLellan further discloses wherein the pin interconnection layer comprises a first insulating material (115, see [0029]) and at least one first internal interconnection line (e.g. 210, see [0030]), each first internal interconnection line has a line width between 2 μm and 200 μm, and any two adjacent first internal interconnection lines have a line spacing therebetween between 2 μm and 200 μm (10 μm/10 μm in low density region 60, see [0033]).
Regarding claim 14, McLellan further discloses wherein each fine line interconnection layer comprises a second insulating material and at least one second internal interconnection line, each second internal interconnection line has a line width between 0.1 μm and 10 μm, and any two adjacent second internal interconnection lines have a line spacing therebetween between 0.1 μm and 10 μm (1 μm/1 μm in high density region 55, see [0033]).
Regarding claim 15, McLellan further discloses wherein each build-up layer comprises a fourth insulating material (70/75/80/85, see [0029]) and at least one third internal interconnection line (120/125/130/135/140/145/150, see [0029]), at least parts of the third internal interconnection lines of the build-up layer adjacent to the core layer are disposed at the second electrically conductive structure (230) of the core layer, and the BGA openings are disposed at contact points of at least parts of the third internal interconnection lines of the outermost build-up layer (see Fig. 3).
Regarding claim 16, McLellan further discloses wherein the core layer (65) comprises a support substrate made of a third insulating material (see [0029]);
the third insulating material is an insulating material whose thermal expansion coefficient is consistent with that of the second insulating material of the fine line interconnection layer and/or the fourth insulating material of the build-up layer (each is polymeric material, see [0029]); or, the third insulating material is an insulating material whose thermal expansion coefficient is adjustable; and
preferably, the thermal expansion coefficient of the third insulating material is between 2*10-6/°C and 20*10-6/°C or is adjustable to be between 2*10-6/°C and 20*10-6/°C.
Regarding claim 17, McLellan further discloses wherein a thickness of the support substrate is determined based on requirements of an application scene to which the prepared carrier structure is applicable (determined for applications such as those disclosed in [0026]), and is preferably set between 50 μm and 1000 μm .
Regarding claim 18, McLellan further discloses wherein the third insulating material (of core 65) is a plastic packaging material such as epoxy resin, ceramics, glass, BT resin, or powder capable of low-temperature sintering (see [0029]); or, the third insulating material is a mixture of plastic packaging material and heat-conducting microspheres, preferably a mixture of epoxy resin and heat-conducting microspheres, and a mass fraction range of the heat-conducting microspheres is preferably 60 w.t%-99 w.t%.
Regarding claim 19, McLellan discloses a fine line chiplet packaging structure, comprising:
the carrier structure according to claim 12 (see rejection of claim 12 above);
at least one chip (25/30, see [0025]) bonded to a second side of the pin interconnection layer of the carrier structure;
a plastic packaging protection layer (227, see [0030]) disposed on the chip; and
BGA balls (45, see [0025]) disposed at the BGA openings.
Regarding claim 20, McLellan further discloses wherein the chip (25/30) is any one of a processor, a memory, a sensor, or a passive device (see [0026]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220415816, US 20210366877, US 20210217707, US 20180350731, US 20120153463, and US 20150245485 are each cited for showing the features of claim 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896 8/19/2025