DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-12 in the reply filed on 18 February 2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al., US PGPUB No. 2020/0134126 A1.
In reference to claim 1, Lu teaches a method of designing an integrated circuit (Figure 13), comprising:
placing a first block (Figure 5, 502a, 504, 506, Figure 6, 600A) including a first function cell array (Figure 5, 502a, Figure 6, 602) into a layout of the integrated circuit (Paragraph [0034] initial integrated circuit layout); and
placing a second block (Figure 5, 502b, 504o, 506o, Figure 6, 600A) including a second function cell array (Figure 5, 502b, Figure 6, 602) into the layout of the integrated circuit (Paragraph [0034] initial integrated circuit layout), such that the second block extends adjacent the first block within the layout (Figure 5, first and second blocks abut each other);
wherein the first block includes first finishing cells that extend along a boundary of the first block (Figure 5, 506, Figure 6, 606b), and the second block includes second finishing cells that extend along a boundary of the second block (Figure 5, 506o, Figure 6, 606a); and wherein at least some of the first finishing cells abut at least some of the second finishing cells within the layout, at a boundary between the first and second blocks (Figure 5, bottom finishing cells of the top block abut top finishing cells of the bottom block).
In reference to claim 2, Lu teaches wherein at least one of the first finishing cells comprises a structure terminating a first configuration of the first function cell array; and wherein at least one of the second finishing cells comprises a structure terminating a second configuration of the second function cell array (Paragraph [0042] outermost strap active regions terminates the active regions).
In reference to claim 3, Lu teaches further comprising changing at least one finishing cell among the first finishing cells and the second finishing cells, at the respective boundary of the first block and the second block (Paragraph [0042] replacing at least some of the inwardly located elongated active regions and abbreviated active regions with a plurality of conductive structures).
In reference to claim 4, Lu teaches wherein said changing at least one finishing cell comprises identifying a finishing cell having a transitional structure, and replacing a finishing cell at a respective boundary with the identified finishing cell (Paragraph [0042] identifying the transition regions, Figure 13, 1304, Paragraph [0056] identify vertical abutments).
In reference to claim 5, Lu teaches wherein said changing at least one finishing cell comprises replacing one of the first finishing cells and one of the second finishing cells, which abut each other at a boundary, with one finishing cell (Figure 8b, replacing abutting regions of 806a, 806b with conduction structures 814 in abutment region 816, in particular at the bottom of the cells where the boundary regions of the cell blocks abut one another).
In reference to claim 6, Lu teaches wherein each of the first finishing cells comprises a first region that abuts the first function cell array and has a structure terminating the first configuration, and a second region that abuts the first region and includes a halo region; wherein each of the second finishing cells comprises a third region that abuts the second functional cell array and has a structure terminating the second configuration, and a fourth region that abuts the third region and includes a halo region (Figure 1, 108o showing a halo region between terminating structure 106 of the top cell and 106o of the terminating structure of the bottom cell).
In reference to claim 7, Lu teaches wherein the first function cell array comprises function cells aligned to a plurality of rows extending in a first direction; and wherein the first finishing cells include a finishing cell having a height corresponding to two or more of the plurality of rows (Figure 6B showing the finishing cell having a height of 5 rows).
In reference to claim 8, Lu teaches wherein the first block comprises a plurality of first buffer cells surrounding the first finishing cells; and wherein the second block comprises a plurality of second buffer cells surrounding the second finishing cells (Paragraph [0024] halo 108o can be empty or include dummy devices which would be considered buffer cells).
In reference to claim 9, Lu teaches wherein the first configuration comprises a gate electrode pitch, a wiring pitch, and a cell height in the first function cell array; and wherein the second configuration comprises a gate electrode pitch, a wiring pitch, and a cell height in the second function cell array (Paragraph [0058]).
In reference to claim 10, Lu teaches placing third finishing cells at a boundary of the integrated circuit; and placing fourth finishing cells between the first block and the second block, wherein the third finishing cells have a structure terminating a first configuration of the first function cell array or a second configuration of the second function cell array; and wherein the fourth finishing cells have a transitional structure between the first configuration and the second configuration (Figure 8B, 814, 816, Paragraph [0042] termination structures on top and transitional structures at bottom as shown in Figure 12B, 1214a, 1214b, 1216, Paragraph [0053] transition region 1216 structures 1214a, 1214b).
In reference to claim 11, Lu teaches wherein said placing the first block comprises removing a plurality of first finishing cells surrounding the first function cell array; and wherein said placing the second block comprises removing a plurality of second finishing cells surrounding the second function cell array (Paragraph [0042] replacing at least some of the inwardly located elongated active regions and abbreviated active regions with a plurality of conductive structures and Paragraph [0053] replacing at least some of the inwardly located elongated active regions and abbreviated active regions with a plurality of conductive structures).
In reference to claim 12, Lu teaches generating data defining the first block and the second block, which have been placed; fabricating at least one mask based on the data; and manufacturing the integrated circuit using the at least one mask (Figure 15).
Conclusion
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/B.B/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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