Detailed Action
This office action is in response to the request for continued examination filed on March 23rd, 2026. Claims 14-16 and 18-24 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 23rd, 2026, has been entered.
Response to Arguments
Applicant's arguments filed March 23rd, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 6-8, “Remarks”) that Reza and Chowdhury fail to disclose feature (a) wherein the n-type doped layer is directly disposed at a boundary of the two-dimensional gas area. Applicant notes that “the boundary of the two-dimensional electron gas region” refers to the position in the channel layer where the electron concentration of the two-dimensional electron gas region approaches zero.
However, as seen below, Claims 14 and 22 no longer rely on Chowdhury and are instead rejected by a new interpretation of Reza. Utilizing applicant’s definition above, the placement of Reza’s n-type doped layer (22) anywhere within the channel layer (20) below the two-dimensional gas area (21) can be considered to have been placed where the electron concentration approaches zero and therefore considered to have been placed directly at a boundary of the two-dimensional gas area. Applicant does not clearly define the term “approaches zero” and it has been interpreted as generally decreasing towards zero.
Therefore, applicant’s arguments are not persuasive.
Applicant argues (pgs. 8-10) that Reza and the other cited references fail to teach the limitations presented in amended Claims 14 and 22.
However, as seen below, Claims 14 and 22 are now rejected by the combination of Reza, Lee, and Teo.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 14-16, 18-20, and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Reza et al. (9,231,064 B1; hereinafter Reza) in view of Lee (2017/0330940 A1; hereinafter Lee) and Teo et al (2018/0145163 A1; hereinafter Teo).
Regarding Claim 14, Reza (fig. 1) teaches a semiconductor field-effect transistor (Col. 2, Lines 56-58; 10) comprising:
a channel layer (Col. 2, Lines 65-66; 20);
a barrier layer (Col. 3, Lines 3-5; 24) disposed on the channel layer (20);
a gate (Col. 3, Line 33; 32) disposed on the barrier layer (24); and
a source (Col. 3, Lines 31-32; 28) and a drain (Col. 3, Lines 31-32; 30) disposed near two ends (left and right end of 32, see fig. 1) of the gate (32), respectively;
a passivation layer (Col. 3, Line 30; 26) disposed on the barrier layer (24), and the passivation layer covering at least part of upper surfaces of the source, the gate and the drain; wherein
the channel layer (20) and the barrier layer (24) comprises different materials (Col. 2; Lines 65-66; 20 is undoped GaN) (Col. 3, Lines 3-5; 24 is undoped AlGaN), and the channel layer (20) is provided with a two-dimensional electron gas (Col. 3, Lines 9-10; 21) area near the barrier layer (24); wherein
the channel layer (20) further comprises an n-type doped layer (Col. 3, Lines 1-3; 22) directly disposed at a boundary (22 is directly disposed against 21 as it decreases through channel 20) of the two-dimensional electron gas area (21); wherein
the n-type doped layer is separated from a junction of the channel layer and the barrier layer by 60 to 100 angstroms, and
the n-type doped layer comprises a high concentration electron group with an electron concentration of 1.5*1019 to 3*1019 ns*cm-3.
Reza doesn’t explicitly teach that the passivation layer covering at least part of upper surfaces of the source, the gate and the drain.
However, Lee (fig. 6) teaches that the passivation layer ([0048], 110, [0052], 120) covering at least part of upper surfaces of the source ([0048], 106), the gate ([0052], 118) and the drain ([0048], 108). Lee also teaches that the passivation both protects the top surfaces of the source and drain ([0048]) and enhance reliability of the HEMT ([0052]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor field-effect transistor of Reza to include the passivation layers of Lee to protect top surfaces of components and enhance reliability.
Reza doesn’t explicitly teach that the n-type doped layer is separated from a junction of the channel layer and the barrier layer by 60 to 100 angstroms, and the n-type doped layer comprises a high concentration electron group with an electron concentration of 1.5*1019 to 3*1019 ns*cm-3.
However, Teo (fig. 1B) teaches that the n-type doped layer ([0032], 13) is separated from a junction of the channel layer ([0034], 14) and the barrier layer ([0035], 15) by 60 to 100 angstroms ([0034], channel 14 may be 100 angstroms thick and 13 placed at this boundary is 100 angstroms away from the junction of 14 and 15), and the n-type doped layer (13) comprises a high concentration electron group with an electron concentration of 1.5*1019 to 3*1019 ns*cm-3 ([0032], the concentration of 13 ranges from 1*1012 to 1*1013 ns*cm-2 and 13 may have a width of 1 nm, therefore, the electron concentration ranges from 1*1019 to 1*1020 ns*cm-3). Teo also teaches that these values improve device linearity ([0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor field-effect transistor of Reza to include the concentration and placement of the n-type doped layer of Teo to improve linearity.
Regarding Claim 15, Reza (fig. 1) teaches the semiconductor field-effect transistor according to claim 14, the n-type doped layer (22) comprises a silicon dopant (Col. 3, Line 2).
Regarding Claim 16, Teo (fig. 1B) teaches the semiconductor field-effect transistor according to claim 14, wherein the n-type doped layer (13) has an electron area concentration between 1.5*1012 and 6*1012 ns*cm-2 ([0032], the concentration of 13 ranges from 1*1012 to 1*1013 ns*cm-2).
Regarding Claim 18, Reza (fig. 1) teaches the semiconductor field-effect transistor according to claim 14, wherein the channel layer (20) is formed by unintentionally doped or undoped GaN (Col. 2; Lines 65-66; 20 is undoped GaN), and the barrier layer (24) is formed by unintentionally doped or undoped AlGaN (Col. 3, Lines 3-5; 24 is undoped AlGaN).
Regarding Claim 19, Reza (fig. 1) teaches the semiconductor field-effect transistor according to claim 14, further comprising a buffer layer (Col. 2, Lines 61-62; 14) disposed below the channel layer (20).
Regarding Claim 20, Reza (fig. 1) teaches the semiconductor field-effect transistor according to claim 14, wherein the semiconductor field-effect transistor (10) is a Modulation-Doped Field-Effect Transistor (MODFET), a High Electron Mobility Transistor (HEMT) (Col. 2, Lines 56-58), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Metal-Semiconductor Field-Effect Transistor (MESFET) or a Metal- Insulator-Semiconductor Field-Effect Transistor (MISFET).
Regarding Claim 22, Reza (fig. 1) teaches a method of manufacturing a semiconductor field-effect transistor (Col. 2, Lines 56-58; 10) comprising:
forming a buffer layer (Col. 2, Lines 61-62; 14) on a substrate (Col. 2, Lines 59-60; 12);
forming a channel layer (Col. 2, Lines 65-66; 20) on the buffer layer (14) and
forming an n-type doped layer (Col. 3, Lines 1-3; 22) directly at a boundary (22 is directly disposed against 21 as it decreases through channel 20) of a two-dimensional electron gas area (Col. 3, Lines 9-10; 21) in the channel layer (20);
forming a barrier layer (Col. 3, Lines 3-5; 24) on the channel layer (20);
forming a gate (Col. 3, Line 33; 32) on the barrier layer (24), and
forming a source (Col. 3, Lines 31-32; 28) and a drain (Col. 3, Lines 31-32; 30) near two ends (left and right end of 32, see fig. 1) of the gate electrode (32), respectively;
forming a passivation layer (Col. 3, Line 30; 26) disposed on the barrier layer (24), and the passivation layer covering at least part of upper surfaces of the source, the gate and the drain; wherein
the n-type doped layer is separated from a junction of the channel layer and the barrier layer by 60 to 100 angstroms, and
the n-type doped layer comprises a high concentration electron group with an electron concentration of 1.5*1019 to 3*1019 ns*cm-3 .
Reza doesn’t explicitly teach that the passivation layer covering at least part of upper surfaces of the source, the gate and the drain.
However, Lee (fig. 6) teaches that the passivation layer ([0048], 110, [0052], 120) covering at least part of upper surfaces of the source ([0048], 106), the gate ([0052], 118) and the drain ([0048], 108). Lee also teaches that the passivation both protects the top surfaces of the source and drain ([0048]) and enhance reliability of the HEMT ([0052]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor field-effect transistor of Reza to include the passivation layers of Lee to protect top surfaces of components and enhance reliability.
Reza doesn’t explicitly teach that the n-type doped layer is separated from a junction of the channel layer and the barrier layer by 60 to 100 angstroms, and the n-type doped layer comprises a high concentration electron group with an electron concentration of 1.5*1019 to 3*1019 ns*cm-3.
However, Teo (fig. 1B) teaches that the n-type doped layer ([0032], 13) is separated from a junction of the channel layer ([0034], 14) and the barrier layer ([0035], 15) by 60 to 100 angstroms ([0034], channel 14 may be 100 angstroms thick and 13 placed at this boundary is 100 angstroms away from the junction of 14 and 15), and the n-type doped layer (13) comprises a high concentration electron group with an electron concentration of 1.5*1019 to 3*1019 ns*cm-3 ([0032], the concentration of 13 ranges from 1*1012 to 1*1013 ns*cm-2 and 13 may have a width of 1 nm, therefore, the electron concentration ranges from 1*1019 to 1*1020 ns*cm-2). Teo also teaches that these values improve device linearity ([0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor field-effect transistor of Reza to include the concentration and placement of the n-type doped layer of Teo to improve linearity.
Regarding Claim 23, Reza (fig. 1) teaches the method of manufacturing the semiconductor field-effect transistor according to claim 22, wherein the n-type doped layer (22) is formed by doping a silicon dopant (Col. 3, Lines 14-17).
Regarding Claim 24, Teo (fig. 1B) teaches the method of manufacturing the semiconductor field-effect transistor according to claim 22, wherein the n-type doped layer (13) has an electron area concentration between 1.5*1012 and 6*1012 ns*cm-2 ([0032], the concentration of 13 ranges from 1*1012 to 1*1013 ns*cm-2).
Claim 21 rejected under 35 U.S.C. 103 as being unpatentable over Reza, Lee, and Teo as applied to Claim 14 above, and further in view of Bothe et al. (2022/0376099 A1; hereinafter Bothe).
Regarding Claim 21, Reza doesn’t explicitly teach a power amplifier comprising the semiconductor field-effect transistor according to claim 14. Reza does teach that the semiconductor field-effect transistor is a HEMT (Col. 2, Lines 56-58).
However, Bothe teaches that HEMT has high carrier concentration and high carrier mobility and thus has a very large transconductance ([0005]). Bothe also teaches that HEMT may be advantageously utilized in a power amplifier for the above benefits ([0007]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor field-effect transistor of Reza to include the power amplifier application of Bothe to form a power amplifier with a very large transconductance.
Conclusion
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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