DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/09/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 14, 22-24, 31-34, and 39-41 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Signorini (US 2020/0312781),
Regarding claim 1, Signorini discloses chip scale electronics package comprising: a die substrate (Fig.1A, numerals 137; 131; Fig. 2A, numeral 235) disposed under and attached directly to the die (120) ; (220), the substrate including one or more redistribution layers ([0028]; [0039]), sidewalls of the substrate aligned with sidewalls of the die (Fig.2A), and a length of the die substantially matching a length of the substrate (Fig.2A); a plurality of interconnect members (Fig. 1A, numeral 143; Fig. 3, numeral 343) disposed under and attached to the substrate (Fig.3, numeral 320) configured for connection of the chip scale electronics package to a printed circuit board (396) of a multi-die package (Fig.2J), the plurality of interconnect members (243) electrically connected to the die via (262) the one or more redistribution layers (235) in the substrate; a conductive seal ring (Fig.1C, numeral 139) that extends along an outer boundary of the die (137); and a metal shield (Fig.3, numeral 330) disposed on and extending over a top surface of the die (320), the sidewalls of the die (330) and the sidewalls of the substrate (3310; (337) and connected to ground via at least the conductive seal ring ([0031]; [0059]); the metal shield configured to provide individual shielding of the die without also shielding other dies of the multi-die package (Fig.2J).
Regarding claim 14, Signorini discloses a wireless electronic device comprising: an antenna ([0064]); and a front end module including one or more chip scale electronics packages (Fig.2J), each chip scale electronics package of the one or more chip scale electronics packages including a die (220), a substrate (235) disposed under and attached to the die (220), the substrate including one or more redistribution layers (235) ([0039]), sidewalls of the substrate aligned with sidewalls of the die, and a length of the die substantially matching a length of the substrate (Fig.2A), a plurality of interconnect members (Fig.3, numeral 343) disposed under and attached to the substrate (332); (337), the plurality of interconnect members electrically connected to the die via the one or more redistribution layers in the substrate ([0039]), a conductive seal ring (Fig. 1C, numeral 139), and a metal shield (130); (230); (330) disposed on and extending over a top surface of the die (220) (320), the metal shield in contact with a peripheral boundary of the sidewalls of the die (220; (320), and the sidewalls of the substrate and connected to ground via at least the conductive seal ring and the plurality of interconnect members ([0059]; [0031]), the metal shield configured to shield the die from stray power and electromagnetic radiation to provide individual shielding of the die without also shielding other dies of the front end module (Fig.2J).
Regarding claim 22 and 30, Signorini discloses wherein the die (22) extends along an area that substantially coincides with an area of the substrate (235).
Regarding claim 23 and 31, Signorini discloses wherein the conductive seal ring (Fig.1C, numeral 139) extends along an outer boundary of the substrate (137), the conductive seal ring connected to ground via foundry metal in the substrate and the plurality of interconnect members ([0031]).
Regarding claims 24 and 32, Signorini discloses wherein the metal shield (130) is in contact with a top surface of the die (120) (Fig.1B).
Regarding claims 33 and 39, Signorini discloses wherein the conductive seal ring (239) has a sawn peripheral boundary (Fig. 2G) having been sawn during dicing to separate the chip scale electronics package from a wafer (note; “having been sawn during dicing to separate the chip scale electronics package from a wafer” is a product-by-process limitation.).
Regarding claims 34 and 40, Signorini discloses wherein the metal shield extends over the sawn peripheral boundary (Fig.3, numeral 330).
Regarding claims 35 and 41, Signorini discloses wherein the conductive seal ring (Fig. 1C, numeral 139) extends inward from the metal shield (130).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 27, 28, 36-38 are rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Patten (US 2020/0098698).
Regarding claim 7, Signorini discloses s module for an electronic device comprising: a package substrate (Fig.3, numerals 337, 331; 330); a chip scale electronics package mounted on the package substrate (396), the chip scale electronics package including a die (320), a substrate (337); (331) disposed under and attached to the die (320), the substrate including one or more redistribution layers (235) (Fig.2E), sidewalls of the substrate aligned with sidewalls of the die, and a length of the die substantially matching a length of the substrate (Fig.2E), a plurality of interconnect members (343) disposed under and attached to the substrate, the plurality of interconnect members electrically connected to the die via the one or more redistribution layers in the substrate (331), a conductive seal ring (Fig.1C, numeral 139( and metal shield (130)disposed on and extending over a top surface of the die the sidewalls of the die, and the sidewalls of the substrate and connected to ground via at least the conductive seal ring([0031]; [0059]) the metal shield configured to provide individual shielding of the die without also shielding any other die mounted on the package substrate (Fig.2J)
Signorini does not disclose the chip scale electronics package mounted to the package substrate via the plurality of interconnect members; and additional circuitry, the chip scale electronics package and the additional circuitry disposed on the package substrate.
Patten discloses package substrate (Fig. 7, numeral 702) and the die-level electronics package (712) mounted to the package substrate via the interconnect members (726); and additional circuitry (714), the die-level electronics package (712) and the additional circuitry (714) disposed on the package substrate (702).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Signorini with Patten to have a package substrate and the die-level electronics package mounted to the package substrate via the die-level interconnect members; and additional circuitry, the die-level electronics package and the additional circuitry disposed on the package substrate for the purpose of fabrication wafer level chip scale packages (Patten, Abstract).
Regarding claim 27, Signorini discloses wherein the die (22) extends along an area that substantially coincides with an area of the substrate (235).
Regarding claims 28, Signorini discloses wherein the metal shield (130) is in contact with a top surface of the die (120) (Fig.1B).
Regarding claims 36, Signorini discloses wherein the conductive seal ring (239) has a sawn peripheral boundary (Fig. 2G) having been sawn during dicing to separate the chip scale electronics package from a wafer (note; “having been sawn during dicing to separate the chip scale electronics package from a wafer” is a product-by-process limitation.).
Regarding claim 37, Signorini discloses wherein the metal shield extends over the sawn peripheral boundary (Fig.3, numeral 330).
Regarding claims 38, Signorini discloses wherein the conductive seal ring (Fig. 1C, numeral 139) extends inward from the metal shield (130).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 7, 14, 22-24, 27-28, and 30-41 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/ Primary Examiner, Art Unit 2891
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