Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 11/26/2025 has been entered. Claims 1-3, 5-9, 11-16, and 18-23 remain pending.
Response to Arguments
Applicant's arguments with respect to Claims 1, 7 and 14 have been fully considered but they are not persuasive.
First, Applicant traverses the rejections of Claims 1, 7, and 14, but provides no arguments in support of the traversal. Therefore, Examiner is treating this as a non-traversal.
Regarding Applicant’s amendments, the arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. See the Claim Rejections below for details, which uses a new reference (Jebory) in place of Huegsen.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-23 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 21-23, the claims recite in part “…further comprising a mold between the die and the die-level metal shield, the mold encapsulating the die.” Based on Fig. 2 and Examiner’s interpretation of “the mold encapsulating the die,” Examiner is assuming that the mold layer lies on top of the die in addition to surrounding the sides, and that the shield sits on top of the mold (this is consistent with Fig. 2 and Para. [0039] of the specification, which states “A mold 24 is disposed over the die 21” and “The shield 25 can extend over a top of the mold 24 and die 21”). However, in claim 1, the claim recites that “the die-level metal shield in contact with a peripheral boundary of the die” which Examiner assumes to mean that the shield is contact with the die. Since the metal shield cannot be in contact with the peripheral boundary of the die when a mold layer is placed over the die, Claims 21-23 are inconsistent with the claims they depend on.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US20200312781A1 (Signorini) in view of US20180033737A1 (Kuhlman) and US20130087893A1 (Jebory).
Regarding Claim 1, Signorini discloses an electronics package (Fig. 1A, el. 100, Para. [0027]) for use in a module of an electronic device (Para. [0027]) comprising: a die (Fig. 1A, el. 120, Para. [0027]); a plurality of interconnect members disposed under the die (Fig. 1A, el. 143, Para. [0030]); one or more redistribution layers (Fig. 1A, els. 131 and 132, Para. [0028]) interposed between the die and the plurality of interconnect members (Fig. 1A, Para. [0028]); and a die-level metal shield (Fig. 1A, el. 130, Para. [0031] – the metal shield is die-level as it placed directly around the die) disposed over the die (Para. [0031]), the die-level metal shield in contact with a peripheral boundary of the die (Fig. 1A, Para. [0031]) and configured to shield the die from stray power and electromagnetic radiation (Para. [0031]).
Signorini does not disclose one or more die-level vias that extend through the die and are electrically and thermally connected to one or more of the interconnect members; and does not disclose that the metal shield is connected to ground via the one or more vias and the interconnect members, the one or more die-level vias electrically and thermally connected to the one or more of the interconnect members via the one or more redistribution layers, at least one first die-level via of the one or more die-level vias connects to at least one or more redistribution layers via fab metal connection, and at least one second die-level via of the one or more die-level vias connects directly to the one or more redistributions layers, the at least one second die-level via having a wider profile than the at least one first die-level via.
Kuhlman discloses a die (Fig. 5B, el. 502, Para. [0052]) with one or more die-level vias (Fig. 5B, el. 181, Para. [0052] – although Fig. 5B only shows one via, Para. [0052] discloses that there could be multiple vias) which extend through the die (Fig. 1A, el. 510, Para. [0052]); interconnect members (Fig. 5B, els. 171, 172, and 165, Para. [0052]), where the one or more die-level vias are electrically and thermally connected to one or more of the interconnect members (Para. [0052], where the via is electrically connected to interconnect member 165, and is inherently thermally connected because the via is metal, which conducts heat). Kuhlman also discloses a metal shield (Fig. 5B, el. 151, Para. [0052]) that is connected to ground (Fig. 5B, el. 165, Para. [0052]) via the one or more vias and the interconnect members (Para. [0052]), and that a first die-level via connects to the interconnect member via a fab metal connection (Fig. 5B, el. 143, Para. [0052]).
Jebory discloses a die (Fig. 2, el. 200, Para. [0015]) with die-level vias (Fig. 2, els. 202, 204, and 206, Para. [0015]) that are narrower than a typical die-level via (Para. [0015] which discloses narrower vias than the conventional ones shown in Fig. 1 and described in Para. [0013]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use grounding technique disclosed by Kuhlman, where the die-level via connects the metal shield to ground via a fab metal connection, and use it to ground the metal shield disclosed by Signorini. Doing so would have the benefit of allowing multiple vias connecting the metal shield to ground, improving heat dissipation and grounding. Further, it would have been obvious to use die-level vias of different widths, as disclosed by Jebory. As disclosed by Jebory, exclusively using wider vias limits the number of vias that may be formed in a substrate, which can result in uneven thermal dissipation (Para. [0014]).
Regarding Claim 2, Signorini in view of Kuhlman and Jebory discloses the package of claim 1 further comprising a substrate (Signorini, Para. [0028], which describes a first dielectric layer 129 and two conductive layers 131 and 132 which make up the substrate) interposed between the die and the interconnect members (Signorini, Fig. 1A, Para. [0028]), the substrate including the one or more redistribution layers (Fig. 1A).
Regarding Claim 6, Signorini in view of Kuhlman discloses the package of claim 2, wherein the die extends along an area that substantially coincides with an area of the substrate (see Signorini, Fig. 1A, where the die 120 extends along are of the substrate).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Kuhlman, Jebory and US20220285286A1 (Huesgen).
Regarding Claim 3, Signorini in view of Kulhman and Jebory discloses the package of claim 1.
Signorini in view of Kulhman and Jebory does not disclose that the one or more vias are configured to dissipate heat from the metal shield and the die.
Huesgen discloses a shielded package (Fig. 9, el. 200, Para. [0049]) where one or more vias (Fig. 9, 211, Para. [0049]) are configured to dissipate heat from a metal shield (Fig. 9, el. 210, Para. [0049]) and a die (Fig. 9, el. 204, Para. [0049]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to configure the vias of Signorini in view of Kuhlman to be heat dissipating vias as disclosed by Huesgen for the purpose of providing better heat dissipation (Huesgen, Para. [0031]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Kuhlman, Jebory and US20120270404A1 (Bajaj).
Regarding Claim 5, Signorini in view of Kuhlman and Jebory discloses the package of Claim 1.
Signorini in view of Kuhlman and Jebory does not disclose that the one or more die-level vias taper from a wider end proximate the die-level metal shield to a narrower end proximate the one or more redistribution layers.
Bajaj discloses a die-level via (Fig. 4E, el. 402, Para. [0038]) that tapers from a wider end at the top to a narrower end at the bottom (Fig. 4E, Para. [0038]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to taper the vias according to Bajaj. As disclosed by Bajaj, tapering the vias has the benefit of facilitating attachment of components to each other. In this case, tapering the vias may facilitate attachment of the via to the fab metal block or to the RDL.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Kuhlman, Jebory, and US20110127653A1 (Pagaila).
Regarding Claim 21, Signorini in view of Kuhlman and Jebory discloses the package of Claim 1.
Signorini in view of Kuhlman an Jebory does not disclose a mold between the die and the die-level metal shield, the mold encapsulating the die.
Pagaila discloses an electronics package (Fig. 2, el. 100, Para. [0039]) comprising a die (Fig. 2, el. 204, Para. [0039]), a mold layer (Fig. 2, el. 212, Para. [0040]), and a die-level metal shield (Fig. 2, el. 214, Para. [0040]), the mold layer between the die and the die-level metal shield (Fig. 2).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add a mold layer, as in Pagaila, to the electronics package disclosed by Signorini in view of Kuhlman and Jebory. The addition of a mold layer has the well known benefit of providing protection to the die from stress and environmental contamination.
Claims 7-8 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Kuhlman and Jebory.
Regarding Claim 7, Signorini discloses a module (Fig. 5, el. 502, Para. [0063]) for an electronic device (Fig. 5, el. 500, Para. [0063]) comprising: a package substrate (Fig. 5, Para. [0063], el. 502, which is a motherboard, necessarily has a substrate to mount the various elements on it); an electronics package (Fig. 5, el. 504 or 506, Paras. [0066] and [0067]) mounted on the package substrate (Fig 5), the electronics package including a die (Fig. 1A, el. 120, Para. [0027]), a plurality of interconnect members disposed under the die (Fig. 1A, el. 143, Para. [0030]), one or more redistribution layers (Fig. 1A, els. 131 and 132, Para. [0028]) interposed between the die and the plurality of interconnect members (Fig. 1A, Para. [0028]); and a die-level metal shield (Fig. 1A, el. 130, Para. [0031] – the metal shield is die-level as it placed directly around the die) disposed over the die (Para. [0031]), the die-level metal shield in contact with a peripheral boundary of the die (Fig. 1A, Para. [0031]) and configured to shield the die from stray power and electromagnetic radiation (Para. [0031]), the electronics package mounted to the package substrate via the interconnect members; and additional circuitry (Fig. 5, see elements such as DRAM, ROM, etc.), the electronics package and the additional circuitry disposed on the package substrate.
Signorini does not disclose one or more die-level vias that extend through the die and are electrically and thermally connected to one or more of the interconnect members; and does not disclose that the metal shield is connected to ground via the one or more vias and the interconnect members, the one or more die-level vias electrically and thermally connected to the one or more of the interconnect members via the one or more redistribution layers, at least one first die-level via of the one ore more die-level vias connects to at least one ore more redistribution layers via fab metal connection, and at least one second die-level via of the one or more die-level vias connects directly to the one or more redistributions layers, the at least one second die-level via having a wider profile than the at least one first die-level via.
Kuhlman discloses a die (Fig. 5B, el. 502, Para. [0052]) with one or more die-level vias (Fig. 5B, el. 181, Para. [0052] – although Fig. 5B only shows one via, Para. [0052] discloses that there could be multiple vias) which extend through the die (Fig. 1A, el. 510, Para. [0052]); interconnect members (Fig. 5B, els. 171, 172, and 165, Para. [0052]), where the one or more die-level vias are electrically and thermally connected to one or more of the interconnect members (Para. [0052], where the via is electrically connected to interconnect member 165, and is inherently thermally connected because the via is metal, which conducts heat). Kuhlman also discloses a metal shield (Fig. 5B, el. 151, Para. [0052]) that is connected to ground (Fig. 5B, el. 165, Para. [0052]) via the one or more vias and the interconnect members (Para. [0052]), and that a first die-level via connects to the interconnect member via a fab metal connection (Fig. 5B, el. 143, Para. [0052]).
Jebory discloses a die (Fig. 2, el. 200, Para. [0015]) with die-level vias (Fig. 2, els. 202, 204, and 206, Para. [0015]) that are narrower than a typical die-level via (Para. [0015] which discloses narrower vias than the conventional ones shown in Fig. 1 and described in Para. [0013]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use grounding technique disclosed by Kuhlman, where the die-level via connects the metal shield to ground via a fab metal connection, and use it to ground the metal shield disclosed by Signorini. Doing so would have the benefit of allowing multiple vias connecting the metal shield to ground, improving heat dissipation and grounding. Further, it would have been obvious to use die-level vias of different widths, as disclosed by Jebory. As disclosed by Jebory, exclusively using wider vias limits the number of vias that may be formed in a substrate, which can result in uneven thermal dissipation (Para. [0014]).
Regarding Claim 8, Signorini in view of Kuhlman and Jebory discloses the module of claim 7 further comprising a substrate (Signorini, Para. [0028], which describes a first dielectric layer 129 and two conductive layers 131 and 132 which make up the substrate) interposed between the die and the interconnect members (Signorini, Fig. 1A, Para. [0028]), the substrate including the one or more redistribution layers (Fig. 1A).
Regarding Claim 12, Signorini in view of Kuhlman and Jebory discloses the module of claim 7, wherein the die extends along an area that substantially coincides with an area of the substrate (see Signorini, Fig. 1A, where the die 120 extends along are of the substrate).
Regarding Claim 13, Signorini in view of Kuhlman and Jebory discloses the module of claim 7 wherein the die-level metal shield is in contact with a top of the die (Signorini, Fig. 1A, Para. [0031]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Kuhlman, Jebory and Huesgen.
Regarding Claim 9, Signorini in view of Kulhman and Jebory discloses the module of claim 7.
Signorini in view of Kulhman and Jebory does not disclose that the one or more vias are configured to dissipate heat from the metal shield and the die.
Huesgen discloses a shielded package (Fig. 9, el. 200, Para. [0049]) where one or more vias (Fig. 9, 211, Para. [0049]) are configured to dissipate heat from a metal shield (Fig. 9, el. 210, Para. [0049]) and a die (Fig. 9, el. 204, Para. [0049]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to configure the vias of Signorini in view of Kuhlman to be heat dissipating vias as disclosed by Huesgen for the purpose of providing better heat dissipation (Huesgen, Para. [0031]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Kuhlman, Jebory and US20120270404A1 (Bajaj).
Regarding Claim 11, Signorini in view of Kuhlman and Jebory discloses the module of Claim 7.
Signorini in view of Kuhlman and Jebory does not disclose that the one or more die-level vias taper from a wider end proximate the die-level metal shield to a narrower end proximate the one or more redistribution layers.
Bajaj discloses a die-level via (Fig. 4E, el. 402, Para. [0038]) that tapers from a wider end at the top to a narrower end at the bottom (Fig. 4E, Para. [0038]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to taper the vias according to Bajaj. As disclosed by Bajaj, tapering the vias has the benefit of facilitating attachment of components to each other. In this case, tapering the vias may facilitate attachment of the via to the fab metal block or to the RDL.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Kuhlman, Jebory, and Pagaila.
Regarding Claim 21, Signorini in view of Kuhlman and Jebory discloses the module of Claim 7.
Signorini in view of Kuhlman and Jebory does not disclose a mold between the die and the die-level metal shield, the mold encapsulating the die.
Pagaila discloses an electronics package (Fig. 2, el. 100, Para. [0039]) comprising a die (Fig. 2, el. 204, Para. [0039]), a mold layer (Fig. 2, el. 212, Para. [0040]), and a die-level metal shield (Fig. 2, el. 214, Para. [0040]), the mold layer between the die and the die-level metal shield (Fig. 2).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add a mold layer, as in Pagaila, to the electronics package disclosed by Signorini in view of Kuhlman and Jebory. The addition of a mold layer has the well known benefit of providing protection to the die from stress and environmental contamination.
Claims 14-15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Kuhlman and Jebory.
Regarding Claim 14, Signorini discloses a wireless electronic device (Fig. 5, el. 500, Paras. [0063] – [0065]) comprising: an antenna (Fig. 5, Para. [0064]); and a front end module (Fig. 5, el. 502, Para. [0063]) including one or more electronics packages (Fig. 5, els. 504 or 506, Para. [0065 – 0067]), each electronics package including a die (Fig. 1A, el. 120, Para. [0027]), a plurality of interconnect members disposed under the die (Fig. 1A, el. 143, Para. [0030]), ]), one or more redistribution layers (Fig. 1A, els. 131 and 132, Para. [0028]) interposed between the die and the plurality of interconnect members (Fig. 1A, Para. [0028]); and a die-level metal shield (Fig. 1A, el. 130, Para. [0031] – the metal shield is die-level as it placed directly around the die) disposed over the die (Para. [0031]), the die-level metal shield in contact with a peripheral boundary of the die (Fig. 1A, Para. [0031]) and configured to shield the die from stray power and electromagnetic radiation (Para. [0031])
Signorini does not disclose one or more die-level vias that extend through the die and are electrically and thermally connected to one or more of the interconnect members; and does not disclose that the metal shield is connected to ground via the one or more vias and the interconnect members, the one or more die-level vias electrically and thermally connected to the one or more of the interconnect members via the one or more redistribution layers, at least one first die-level via of the one ore more die-level vias connects to at least one ore more redistribution layers via fab metal connection, and at least one second die-level via of the one or more die-level vias connects directly to the one or more redistributions layers, the at least one second die-level via having a wider profile than the at least one first die-level via.
Kuhlman discloses a die (Fig. 5B, el. 502, Para. [0052]) with one or more die-level vias (Fig. 5B, el. 181, Para. [0052] – although Fig. 5B only shows one via, Para. [0052] discloses that there could be multiple vias) which extend through the die (Fig. 1A, el. 510, Para. [0052]); interconnect members (Fig. 5B, els. 171, 172, and 165, Para. [0052]), where the one or more die-level vias are electrically and thermally connected to one or more of the interconnect members (Para. [0052], where the via is electrically connected to interconnect member 165, and is inherently thermally connected because the via is metal, which conducts heat). Kuhlman also discloses a metal shield (Fig. 5B, el. 151, Para. [0052]) that is connected to ground (Fig. 5B, el. 165, Para. [0052]) via the one or more vias and the interconnect members (Para. [0052]), and that a first die-level via connects to the interconnect member via a fab metal connection (Fig. 5B, el. 143, Para. [0052]).
Jebory discloses a die (Fig. 2, el. 200, Para. [0015]) with die-level vias (Fig. 2, els. 202, 204, and 206, Para. [0015]) that are narrower than a typical die-level via (Para. [0015] which discloses narrower vias than the conventional ones shown in Fig. 1 and described in Para. [0013]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use grounding technique disclosed by Kuhlman, where the die-level via connects the metal shield to ground via a fab metal connection, and use it to ground the metal shield disclosed by Signorini. Doing so would have the benefit of allowing multiple vias connecting the metal shield to ground, improving heat dissipation and grounding. Further, it would have been obvious to use die-level vias of different widths, as disclosed by Jebory. As disclosed by Jebory, exclusively using wider vias limits the number of vias that may be formed in a substrate, which can result in uneven thermal dissipation (Para. [0014]).
Regarding Claim 15, Signorini in view of Kuhlman and Jebory discloses the wireless electronic device of claim 14 further comprising a substrate (Signorini, Para. [0028], which describes a first dielectric layer 129 and two conductive layers 131 and 132 which make up the substrate) interposed between the die and the interconnect members (Signorini, Fig. 1A, Para. [0028]), the substrate including the one or more redistribution layers (Fig. 1A).
Regarding Claim 19, Signorini in view of Kuhlman and Jebory discloses the wireless electronic device of claim 14, wherein the die extends along an area that substantially coincides with an area of the substrate (see Signorini, Fig. 1A, where the die 120 extends along are of the substrate).
Regarding Claim 20, Signorini in view of Kuhlman and Jebory discloses the wireless electronic device of claim 14 wherein the die-level metal shield is in contact with a top of the die (Signorini, Fig. 1A, Para. [0031]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Kuhlman, Jebory and Huesgen.
Regarding Claim 16, Signorini in view of Kulhman and Jebory discloses the wireless electronic device of claim 14.
Signorini in view of Kulhman and Jebory does not disclose that the one or more vias are configured to dissipate heat from the metal shield and the die.
Huesgen discloses a shielded package (Fig. 9, el. 200, Para. [0049]) where one or more vias (Fig. 9, 211, Para. [0049]) are configured to dissipate heat from a metal shield (Fig. 9, el. 210, Para. [0049]) and a die (Fig. 9, el. 204, Para. [0049]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to configure the vias of Signorini in view of Kuhlman to be heat dissipating vias as disclosed by Huesgen for the purpose of providing better heat dissipation (Huesgen, Para. [0031]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Kuhlman, Jebory and Bajaj.
Regarding Claim 18, Signorini in view of Kuhlman and Jebory discloses the wireless electronic device of Claim 14.
Signorini in view of Kuhlman and Jebory does not disclose that the one or more die-level vias taper from a wider end proximate the die-level metal shield to a narrower end proximate the one or more redistribution layers.
Bajaj discloses a die-level via (Fig. 4E, el. 402, Para. [0038]) that tapers from a wider end at the top to a narrower end at the bottom (Fig. 4E, Para. [0038]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to taper the vias according to Bajaj. As disclosed by Bajaj, tapering the vias has the benefit of facilitating attachment of components to each other. In this case, tapering the vias may facilitate attachment of the via to the fab metal block or to the RDL.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Signorini in view of Kuhlman, Jebory, and Pagaila.
Regarding Claim 23, Signorini in view of Kuhlman and Jebory discloses the wireless electronic device of claim 14.
Signorini in view of Kuhlman and Jebory does not disclose a mold between the die and the die-level metal shield, the mold encapsulating the die.
Pagaila discloses an electronics package (Fig. 2, el. 100, Para. [0039]) comprising a die (Fig. 2, el. 204, Para. [0039]), a mold layer (Fig. 2, el. 212, Para. [0040]), and a die-level metal shield (Fig. 2, el. 214, Para. [0040]), the mold layer between the die and the die-level metal shield (Fig. 2).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add a mold layer, as in Pagaila, to the electronics package disclosed by Signorini in view of Kuhlman and Jebory. The addition of a mold layer has the well known benefit of providing protection to the die from stress and environmental contamination.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899