Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to application 18/162657 filed on 01/31/23.
Summary of claims
Claims 1-20 are pending.
Claims 1-20 are rejected
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Emre Salman et al. (“Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis”, IEEE Transactions on Computer-Aided Design of Integrated Circuit and System, vol. 26, no. 6, (06-01-2007) pp. 1114-1125).
As to claim 1 the prior art teaches a method for checking a data processing circuit, comprising:
acquiring performance check files of a plurality of timing sequence logic elements ((comprise input ends and latches) in the data processing circuit (see fig 1a, 1b p. 1115 col. 1 lines 9-18);
and obtaining timing sequence information (STA) of the respective timing sequence logic elements (comprise input ends and latches) by simulating (see abstraction) the data processing circuit based on the performance check files of the plurality of timing sequence logic elements (see abstract, fig 1a, fig 1b p1115 col. 1 lines 20 to col. 2 lines 2).
As to claim 2 and 13 the prior art teaches wherein the plurality of timing sequence logic elements comprise: input ends and latches; and each input end is connected to a respective latch (see fig 1a, 1b p1115 col. 2 lines 1-11).
As to claim 3 and 14 the prior art teaches wherein the timing sequence information comprises at least one of: a first setup time and a first hold time of a rising edge of a clock signal when the input end receives a data signal according to the clock signal; a second setup time and a second hold time of a falling edge of the clock signal when the input end receives the data signal according to the clock signal; a third setup time and a third hold time of a rising edge of a sampling signal when the latch samples the data signal according to the sampling signal; and a fourth setup time and a fourth hold time of a falling edge of the sampling signal when the latch samples the data signal according to the sampling signal (see fig 1a, 1b p1115 col. 2 lines 5-32)
As to claim 4 and 15 the prior art teaches wherein after obtaining the timing sequence information of the respective timing sequence logic elements, the method further comprises: displaying identifiers and the timing sequence information of the timing sequence logic elements on a display device (see fig 2a-bp. 1116 col. 1 lines 1-10).
As to claim 5 and 16 the prior art teaches wherein after displaying the identifiers and the timing sequence information of the timing sequence logic elements on the display device, the method further comprises: determining whether the data processing circuit satisfies a preset condition according to the timing sequence information (see fig 2a-b p. 1116 col. 1 lines 1-10).
As to claim 6 and 17 the prior art teaches wherein the preset condition comprises that: the timing sequence information of all input ends of the data processing circuit is within a first preset range (see fig 3a-b p. 1116 col. 2 lines 3-15).
As to claim 7 and 18, the prior art teaches wherein the preset condition further comprises that: the timing sequence information of all latches of the data processing circuit is within a second preset range (see fig 4 a-c p. 1117 col. 1 lines 1-10).
As to claim 8 and 19 the prior art teaches wherein the preset condition further comprises that: in the data processing circuit, a difference between the timing sequence information of all input ends and the timing sequence information of the latches connected to respective input ends is within a third preset range (see fig 4a-c p. 1117 col. 1 lines 10-20).
As to claim 9 the prior art teaches further comprising: performing function check on the data processing circuit in response to determining that the data processing circuit satisfies the preset condition (see fig 5 a-b p. 1117 col. 2 lines 16-30).
As to claim 10 the prior art teaches further comprising: adjusting a delay of the clock signal and/or the data signal in response to determining that the data processing circuit does not satisfy the preset condition, so that the data processing circuit satisfies the preset condition (see fig 5a-b p. 1117 col. 1 lines 25-40).
As to claim 11 the prior art teaches wherein before acquiring the performance check files of the plurality of timing sequence logic elements in the data processing circuit, the method further comprises: generating a netlist of the data processing circuit according to a design database of the data processing circuit; and configuring the performance check files of the respective timing sequence logic elements (see fig 6 p. 1118 col. 1 lines 13-25).
As to claim 12, the prior art teaches n apparatus for checking a data processing circuit, comprising: at least one processor and a memory, wherein the memory stores computer-executable instructions; and the at least one processor is configured to execute the computer-executable instructions stored in the memory to perform operations of:
acquiring performance check files of a plurality of timing sequence logic elements (comprise input ends and latches) in the data processing circuit (see fig 1a, 1b p. 1115 col. 1 lines 9-18);
and obtaining timing sequence information of the respective timing sequence logic elements by simulating the data processing circuit based on the performance check files of the plurality of timing sequence logic elements (see abstract, fig 1a, fig 1b p1115 col. 1 lines 20 to col. 2 lines 2).
As to claim 20 the prior art teaches a non-transitory computer-readable storage medium having stored thereon computer executable instructions that when executed by a processor, implement a method for checking a data processing circuit, the method comprising:
acquiring performance check files of a plurality of timing sequence logic elements ((comprise input ends and latches) in the data processing circuit (see fig 1a, 1b p. 1115 col. 1 lines 9-18);
and obtaining timing sequence information of the respective timing sequence logic elements by simulating the data processing circuit based on the performance check files of the plurality of timing sequence logic elements (see abstract, fig 1a, fig 1b p1115 col. 1 lines 20 to col. 2 lines 2).
Conclusion
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/BINH C TAT/Primary Examiner, Art Unit 2851