Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The terminal disclaimer filed on 10/27/2025 traverses the Double Patenting rejection which is hereby withdrawn.
The amendments to claims 5-6 traverses the 112 rejections which are hereby withdrawn.
Response to Arguments
Applicant's arguments filed 10/27/2025 have been fully considered but they are not persuasive.
On pages 9-12, Applicant alleges that Savignac does not anticipate claim 1 as amended.
Specifically, on page 11, Applicant alleges that Savignac is entirely silent concerning the limitation: “at least one other electrically insulating layer structure arranged between the at least first and second core layer structures, wherein respective electrically conductive layer structures of the at least first and second core layer structures are embedded in the at least one other electrically insulating layer structure.”
The Examiner respectfully disagrees with Applicant’s allegations regarding claim 1. See Savignac, Fig. 6, annotated, below.
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As illustrated above, this construction of Savignac’s structure anticipates each limitation of claim 1. Therefore, the Examiner respectfully submits that Applicant’s allegations are not persuasive.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 7, 9 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Savignac” (US 2007/0195505).
Regarding claim 1, Savignac anticipates 1. A component carrier, comprising: a stack comprising at least first and second core layer structures, each core layer structure comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, wherein the core layer structures are stacked on top of each other in a stacking direction (Fig. 6, [0036], [0041], [0052]; the printed circuit board 1 comprises a stack comprising first and second core layer structures, the uppermost insulating layer and the uppermost line plane 21 is a first core layer, and the third from the top insulating layer and line plane 21 is a second core layer that are stacked on top of each other in a stacking direction),
the stack defining a recess, wherein a first portion of the recess extends completely through the first core layer structure, and a second portion of the recess extends at least partially into the second core layer structure (Fig. 6, [0036], [0041], [0052]; the recess 19 defines a recess having a first portion that extends completely through the first core layer structure, and a second portion that extends at least partially into the second core layer structure);
and at least one other electrically insulating layer structure arranged between the at least first and second core layer structures, wherein respective electrically conductive layer structures of the at least first and second core layer structures are embedded in the at least one other electrically insulating layer structure (Fig. 6, [0036], [0041], [0052]; the second from the top insulating layer arranged between the first and second core layer structures is construed as one other electrically insulating layer structure, such that their respective conductive layers are embedded in the one other electrically insulating layer structure).
Regarding claim 4, Savignac anticipates 4. The component carrier according to claim 1, the stack further comprising: a third core layer structure, wherein the recess extends completely through the third core layer structure (Fig. 6, [0036], [0041], [0052]; the printed circuit board 1 comprises the fourth from the top insulating layer and line plane 21 which is a third core layer structure, wherein the recess 19 extends completely through the third core layer structure).
Regarding claim 7, Savignac anticipates 7. The component carrier according to claim 1, wherein the recess extends completely through the second core layer structure (Fig. 6, [0036], [0041], [0052]; the recess 19 extends completely through the second core layer structure).
Regarding claim 9, Savignac anticipates 9. The component carrier according to claim 1, wherein the recess extends from a first main surface of the stack into the first core layer structure, and a flexible layer is arranged above a second main surface of the stack opposite the first main surface, wherein the flexible layer is arranged in a flexible region (Fig. 6, [0036], [0041], [0052]; the recess 19 extends from a first main surface of the stack into the first core layer structure, and a flexible layer portion of the printed circuit board 1 at the recess 19 is arranged above a second main surface of the stack opposite the first main surface, wherein the flexible layer is arranged in a flexible region).
Regarding claim 12, Savignac anticipates 12. The component carrier according to claim 1, wherein the recess extends from a first main surface of the stack into the first core layer structure, and a further recess extending partially from a second main surface into the stack is arranged opposite the recess, wherein the second main surface is arranged opposite the first main surface (Fig. 6, [0036], [0041], [0052]; the recess 19 extends from a first main surface of the printed circuit board 1 into the first core layer structure, and a further recess extending partially from a second main surface into the printed circuit board 19 is arranged opposite the recess 19, wherein the second main surface is arranged opposite the first main surface).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-3, 5-6, 10-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Savignac in view of “Maruyama” (US 2010/0025093).
Regarding claim 2, Savignac discloses the claimed invention as applied to claim 1, above.
Savignac does not disclose the limitations of claim 2.
Maruyama discloses 2. The component carrier according to claim 1, wherein the first and second core layer structures are connected by lamination (Figs. 1-3, [0098]-[0100]; the multilayered circuit board has core layer structures connected by lamination).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Savignac’s component carrier with Maruyama’s board in order to improve the formability of the insulator layer, as suggested by Maruyama at [0060].
Regarding claim 3, Savignac discloses the claimed invention as applied to claim 1, above.
Savignac does not disclose the limitations of claim 1.
Maruyama discloses 3. The component carrier according to claim 1, wherein the first and second core layer structures have a thickness between 15 μm-2000 μm (Figs. 1-3, [0098]-[0100]; the multilayered circuit board has insulator layers each having a thickness of 40 μm).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Savignac’s component carrier with Maruyama’s board in order to improve the formability of the insulator layer, as suggested by Maruyama at [0060].
Regarding claim 5, Savignac discloses the claimed invention as applied to claim 4, above.
Savignac does not disclose the limitations of claim 5.
Maruyama discloses 5. The component carrier according to claim 4, wherein the first, second and third core layer structures are connected by lamination (Figs. 1-3, [0098]-[0100]; the multilayered circuit board has core layer structures connected by lamination).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Savignac’s component carrier with Maruyama’s board in order to improve the formability of the insulator layer, as suggested by Maruyama at [0060].
Regarding claim 6, Savignac discloses the claimed invention as applied to claim 1, above.
Savignac does not disclose the limitations of claim 6.
Maruyama discloses 6. The component carrier according to claim 1, wherein at least one of the core layer structures comprises a prepreg structure (Figs. 1-3, [0069], [0098]-[0100]; at least one of the core layer structures comprises a prepreg structure).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Savignac’s component carrier with Maruyama’s board in order to improve the formability of the insulator layer, as suggested by Maruyama at [0060].
Regarding claim 10, Savignac discloses the claimed invention as applied to claim 1, above.
Savignac discloses 10. The component carrier according to claim 1, wherein the second core layer structure has a stepped portion (Fig. 6, [0036], [0041], [0052]; the second core layer structure has a stepped portion).
Savignac does not disclose the second core layer comprising pre-impregnated fibers.
Maruyama discloses a core layer comprising pre-impregnated fibers (Figs. 1-3, [0059]-[0060], [0069], [0098]-[0100]; at least one of the core layer structures comprises pre-impregnated fibers).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Savignac’s component carrier with Maruyama’s board in order to improve the formability of the insulator layer, as suggested by Maruyama at [0060].
Regarding claim 11, Savignac in view of Maruyama discloses the claimed invention as applied to claim 10, above.
Savignac discloses 11. The component carrier according to claim 10, wherein at least one further stepped portion is formed on at least one sidewall of the recess (Fig. 6, [0036], [0041], [0052]; a stepped portion is formed on at least one sidewall of the recess 19).
Regarding claim 13, Savignac in view of Maruyama discloses the claimed invention as applied to claim 10, above.
Savignac discloses 13. The component carrier according to claim 10, wherein the recess extends from a first main surface of the stack, and a surface of the stepped portion exposed towards the first main surface is free of indentations (Fig. 6, [0036], [0041], [0052]; the recess 19 extends from a first main surface of the printed circuit board 1, and a surface of the stepped portion exposed towards the first main surface is free of indentations).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Savignac in view of “Onishi” (US 6,191,366).
Regarding claim 8, Savignac discloses the claimed invention as applied to claim 1, above.
Savignac does not disclose the limitations of claim 8.
Onishi discloses 8. The component carrier according to claim 1, wherein the recess is delimited by a protrusion that extends from a surface of the recess (Fig. 7, col. 5, lines 51-55; the recess 3 is delimited by a protrusion that extends from a surface of the recess 3).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Savignac’s component carrier with Onishi’s protrusion in order to increase the adhesion strength, as suggested by Onishi at col. 5, lines 55-57.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Savignac in view of “Dellmann” (US 2009/0133914).
Regarding claim 14, Savignac discloses the claimed invention as applied to claim 9, above.
Savignac discloses 14. The component carrier according to claim 9, wherein the recess extends from a first main surface of the stack into the first core layer structure, and a rigid region comprises a first rigid region arranged adjacent to a first boundary of the flexible region and a second rigid region arranged adjacent to a second boundary of the flexible region opposite the first boundary (Fig. 6, [0036], [0041], [0052]; the recess 19 extends from a first main surface of the stack into the first core layer structure, the portion of the printed circuit board 1 at the bottom of the recess 19 is the flexible region, and the portions of the printed circuit board 1 to the left and right of the flexible region are the respective first and second rigid regions, each of which are arranged adjacent to a respective first and second boundary of the flexible region).
Savignac does not disclose wherein an angle between a portion of the first main surface in the first rigid region and a further portion of the first main surface in the second rigid region is unequal to zero.
Dellmann discloses wherein an angle between a portion of the first main surface in the first rigid region and a further portion of the first main surface in the second rigid region is unequal to zero (Fig. 3B, [0045]; the elevated portions 4 which have tilted surfaces are first and second rigid regions, wherein an angle between a portion of the first main surface in the first rigid region and a further portion of the first main surface in the second rigid region is unequal to zero).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Savignac’s component carrier with Dellmann’s tilted surfaces in order to enable for the transfer of components to a receiver surface having uneven topography, as suggested by Dellmann at [0018].
Regarding claim 15, Savignac in view of Dellmann discloses the claimed invention as applied to claim 14, above.
Savignac does not disclose the limitations of claim 15.
Dellmann discloses 15. The component carrier according to claim 14, wherein the angle between the portion of the first main surface and the further portion of the first main surface is greater than 5 degrees or smaller than −5 degrees (Fig. 3B, [0045]; the angle between the portion of the first main surface and the elevated portions 4 is greater than 5 degrees or smaller than −5 degrees).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Savignac in view of Maruyama and Onishi.
Regarding claim 16, Savignac in view of Maruyama discloses the claimed invention as applied to claim 10, above.
Savignac does not disclose the limitations of claim 16.
Onishi discloses 16. The component carrier according to claim 10, wherein the second core layer structure having the stepped portion comprises a protrusion, wherein the protrusion at least partially delimits the stepped portion (Fig. 7, col. 5, lines 51-55; the recess 3 is delimited by a protrusion that extends from a surface of the recess 3).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Savignac’s component carrier, as modified by Maruyama, with Onishi’s protrusion in order to increase the adhesion strength, as suggested by Onishi at col. 5, lines 55-57.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm.
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/STANLEY TSO/Primary Examiner, Art Unit 2847