DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the objection to the drawings, Applicant’s cancellation of claims 7 and 13, and the amendment to claim 12 has resolved the prior issues of claimed subject matter not being shown in the drawings. Accordingly, the objection to the drawings is withdrawn.
RE: the rejection of claim(s) 3-5 and 12-13 under 35 USC 112(b), Applicant’s amendments of claims 3-5 and 12 have been fully considered and resolve the prior issues of indefiniteness. Accordingly, the prior rejection of claim(s) 3-5 and 12 has been withdrawn. The cancellation of claim 13 has rendered its rejection moot.
RE: the rejection of claims under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot in view of the new grounds of rejection presented herein. These new grounds of rejection were necessitated by Applicant’s amendment to the claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 8-10, and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 includes “a dielectric layer, disposed on a substrate, wherein the substrate comprises a memory region, a periphery region and an edge region, and the periphery region,” “a ground layer, disposed on the dielectric layer, wherein the ground layer has a beveled sidewall in the edge region,” and “a dielectric stacked structure, disposed on the ground layer, wherein the dielectric stacked structure has a beveled sidewall in the edge region” and it is unclear how the ground layer can have a beveled sidewall in the edge region of the substrate when the ground layer is on the dielectric layer, which is on the substrate. Similarly, it is unclear how the dielectric stacked structure can have a beveled sidewall in the edge region of the substrate when the dielectric stacked structure is on the ground layer, which is on the dielectric layer, which is on the substrate. For the purposes of examination, the limitation “wherein the ground layer has a beveled sidewall in the edge region” will be interpreted to mean “wherein the ground layer has a beveled sidewall over the edge region.” Similarly, the limitation “wherein the dielectric stacked structure has a beveled sidewall over the edge region”
Claims 2-6, 8-10, and 12 are rejected due to their dependency from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 8-10, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20240038659A1 (“Park”) in view of US20210408027A1 (“Takaki”).
RE: Claim 1, Park discloses A semiconductor structure for a three-dimensional (3D) memory (100 in FIGs. 1, 2A-2B), comprising:
a dielectric layer (295 in FIG. 2A; 295 is silicon nitride, [0034]; US 20210328141 A1 (“Lin”) discloses silicon nitride is a dielectric material, [0011]; Accordingly, 295 is dielectric), disposed on a substrate, wherein the substrate (201 and/or the lower portions of 201 excluding portions of 205) comprises a memory region (portion of 201 in/under R3; R3 is a memory cell region, [0038], and therefore the portion of 201 in/under R3 is considered a memory region of the substrate), a periphery region (portion of 201 in/under right half part of R2) and an edge region (portion of 201 in/under R1 and left half part of R2), and the periphery region is located between the memory region and the edge region (FIG. 2A shows the portion of 201 in/under the right half part of R2 is between the portion of 201 in/under R3 and the portion of 201 in/under R1, the left half part of R2);
a ground layer (101), disposed on the dielectric layer, wherein the ground layer has a beveled sidewall in the edge region (FIG. 2B shows in region R1, 101 has a beveled sidewall adjacent to MS2a; MS2a has a width that decreases toward 101, [0064]; MS2a has inclined side surfaces, [0064]; As FIG. 1 shows in top view, MS2a have flat side surfaces, MS2a has flat inclined side surfaces facing partially downward; Since MS2a is embedded in 101, 101 would have a flat inclined side surface angled partially upward, corresponding to the claimed beveled sidewall);
a ground via (250 in FIG. 2A), disposed in the dielectric layer, and electrically connected to the substrate (FIG. 2A shows 250 in 295 and electrically connected to 201 by portions of 270, 280);
a dielectric stacked structure (combination of insulating layers 120, 110; insulating layers 120 are disposed between gate electrodes 130, [0053]; 120 are silicon oxide or silicon nitride, [0053]; 110 is silicon oxide or silicon nitride, [0046]; Lin discloses silicon oxide and silicon nitride are dielectric, [0011]; Accordingly, 120, 110 are dielectric and in combination correspond to the claimed dielectric stacked structure as 120 are stacked on 110), disposed on the ground layer, wherein the dielectric stacked structure has a beveled sidewall in the edge region (MS2a has inclined side surfaces, [0064], and are shown in FIG. 2B in direct contact with sidewalls of 120 in R1, [0038]; Accordingly, each sidewall of 120 adjacent to the inclined side surface of MS2a would also be inclined and therefore beveled and would correspond to the claimed beveled sidewall); and
a through via (173 in FIG. 2A), disposed in the dielectric stacked structure (FIG. 2A shows 173 in 110), and connected to the ground layer (FIG. 2A shows 173 is disposed in 190 and connected to 101),
wherein the dielectric stacked structure has a vertical channel hole (hole for CH).
Park does not explicitly disclose the ground via is disposed in the ground layer.
However, Park discloses The ground via 250 may include the same semiconductor material as the plate layer 101, for example, at least one of silicon (Si) or germanium (Ge), and may further include impurities. According to example embodiments, the ground via 250 may not be formed integrally with the plate layer 101, but may include a material, different from that of the plate layer 101, [0037].
Park further discloses The ground via 250 may be connected to the substrate 201 through a ground interconnection structure including conductive plugs and conductive lines, corresponding to the lower interconnection structure. The ground via 250 may form a ground structure, together with the ground interconnection structure, [0036].
In the same field of endeavor, Takaki discloses The ground wiring structure GI includes lower contact plugs 270 and lower wiring lines 280, which are a part of the first wiring structure LI, and further includes an upper via 150 connected to the uppermost third lower wiring line 286 of the lower wiring lines 280, [0063], see FIG. 2A.
Takaki further discloses the via 150 penetrates from an upper portion the second horizontal conductive layer 104, the insulating region IR, the second substrate 101, [0065].
Takaki further discloses the substrate is formed of semiconductor material, [0033].
Takaki further discloses the via 150 includes a barrier layer 152 and a via conductive layer 154, and barrier layer 152 includes a metal nitride, and via conductive layer 154 includes copper, [0066].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the ground via 250 to have a barrier layer and via conductive layer disposed in the plate layer 101 as taught by Takaki in order to increase the conductivity of the ground via 250 and to increase the contact area between the ground via 250 and the plate layer 101, thereby reducing the contact resistance between them. With this modification, the bottom diameter of the bottom portion of the ground via 250, which would still be in layers 294, 295, would remain unchanged.
RE: Claim 2, Park in view of Takaki discloses The semiconductor structure for a 3D memory of claim 1, wherein a material of the through via comprises polysilicon or metal (In Park, 173 has the same material as 170, [0080]; 170 includes 174, [0071]; 174 includes copper, [0074]; Accordingly, 173 includes copper which is metal).
RE: Claim 3, Park in view of Takaki discloses The semiconductor structure for a 3D memory of claim 1, wherein a diameter of the through via is the same as a diameter of the vertical channel hole (In Park Each of the substrate contacts 173 may have a shape corresponding to or the same shape as the channel structure CH, [0080]).
RE: Claim 4, Park in view of Takaki discloses The semiconductor structure for a 3D memory of claim 1, wherein a shortest distance between the through via and the vertical channel hole is 10% or more of a diameter of the vertical channel hole (In Park FIG. 2A shows the shortest distance between 173 and CH is more than 100% of the diameter of CH).
RE: Claim 5, Park in view of Takaki discloses The semiconductor structure for a 3D memory of claim 1, wherein a shortest distance between the through via and the ground via is 10% or more of a diameter of the ground via (In Park FIG. 2A shows the shortest distance between 173 and 250 is more than 100% of the bottom diameter of 250; As modified, the bottom diameter of ground via 250 is unchanged by Takaki).
RE: Claim 6, Park in view of Takaki discloses The semiconductor structure for a 3D memory of claim 1, wherein a bottom surface of the through via is located on a top surface of the ground layer (In Park FIG. 2A shows a bottom surface of 173 is located on a top surface of 101).
RE: Claim 8, Park in view of Takaki discloses The semiconductor structure for a 3D memory of claim 1, wherein a bottom surface of the through via is located on a top surface of the dielectric layer (In Park FIG. 2A shows a bottom surface of 173 is located on a top surface of 295).
RE: Claim 9, Park in view of Takaki discloses The semiconductor structure for a 3D memory of claim 1, wherein a bottom surface of the through via is located at the same level as a bottom surface of the vertical channel hole (In Park 173 is disposed on the same height level as channel structures CH, [0079]; Accordingly, the bottom surface of 173 is located at the same level as the bottom surface of CH).
RE: Claim 10, Park in view of Takaki discloses The semiconductor structure for a 3D memory of claim 1, further comprising a device structure layer (In Park FIG. 2A, the layer including 220 and 270) disposed between the substrate and the dielectric layer (FIG. 2A shows the layer including 220, 270 is disposed between the lower portion of 201 and 295), wherein the ground via is electrically connected to the substrate through the device structure layer (FIG. 2A shows 250 is electrically connected to the lower portion of 201 through impurity regions 205 and/or 270).
RE: Claim 12, Park in view of Takaki discloses The semiconductor structure for a 3D memory of claim 1, wherein the through via is located above the periphery region of the substrate (In Park FIG. 2A shows 173 is located above the portion of 201 in/under the right half part of R2).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899