DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 11/22/2025. Claims 1-15 are pending in this application. Claims 8 & 10-15 are withdrawn.
Claims 1-7 & 9 are being examined in this Office Action.
Claim Objections
2. The claims are objected because of the following reasons:
Re claim 1,
-line 21: after “there is at least one” insert --of--,
-line 21-22: in front of “the second support layer”, delete “at least one”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 2014/0065785) in view of Xu (CN 112185886).
Re claim 1, Yoon teaches, under BRI, Figs. 2 & 11-15, [068-0076, 0094, 0099, 0116], a method for forming a capacitor, comprising:
-providing a substrate (100, 110);
-sequentially forming a first sacrificial layer (120, 121) and a first support layer (130) for covering the substrate (100, 110);
-forming a plurality of first openings (131) penetrating through the first support layer (130), wherein the plurality of first openings (131) expose the first sacrificial layer (121, 120) (Fig. 11);
-sequentially forming a second sacrificial layer (140, 141) and a second support layer (150) for covering a first remaining portion of the first support layer (130) (Fig. 12);
-forming a plurality of through holes (H) which sequentially penetrate through the second support layer (150), the second sacrificial layer (140, 141), the first remaining portion of the first support layer (130), and the first sacrificial layer (121, 120) (Fig. 14);
-forming a plurality of first electrode layers (170), each of the plurality of first electrode layers covering an inner wall of a respective one of the plurality of through holes (H) (Fig. 15);
-after forming the plurality of first electrode layers (170); and
-sequentially forming a dielectric layer (180) and a second electrode layer (190) for covering the plurality of first electrode layers (170), to form the capacitor (Fig. 2),
Wherein there is at least one the first support layer (130, becomes pattern 132) or the at least one the second support layer (150, becomes pattern 152) between any two adjacent the first electrode layers (170) (in either or both vertical & horizontal directions) (Fig. 15).
Note: alternative consideration, 121 & 130 considered as first support layer, 141 & 150 considered as second support layer, 120 as first sacrificial layer & 140 as second sacrificial layer.
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Yoon does not explicitly teach forming a plurality of second openings penetrating through a first remaining portion of the second support layer, wherein the plurality of first openings are located at different positions than the plurality of second openings in a direction parallel to the substrate.
Xu teaches, Figs. 13-24, pages 7, 12 & 15, forming a plurality of second openings (622) penetrating through a first remaining portion of the second support layer (620), wherein the plurality of first openings (750) are located at different positions than the plurality of second openings (622) in a direction parallel to the substrate (100).
As taught by Xu, one of ordinary skill in the art would utilize & modify the above teaching into Yoon to obtain a plurality of second openings penetrating through a first remaining portion of the second support layer, wherein the plurality of first openings are located at different positions than the plurality of second openings in a direction parallel to the substrate as claimed, because it aids in achieving a capacitor array having improved stability.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Xu in combination with Yoon due to above reason.
Re claim 2, in combination cited above, Xu teaches, Figs. 15-20, page 12, wherein before forming the dielectric layer (400) and the second electrode layer (500), the method further comprises:
removing a remaining portion of the second sacrificial layer (620) through the plurality of second openings (622), to expose the plurality of first openings (750); and
after removing the remaining portion of the second sacrificial layer (620), removing a remaining portion of the first sacrificial layer (711) through the plurality of first openings to form a plurality of first voids (211).
Re claim 3, in combination cited above, Xu teaches, Figs. 19-24, page 15, sequentially forming the dielectric layer (400) and the second electrode layer (500) for covering the plurality of first electrode layers (300) comprises:
sequentially forming, in the plurality of through holes, in a radial direction of each of the plurality of through holes, the dielectric layer (400) and the second electrode layer (500) for covering the plurality of first electrode layers (300), and simultaneously, sequentially forming, in the plurality of first voids (211), the dielectric layer (400) and the second electrode layer (500) for covering the plurality of first electrode layers (300), a second remaining portion of the first support layer (210), and a second remaining portion of the second support layer (620);
wherein after forming the second electrode layer (500), the method further comprises:
filling gaps (622) in the second electrode layer with a conductive material (650) to form a conductive structure.
Re claim 4, in combination cited above, Xu teaches, Figs. 13-24, wherein forming the plurality of first electrode layers (300), each of the plurality of first electrode layers (300) covering the inner wall of the respective one of the plurality of through holes comprises:
forming each of the plurality of first electrode layers (300) filling the respective one of the plurality of through holes (750), wherein a width of each of the plurality of first electrode layers (300) is the same as a width of each of the plurality of through holes (750) in the direction parallel to the substrate (100).
Re claim 5, in combination cited above, Xu teaches, Figs. 13-24, page 15, wherein sequentially forming the dielectric layer (400) and the second electrode layer (500) for covering the plurality of first electrode layers (300) comprises:
forming, in the plurality of first voids (211), the dielectric layer (400) for covering the plurality of first electrode layers (300), a third remaining portion of the first support layer (220), and a third remaining portion of the second support layer (620);
forming the second electrode layer (500) for covering the dielectric layer (400);
wherein after forming the second electrode layer (500), the method further comprises:
filling gaps in the second electrode layer with a conductive material (650) to form a conductive structure.
Re claim 6, in combination cited above, Xu teaches, Figs. 3 & 12-13, pages 7 & 10, wherein a plurality of contacts (101, 610) are formed in the substrate (100), and wherein before forming the first sacrificial layer (710), the method further comprises:
forming an etching stop layer (631) for covering the substrate provided with the plurality of contacts (101, 610);
wherein forming the plurality of through holes (750) which sequentially penetrate through the second support layer (621), the second sacrificial layer (741), the first remaining portion of the first support layer (210), and the first sacrificial layer (731) comprises:
forming the plurality of through holes (750) which sequentially penetrate through the second support layer (621), the second sacrificial layer (741), the first remaining portion of the first support layer (210), the first sacrificial layer (711), and the etching stop layer (631), wherein each of the plurality of through holes (750) exposes a respective one of the plurality of contacts (101, 610).
Re claim 7, in combination cited above, Xu teaches, Fig. 14, after the plurality of first electrode layers (300) are formed, each of the plurality of first electrode layers (300) is connected to the respective one of the plurality of contact (101, 610).
Re claim 9, Yoon teaches, Fig. 12, a thickness of the second support layer (150) is greater than a thickness of the first support layer (130).
Response to Arguments
4. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Claim 1 amended with newly added features, rejection & interpretation under Yoon/Xu also changed to meet the claim.
Applicant submits “Yoon fails to disclose there is at least one the first support layer or at least one of the second support layer between any two adjacent the first electrode layers”.
The examiner respectfully disagrees.
According to the claim language, and under BRI & in view of Fig. 15, Yoon does teach there is at least one the first support layer (132) or at least one of the second support layer (152) between any two adjacent the first electrode layers (170) (vertically and/or horizontally). In an alternatively consideration, Yoon teaches at least one the first support layer (121, 132) or at least one of the second support layer (141, 152) between any two adjacent the first electrode layers (170) (vertically and/or horizontally) (Fig. 15).
Hence, given a broadest reasonable interpretation, Yoon in view of Xu teaches the claimed invention. Details included in the above rejection.
Conclusion
5. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 12/6/25
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