DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for the benefit of and priority to U.S. Provisional Application No. 63/306817, filed February 4 2002, entitled ”Common Anode Micro-LED System Architecture”.
Response to Amendment
The present amendment, filed on or after 12/16/2025, has been entered. The Applicant has amended claims 1, 11-12, and 15, canceled claims 10 and 20, and added claims 21-22 as new claims. Accordingly, claims 1-9, 11-19, and 21-22 remain pending in the application.
Applicant’s amendments to the claims 11-12 and the title has overcome each and every objection previously set forth in the Non-Final Office Action mailed on 7/16/ 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, 11, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Valentine (US 2019/0306945 A1) in views of Pan (US 2019/0302917 A1), Yee (US 2020/0251050 A1), and Morris (US 2020/0251049 A1).
Regarding claim 1, Valentine teaches a display device (µLED display panel, Fig. 2 (block diagram), [0025]) comprising:
a first array of micro light-emitting diodes (micro-LEDs) (comprising µLEDs 350 in µLED cells 230, Figs. 2-3, [0025] and [0040]) and including a first common anode for the first array of micro-LEDs ([0040]: “… the μLED 350 may comprise one element of a μLED array with a common anode connected to a positive supply voltage.”); and
pixel drive circuits (circuits in μLED cells 230, Figs. 2 and 3A-B, [0029]) configured to individually address micro-LEDs (µLEDs 350, Fig. 3A, [0029]) of the first array of micro-LEDs (comprising µLEDs 350 in µLED cells 230, Figs. 2 and 3A-B) through cathodes ([0040]: “… the cathode of μLED 350 is connected to n-type transistor T2 which provides a switchable link to a fixed current sink formed by transistor T1 to ground, …”, where transistor T2 is part of the current source 340, see Figs. 3A-B for the current source 340) of the micro-LEDs (µLED 350, Figs. 3A-B: while Figs. 3A-B illustrate the common cathode circuit configuration, the same circuits apply to the case of common anode when the µLED 350 is flipped upside down and the anode is connected to a voltage source, which is the embodiment considered here even though not illustrated in any of the figures), each pixel drive circuit (comprising comparator 310, analog sample and hold module 315, and current source 340, Figs. 3A-B, [0031]-[0032]) of the pixel drive circuits (Figs. 3A-B) including:
an analog current drive circuit (current source 340, Figs. 3A-B) connected to a cathode ([0040]: “… the cathode of μLED 350 is connected to n-type transistor T2 which provides a switchable link to a fixed current sink formed by transistor T1 to ground, …”, not illustrated in figures as mentioned above) of a micro-LED (μLEDs 350, Figs. 3A-B) of the first array of micro-LEDs (comprising µLEDs 350 in µLED cells 230, Figs. 2 and 3A-B);
a storage circuit (analog sample and hold module 315, Figs. 3A-B) for storing pixel data (Vset; [0029]: “The μLED controller 305 receives as an input a data signal (Vset”) 325, …”; and [0030]: “The analog sample and hold 315 stores an analog value corresponding to the value of Vset.”; meaning that the analog sample and hold module 315 stores the pixel data); and
a timing control circuit (comparator 310 and analog sample and hold module 315, Figs. 3A-B) configured to control the analog current drive circuit (current source 340, Figs. 3A-B and 4, [0039]: the comparator 310 generates a PWM signal VμLED which determines the ON-OFF cycles of the current source connected to the μLED 350) based on the pixel data (Vset from the analog sample and hold 315, Figs. 3A-B and 4, [0041]).
Valentine, however, is silent about that
a first array of micro light-emitting diodes (micro-LEDs) are characterized by a pitch less than 20 µm;
the pixel drive circuits are on a backplane wafer; and
the timing control circuit includes
a comparator configured to compare the pixel data with a counter value;
and
a pulse-width-modulation (PWM) latch configured to generate a PWM
signal based on an output of the comparator.
Pan, on the other hand, teaches a display device (integrated display system 500, Fig. 5A, [0185]) with the light emitting elements (LEDs 520, Fig. 5A, [0188]) which may be micro-LEDs ([0055])) wherein
the pixel drive circuits (non-volatile memories/drivers 512, Fig. 5A-B, [0187]) are on a backplane wafer (TFT array backplane 510, Figs. 5A-B, [0187]: “… the TFT array backplane 510 includes a number of pixel circuits.”).
Pan further discloses that having the pixel drive circuits on a backplane separated from the LED array enables the use of standard semiconductor IC (integrated circuit) manufacturing equipment, facilities, and processes, resulting in reduced cost, and backplane integrated LED arrays enables fabrication of ultra-high resolution display devices ([0054]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to put the pixel drive circuitry in the display device of Valentine on a backplane wafer below the first micro-LED array, as disclosed by Pan, to obtain an ultra-high resolution display device and reduce the production costs (Pan, [0054]).
Pan, however, does not teach that
a first array of micro light-emitting diodes (micro-LEDs) are characterized by a pitch less than 20 µm; and
the timing control circuit includes
a comparator configured to compare the pixel data with a counter value;
and
a pulse-width-modulation (PWM) latch configured to generate a PWM
signal based on an output of the comparator.
Yee, on the other hand, teaches row-based brightness uniformity compensation for LED displays (Fig. 6, [0050]; [0038]: LEDs could be microLEDs), wherein to compensate for different brightness levels of individual LEDs across different pixel rows, the timing or calculation of pulse width modulation (PWM) switching events can be varied ([0023]). Yee further teaches that the row-based brightness uniformity compensation for LED display comprises a timing control circuit (Fig. 6, [0050]) which includes
a comparator (comparator circuit 604, Fig. 6, [0050]) configured to compare the pixel data ([0054]: “data bits of the control word from the memory 602”) with a counter value ([0054]: “The comparator circuit 604 receives the count bits from the row driver 614 generated by the counter 610 and receives the data bits of the control word from the memory 602, and compares the count bits with the data bits to generate a comparison result.”);
and
a pulse-width-modulation (PWM) latch (latch circuit 606, Figs. 6 and 12, [0050]) configured to generate a PWM signal (Figs. 10 and 13: the latch circuit (Fig. 10, [0083]: latch circuit 606 comprises the block which includes the NAND gates 1020, 1022, and 1024, and receives the output signal cmpDyn from the comparator (Figs. 10 and 13) to generate a PWM output nDrive (while Yee does not explicitly state that nDrive is a PWM signal, Fig. 13 shows that nDrive signal as the output of the latch circuit has a duty cycle proportional to data value, which is the feature of PWM signals)) based on an output (cmpDyn signal at the dynamic comparison node 1032, Fig. 10, [0081]-[0082]) of the comparator (comparator circuit 604, Fig. 10, [0081]).
Yee further discloses that the LEDs of a display device may emit light at different brightness levels even for the same PWM control signal inputs because of fabrication defects in the LEDs, defects in assembling the LEDs to the display panel, or various other reasons. As such, display devices may lack of uniform brightness across the display panel ([0002]). Yee’s PWM-based timing control circuitry is designed to compensate for the lack of brightness uniformity in LEDs ([0003]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the timing control circuitry in the display device of Valentine in view of Pan with the timing control circuitry taught by Yee to be able to compensate for the brightness variations of the LEDs. Thus, combination of Valentine, Pan, and Yee meets the limitations that the timing control circuit includes
a comparator configured to compare the pixel data with a counter value;
and
a pulse-width-modulation (PWM) latch configured to generate a PWM signal based on an output of the comparator.
Valentine, Pan, and Yee, however, do not teach that
a first array of micro light-emitting diodes (micro-LEDs) are characterized by a pitch
less than 20 µm.
Morris, on the other hand, teaches a micro-LED array (the red-light emitters 512, Fig. 5A, [0133]) characterized by a pitch less than 20 µm ([0133]: about 1.5 μm).
Thus, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use the micro-LED arrays with a pitch less than 20 µm, as disclosed by Morris, in the display device of Valentine in views of Pan and Yee to obtain an ultra-high resolution display device.
Thus, the combination of Valentine, Pan, Yee, and Morris meets all the limitations of claim 1.
Regarding claim 2, while Valentine in view of Pan, Yee and Morris teaches the display device of claim 1,
Valentine is silent about the structure of the micro-LEDs of the first array of micro-LEDs.
Pan, on the other hand, teaches that each micro-LED (LED 662, Fig. 6F, [0246]: Fig. 6A-I show the manufacturing steps of the embodiment in Figs. 5A-B) of the first array of micro-LEDs (array of LEDs 662, Figs. 6F and 6G) includes a mesa structure (LEDs 662 form the mesa structures separated by the gaps 661 which are filled with a dielectric spacer 672, Figs. 6F and 6G, [0249]) that includes:
a reflector layer (conductive layers 504, Fig. 5B, [0200]: “… intermediate conductive layers 504 forms a highly-reflective mirror …”) electrically coupled ([0200]: “… for a corresponding LED 520 bonded with the intermediate conductive layer 504.”) to the cathode ([0191]: Pan discloses that the common electrode is at the top of the array, and therefore the combination of Valentine and Pan as applied to claim 1 above requires the LEDs shown in Fig. 5B to be flipped so that the anode (p-electrode 524) is at the top and cathode (n-electrode 526) is at the bottom. Therefore, conductive layers 504 is electrically coupled to the cathode) of the micro-LED (LED 520, Fig. 5B);
an n-type semiconductor layer (n-electrode 526, Fig. 5B, [0188]: an n-GaN layer; the combination of Valentine and Pan switches the p-electrode 524 and n-electrode 526) coupled to the reflector layer (conductive layers 504, Fig. 5B);
an active region (multiple quantum well (MQW) semiconductor layers 522, Fig. 5B, [0188]) on the n-type semiconductor layer (n-electrode 526, Fig. 5B: the combination of Valentine and Pan switches the p-electrode 524 and n-electrode 526); and
at least a portion of a p-type semiconductor layer (p-electrode 524, Fig. 5B, [0188]: an p-GaN layer; the combination of Valentine and Pan switches the n-electrode 526 and p-electrode 524) on the active region (MQW semiconductor layers 522, Fig. 5B).
Pan further discloses that having the pixel drive circuits on a backplane separated from the LED array enables the use of standard semiconductor IC (integrated circuit) manufacturing equipment, facilities, and processes, resulting in reduced cost, and backplane integrated LED arrays enables fabrication of an ultra-high resolution display devices ([0054]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to put the pixel drive circuits on a backplane separated from the LED array would be motivated to arrange the LED arrays in the display device of Valentine in views of Pan, Yee and Morris such that each micro-LED of the first array of micro-LEDs includes a mesa structure with a reflector layer electrically coupled to the cathode of the micro-LED, an n-type semiconductor layer coupled to the reflector layer, an active region on the n-type semiconductor layer, and at least a portion of a p-type semiconductor layer on the active region, as disclosed by Pan, which would provide the benefit obtaining a ultra-high resolution display device with reduced manufacturing costs (Pan, [0054]) and improved light output efficiency due to inclusion of the reflector layer in the LED structures (Pan, [0200]).
Regarding claim 3, while Valentine in view of Pan, Yee and Morris teaches the display device of claim 2,
Valentine is silent about that the first common anode includes a transparent conductive layer on the p-type semiconductor layer.
Pan, on the other hand, teaches that the first common anode (n-electrode 526, Fig. 5B, [0191]: the combination of Valentine and Pan as applied to claims 1 and 2 above switches the p-electrode 524 and n-electrode 526 (see claim 2 rejection)) includes a transparent conductive layer (transparent conductive layer 530, Fig. 5B, [0191]) on the p-type semiconductor layer (p-electrode 524, [0187]).
Because the light output from the LEDs in the device of Valentine in views of Pan, Yee, and Morris is from the top side in Fig. 5B, it would be obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to make the electrode on the LEDs from a transparent material to improve light output efficiency of the LEDs. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to make electrical connection to the common anode in the display device of Valentine in views of Pan, Yee and Morris from a transparent conductive layer, as disclosed by Pan, to be able to get more LED light out through the conductive layer.
Regarding claim 4, while Valentine in view of Pan, Yee and Morris teaches the display device of claim 2,
Valentine, Pan, and Yee do not disclose that
the first common anode includes a metal layer in regions surrounding mesa structures of the first array of micro-LEDs; and
the first array of micro-LEDs includes a plurality of p-contacts coupling the metal layer to the p-type semiconductor layer at a plurality of locations between the mesa structures of the first array of micro-LEDs.
Morris, on the other hand, teaches a microLED (micro-LEDs 705, Fig. 7B, [0156]) for microLED arrays (light source 510, Fig. 5A) wherein
the first common anode (electrical contact 765, Fig. 7B, [0157]: electrical contact 765 is the anode as it connects to the p-type semiconductor layer 745) includes a metal layer (metal layer 795, Fig. 7B, [0156]) in regions surrounding mesa structures (mesa structure in Fig 7B as defined in [0156]).
Morris further discloses that metal layer 795 may form a mesa reflector that can reflect light emitted by active layer 735 ([0156]), which would prevent the LED light leaking between pixels, and thereby improve resolution. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a metal layer contacting the transparent anode contact (for maximal surface coverage), as disclosed by Morris, on the sidewalls of the micro-LED mesas in the display device of Valentine in views of Pan, Yee and Morris which would provide the benefit of preventing leakage of light between pixels.
Thus, the combination of Valentine, Pan, Yee and Morris meets the limitations of claim 4 such that
the first common anode includes a metal layer in regions surrounding mesa structures of the first array of micro-LEDs; and
the first array of micro-LEDs includes a plurality of p-contacts (the electrical contact between the metal layer and p-type semiconductor layer) coupling the metal layer to the p-type semiconductor layer at a plurality of locations between the mesa structures of the first array of micro-LEDs.
Regarding claim 5, Valentine in view of Pan, Yee, and Morris teaches the display device of claim 4, wherein
the combination of Valentine, Pan, Yee, and Morris further teaches that the metal layer is on sidewalls of the mesa structures of the first array of micro-LEDs (see claim 4 rejection above).
However, Valentine, Pan, and Yee do not teach that the metal layer is between the mesa structures of the first array of micro-LEDs.
Morris, on the other hand teaches that a metal layer (contact layer 790, Fig. 7A, [0152]) that can be extended from the sidewalls of the mesa structure (mesa structure in Fig. 7A as described in [0148]) to facilitate electrical contact ([0152]) to the anodes of the LEDs from the back side.
It would be obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the electrical connections to both anodes and cathodes in the display device of Valentine in view of Pan, Yee, and Morris originate from the backplane pixel circuits located at the back side of the LED array. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention to extent the metal layer in the display device of Valentine in view of Pan, Yee, and Morris to the regions between mesas to make electrical connections to the backplane pixel circuitry.
Thus, the combination of Valentine, Pan, Yee, and Morris meets all the limitations of claim 5 such that
the metal layer is on sidewalls of the mesa structures of the first array of micro-LEDs and regions between the mesa structures of the first array of micro-LEDs.
Regarding claim 6, while Valentine in view of Pan, Yee, and Morris teaches the display device of claim 2,
Valentine is silent about that the active region includes GaN-based semiconductor materials or phosphide-based semiconductor materials.
Pan, on the other hand, teaches a display device (integrated display system 500, Fig. 5A, [0185]) with the light emitting arrays (LED 520, [0188]) which may be micro-LEDs ([0055])) wherein
the active region includes GaN-based semiconductor materials (Figs. 4A-3 and 4A-4, [0131]) or phosphide-based semiconductor materials.
GaN-based semiconductor materials are known in the field for their suitability to make micro-LED arrays as evidenced by Wang (Wang et al, 2020, J. Semicond. 41 041606 DOI 10.1088/1674 4926/41/4/041606). Selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301. See also In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a
known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). Therefore, a micro-LED array with active regions made of GaN-based semiconductor materials in a display device does not provide an inventive concept.
Regarding claim 7, while Valentine in view of Pan, Yee, and Morris teaches the display device of claim 1, wherein
Valentine does not teach a backplane wafer.
Pan, on the other hand, teaches a display device (integrated display system 500, Fig. 5A, [0185]) with light emitting elements (LED 520, [0188]) have their common electrode (n-electrode 526, Fig. 5B) on the top of the array and their control electrodes (p-electrode 524, Fig. 5B) directly bonded to the backplane (TFT Array backplane 510, Fig. 5B).
Pan discloses that having the pixel drive circuits on a backplane separated from the LED array enables the use of standard semiconductor IC (integrated circuit) manufacturing equipment, facilities, and processes, resulting in reduced cost, and backplane integrated LED arrays enables fabrication of an ultra-high resolution display devices ([0054]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to connect the common electrodes and control electrodes of the micro-LED array in the display device of Valentine in views of Pan, Yee, and Morris such that the control electrode (cathode in the device of Valentine in views of Pan, Yee, and Morris) of the micro-LED is bonded to the backplane wafer, to be able to make an ultra-high resolution display device by utilizing the reduced manufacturing costs as disclosed by Pan.
Thus, the combination of Valentine, Pan, Yee, and Morris leads to a display device wherein the cathode of the micro-LED is bonded to the backplane wafer.
Regarding claim 11, while Valentine in view of Pan, Yee, and Morris teaches the display device of claim 1,
Valentine, Pan, and Yee do not teach that the analog current drive circuit is on an indium-gallium-zinc-oxide (IGZO) layer.
Morris, on the other hand, teaches a drive circuitry (drive circuitry of the backplane 1704, Fig. 18, [0199]) wherein the analog drive circuit (thin film transistor layer 1304, [0183]: “The thin-film circuit layer 1304 comprises circuitry for controlling operation of LEDs in the array of LEDs.”) is on an indium-gallium-zinc-oxide (IGZO) layer ([0011]).
Forming control circuits for GaN-based LED arrays on indium-gallium-zinc-oxide (IGZO) layer is a known method in the field of LED displays, as also evidenced by Ahmed (US 2020/0135092 A1, [0020] and [0032]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would use the known technique of forming the analog drive circuit on an indium-gallium-zinc-oxide (IGZO) layer and expect to yield a predictable result of obtaining a robustly functioning backplane analog drive circuit (see MPEP 2143 (I-D)). Thus, the combination of Valentine, Pan, Yee, and Morris meets all the limitations of claim 11.
Regarding claim 13, Valentine in views of Pan, Yee, and Morris teaches the display device of claim 1, wherein
Valentine further teaches that the storage circuit (analog sample and hold module 315, Figs. 3A-B, [0031]-[0032]) for storing pixel data (V-set, Fig. 3A-B) includes an analog data storage circuit (analog sample and hold circuit 315 is an analog date storage circuit), a digital data storage circuit, or a combination.
Regarding claim 14, while Valentine in view of Pan, Yee, and Morris teaches the display device of claim 1,
Valentine does not teach that a pitch of the pixel drive circuits matches the pitch of the first array of micro-LEDs (while the pitch of the pixel drive circuits and the pitch of the first array of micro-LEDs matches in Valentine, the pixel drive circuits are not in the backplane).
Pan, on the other hand, teaches a display device (integrated display system 500, Figs. 5A, [0185]) wherein the pixel drive circuits (non-volatile memories/drivers 512, Figs. 5A-B, [0187]) are on a backplane wafer (TFT array backplane 510, Figs. 5A-B, [0187]). Pan further discloses that a pitch of the pixel drive circuits (non-volatile memories/drivers 512, Figs. 5A-B, [0187]) matches the pitch of the first array of micro-LEDs (LEDs 520, Figs. 5A-B, [0193]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that matching the pitch of the pixel drive circuits and the pitch of the first array of micro-LEDs would help simplifying the manufacturing (integration of the micro-LED array with the pixel driver circuitry) and tiling multiple displays to form larger displays (Pan, [0055]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to make the pitch of the pixel drive circuits match the pitch of the first array of micro-LEDs in the display device of Valentine in views of Pan, Yee, and Morris to obtain the benefit of simplifying the manufacturing and forming a larger display from multiple displays.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Valentine (US 2019/0306945 A1) in views of Pan (US 2019/0302917 A1), Yee (US 2020/0251050 A1), and Morris (US 2020/0251049 A1) as applied to claims 1-7, 11, and 13-14 above, and further in views of Lee (US 2006/0175986 A1) and Devos (US 2005/0017922 A1).
Regarding claim 8, while Valentine in view of Pan, Yee, and Morris teaches the display device of claim 1,
none of Valentine, Pan, Yee, and Morris teaches that
the backplane wafer includes:
a first voltage regulator configured to output a first positive supply voltage to the timing control circuit; and
a second voltage regulator configured to output a second positive supply voltage to the first common anode of the first array of micro-LEDs.
Lee, on the other hand, teaches an LED array driver circuit (LED array driving apparatus, Fig. 2, [0028]) utilizing a timing control circuit (pulse width modulation (PWM) driver 21, Fig. 2, [0028]-[0030]) for controlling the brightness of the LEDs ([0028]: via setting the duty ratio of the PWM driving signal). Lee further discloses that the timing control circuit (PWM driver 21, Fig. 2) includes a voltage regulator (constant voltage regulator 21a, Fig.2, [0030]) to be able convert the supply power (supply power Vcc, Fig. 2, [0030]) of the circuit to an appropriate predetermined constant voltage for setting the PWM signal amplitude ([0030]-[0032]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a voltage regulator, as taught by Lee, in the timing control circuit of the display device of Valentine in view of Pan, Yee, and Morris to set the PMW voltage amplitude VµLED (Valentine, Figs. 3B and 4: VµLED- is positive) to an appropriate predetermined level according to the specifications of the current source 340 and common anode voltage. Thus, the combination of Valentine, Pan, Yee, Morris, and Lee meets the limitation that
the backplane wafer includes:
a first voltage regulator configured to output a first positive supply voltage to the timing control circuit.
Lee, however, does not teach that
the backplane wafer includes:
a second voltage regulator configured to output a second positive supply voltage to the first common anode of the first array of micro-LEDs.
Devos, on the other hand, teaches a driver circuit for common-anode LED array displays (OLED circuit 116, Fig. 2, [0023]) wherein a voltage regulator (voltage regulator 214 supplying positive +VOLED, Fig. 2, [0026]) configured to output a second positive supply voltage (+VOLED) to the first common anode (Fig. 2: +VOLED is connected to the anodes of OLEDs 212a-j ([0023])) of the first array of LEDs (OLED array 210, Fig. 2, [0023]). Devos further discloses that using a voltage regulator connected to the common anode of the LEDs would provide a better control of the light emission from LEDs ([0027]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use a second voltage regulator configured to output a second positive supply voltage to the first common anode of the first array of micro-LEDs in the display device of Valentine in views of Pan, Yee, Morris, and Lee, as taught by Devos, to obtain the benefit of controlling the light emission of the pixels more precisely (Devos, [0027]).
Thus, Valentine, Pan, Yee, Morris, Lee, and Devos meets all the limitations of claim 8.
Regarding claim 9, while Valentine in views of Pan, Yee, Morris, Lee, and Devos teaches the display device of claim 8,
Valentine, Pan, and Yee are silent about two micro-LED arrays each configured to emit light in a different wavelength range.
Morris on the other hand teaches a near-eye display device (NED 500, Fig. 5A, [0133]) wherein the near-eye display device comprises
the first array of micro-LEDs (a panel of red-light emitters 512, Fig. 5A, [0133]) is configured to emit light in a first wavelength range ([0133]: wavelengths corresponding to red color);
the display device (NED 500, Fig. 5A) includes a second array of micro-LEDs (a panel of green light emitters 514, Fig. 5A, [0133]) that is configured to emit light in a second wavelength range ([0133]: wavelengths corresponding to green color).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form a second array of common-anode microLEDs next to the first common-anode array of microLEDs (each array emitting at a different wavelength range) in the display device of Valentine in views of Pan, Yee, Morris, Lee, and Devos, as disclosed by Morris, to be able to make a high-spatial resolution near-eye display device with color(Morris, [0133]). Thus, the combination of Valentine, Pan, Yee, Morris, Lee, and Davos teaches that
the first array of micro-LEDs is configured to emit light in a first wavelength range;
the display device includes a second array of micro-LEDs that includes a second common anode and is configured to emit light in a second wavelength range.
Morris, however, does not teach that
the backplane wafer further includes a third voltage regulator configured to output a third positive supply voltage to the second common anode of the second array of micro-LEDs.
Devos, on the other hand, teaches a larger display device (OLED display 400, Fig. 4, [0036]) formed by tiling several displays (tiles 300a-j, Fig. 4, [0036]), wherein each tile column has its own voltage regulator.
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that LEDs with different emission wavelengths would operate at different voltage and current levels. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a third regulator on the backplane wafer to set the anode voltage level of the second array of micro-LEDs to be able to use the same level of PMW signal for controlling both the first and second array of micro-LEDs.
Thus, the combination of Valentine, Pan, Morris, Lee, and Devos meets all the limitations of claim 9, such that
the first array of micro-LEDs is configured to emit light in a first wavelength range;
the display device includes a second array of micro-LEDs that includes a second common anode and is configured to emit light in a second wavelength range; and
the backplane wafer further includes a third voltage regulator configured to output a third positive supply voltage to the second common anode of the second array of micro-LEDs.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Valentine (US 2019/0306945 A1) in views of Pan (US 2019/0302917 A1), Yee (US 2020/0251050 A1), and Morris (US 2020/0251049 A1) as applied to claims 1-7, 11, and 13-14 above, and further in view of Ahmed (US 2020/0135092 A1).
Regarding claim 12, while Valentine in views of Pan, Yee, and Morris teaches the display device of claim 1,
Valentine, Pan, Yee, and Morris do not teach that the backplane wafer includes a common control circuit shared by two or more micro-LEDs of the first array of micro-LEDs.
Ahmed, on the other hand, teaches a display device (electronic device 100, Fig. 1, [0021]) with a micro-LED array (micro-LED display 102, Fig. 1, [0021]) and backplane driver circuits (in-pixel driver circuits 108, Fig. 1, [0021]), wherein the backplane wafer (substrate 106 and a plurality of transistor-based in-pixel driver circuits 108, Fig. 1, [0023]) includes a common control circuit (circuit 1000, Fig. 10, [0055]) shared by two or more micro-LEDs (micro-LED 1004 and micro-LED 106, Fig 10, [0055]) of the first array of micro-LEDs (micro-LED display 102, Fig. 1).
Ahmed further discloses that using the same circuit to operate the two LEDs in sequence would provide the benefit of reducing the flicker ([0055]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a common control circuit in the display device of Valentine in views of Pan, Yee, and Morris to be shared by two or more micro-LEDs of the first array of micro-LEDs, as disclosed by Ahmed, to minimize the flicker in the display.
Claims 15-16, 18, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Iguchi-513 (US 2019/0385513 A1) in views of Valentine (US 2019/0306945 A1) and Yee (US 2020/0251050 A1).
Regarding claim 15, Iguchi-513 teaches a display device (LED display chip 1, Fig. 1, [0103]) comprising an array of pixels (plurality of pixels 40, Fig. 1, [0104]) characterized by a pitch less than 20 µm (light emitting unit 31, Fig. 3, [0116]: “… each light emitting unit 31 having an area of 10µm x10 µm …”), each pixel (pixels 40 in Fig. 1 which is analogous to light emitting unit 31 in Fig. 3 as evidenced by Fig. 2) of the array of pixels (light emitting array 30, Fig. 3, [0116]) comprising:
a micro light-emitting diode (micro-LED) (light emitting units 31a, Fig. 59, [0098] and [0116]: LED’s are smaller than 10µm x10 µm, and therefore micro-LEDs according to the definition in the current application (see [0054] of the application)); and
a pixel drive circuit (drive circuit 70a, Figs. 59-60, [0405]) electrically connected to the micro-LED (light emitting unit 31a, Fig. 59, [0400]: each light emitting unit 31a is connected to a drive circuit 70a).
wherein anodes (P-side epitaxial layer 54, Fig. 59, [0400]) of micro-LEDs (light emitting unit 31a, Fig. 59) of the array of pixels (pixel 40, Fig. 59) are electrically shorted (Fig. 59, [0400]: P - side epitaxial layers 54 are electrically connected (shorted) with P-side common electrode 38).
Iguchi-513, however, does not teach that
the pixel drive circuit comprises:
an analog current drive circuit connected to a cathode of the micro-LED;
a storage circuit for storing pixel data; and
a timing control circuit configured to control the analog current drive circuit based on the pixel data, the timing control circuit including:
a comparator configured to compare the pixel data with a counter value;
and
a pulse-width-modulation (PWM) latch configured to generate a PWM
signal based on an output of the comparator.
Valentine, on the other hand, teaches a display device (µLED display panel, Fig. 2 (block diagram), [0025]) with an integrated microLED array (µLEDs 350 in µLED cells 230, Figs. 2-3, [0025] and [0040]) and corresponding array of pixel drive circuitry (μLED cells 230 without the μLEDs 350, Figs. 2 and 3A-B, [0029]) wherein
the pixel drive circuit (Figs. 3A-B) comprises:
an analog current drive circuit (current source 340, Figs. 3A-B) connected to a cathode of the micro-LED ([0040]: “… the cathode of μLED 350 is connected to n-type transistor T2 which provides a switchable link to a fixed current sink formed by transistor T1 to ground, …”, not illustrated in figures);
a storage circuit (analog sample and hold module 315, Figs. 3A-B) for storing pixel data (Vset; [0029]: “The μLED controller 305 receives as an input a data signal (CVset”) 325, …”; and [0030]: “The analog sample and hold 315 stores an analog value corresponding to the value of Vset.”; thus, analog sample and hold module 315 stores the pixel data); and
a timing control circuit (comparator 310 and analog sample and hold module 315, Figs 3B) configured to control the analog current drive circuit (current source 340, Figs. 3B and 4, [0039]: the comparator 310 generates a PWM signal VμLED which determines the ON-OFF cycles of the current source connected to the μLED 350) based on the pixel data (Vset from the analog sample and hold 315, Figs. 3B and 4, [0041]).
Valentine further discloses that the pixel drive circuit of Valentine uses a pulse width modulation (PWM) signal to drive an analog current source, and this scheme of pixel drive circuit is specifically designed for precisely controlling the brightness of pixels in microLED arrays ([0018], which are known to have low internal quantum efficiency at low current levels (Fig. 1A, [0019]-[0020]) and need to be operated at an optimum current level J* with PWM to extract light efficiently and to control the brightness precisely ([0019]-[0023]). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that Valentine’s pixel drive circuits also operate at the common-anode configuration ([0040]: “… the μLED 350 may comprise one element of a μLED array with a common anode connected to a positive supply voltage.”), and therefore, can replace the pixel drive circuits of Iguchi-513. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the pixel drive circuits in the display device of Iguchi-513 with the pixel drive circuits taught by Valentine to be able to control the brightness of the pixels in the microLED array precisely and more effectively (Valentine, [0019]-[0023]).
Valentine, however, does not teach that the timing control circuit including:
a comparator configured to compare the pixel data with a counter value;
and
a pulse-width-modulation (PWM) latch configured to generate a PWM
signal based on an output of the comparator.
Yee, on the other hand, teaches row-based brightness uniformity compensation for LED displays (Fig. 6, [0050]; [0038]: LEDs could be microLEDs), wherein to compensate for different brightness levels of individual LEDs across different pixel rows, the timing or calculation of pulse width modulation (PWM) switching events can be varied ([0023]). Yee further teaches that the row-based brightness uniformity compensation for LED display comprises a timing control circuit (Fig. 6, [0050]) which includes
a comparator (comparator circuit 604, Fig. 6, [0050]) configured to compare the pixel data ([0054]: “data bits of the control word from the memory 602”) with a counter value ([0054]: “The comparator circuit 604 receives the count bits from the row driver 614 generated by the counter 610 and receives the data bits of the control word from the memory 602, and compares the count bits with the data bits to generate a comparison result.”);
and
a pulse-width-modulation (PWM) latch (latch circuit 606, Figs. 6 and 12, [0050]) configured to generate a PWM signal (Figs. 10 and 13: the latch circuit (Fig. 10, [0083]: latch circuit 606 comprises the block which the NAND gates 1020, 1022, and 1024, and receives the output signal cmpDyn from the comparator (Figs. 10 and 13) to generate a PWM output nDrive (while Yee does not explicitly state that nDrive is a PWM signal, Fig. 13 shows that nDrive signal as the output of the latch circuit has a duty cycle proportional to data value, which is the feature of PWM signals)) based on an output (cmpDyn signal at the dynamic comparison node 1032, Fig. 10, [0081]-[0082]) of the comparator (comparator circuit 604, Fig. 10, [0081]).
Yee further discloses that the LEDs of a display device may emit light at different brightness levels even for the same PWM control signal inputs because of fabrication defects in the LEDs, defects in assembling the LEDs to the display panel, or various other reasons. As such, display devices may lack of uniform brightness across the display panel ([0002]). Yee’s PWM-based timing control circuitry is designed to compensate for the lack of brightness uniformity in LEDs ([0003]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the timing control circuitry in the display device of Iguchi-513 in view of Valentine with the timing control circuitry taught by Yee to be able to compensate for the brightness variations of the LEDs.
Thus, the combination of Iguchi-513, Valentine, and Yee meets all the limitations of claim 15.
Regarding claim 16, Iguchi-513 in views of Valentine and Yee teaches the display device of claim 15, wherein
Iguchi-513 further teaches that the anodes (P-side epitaxial layer 54, Fig. 59) of the micro-LEDs (light emitting unit 31a, Fig. 59) of the array of pixels (pixels 40 in Fig. 59) are connected to a transparent conductive layer ([0411]: “A transparent conductive film may be stacked on the P-side epitaxial layer 54.”. Furthermore, because the light output of the display device is through the common electrode 38 (see Fig. 59), common electrode 38 has to be transparent to let the light through).
Regarding claim 18, Iguchi-513 in views of Valentine and Yee teaches the display device of claim 15, wherein
Iguchi-513 further teaches that the micro-LED (light emitting units 31a, Fig. 59) includes GaN-based semiconductor materials ([0161]: n- and p-type layers include GaN) or phosphide-based semiconductor materials.
Regarding claim 22, Iguchi-513 in views of Valentine and Yee teaches the display device of claim 15, wherein
Iguchi-513 further teaches that a cathode (N-side individual electrode 44a, Fig. 59, [0402]) of the micro-LED (light emitting units 31a, Fig. 59) is bonded to the pixel drive circuit (IC chip 20a, Fig. 59, [0402]: “The IC chip 20a includes N - side electrodes 47a (first drive electrode ) individually connected to the N - side individual electrodes 44a corresponding to the pixels 40.”).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Iguchi-513 (US 2019/0385513 A1) in views of Valentine (US 2019/0306945 A1) and Yee (US 2020/0251050 A1) as applied to claims 15-16, 18, and 22 above, and further in views of Iguchi-422 (US 2021/0151422 A1).
Regarding claim 17, while Iguchi-513 in views of Valentine and Yee teaches the display device of claim 15,
Iguchi-513, Valentine, and Yee do not teach that the anodes of the micro-LEDs of the array of pixels are connected to a metal layer in regions between the array of pixels.
Iguchi-422, on the other hand, teaches a display device (image display element 200, Fig. 1, [0071]) comprising micro light emitting elements (excitation light emitting element 105, [0072]: light emitting element 105 is a micro-LED (Abstract)) wherein the transparent electrode (transparent electrode 30, Fig. 1, [0072]) for electrical contact to the anodes (P-side layer, Fig. 1, [0069]) is a metal ([0074]: silver nanofiber).
Considering that Iguchi-513 is silent about the material of the transparent electrode (P-side common electrode 38, Fig. 59 of Iguchi-513) connecting the anodes of micro-LEDs, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use silver nanofiber layer, as taught by Iguchi-422, to form the transparent conductive layer (which also covers regions between the array of pixels from top view to electrically short the anodes) in the display device of Iguchi-513 in views of Valentine and Yee, which provides the benefit of good electrical conductivity and optical transparency (Iguchi-422, [0072]).
Thus, the combination of Iguchi-513, Valentine, Yee, and Iguchi-422 meet the limitations of claim 17 such that the anodes of the micro-LEDs of the array of pixels are connected to a metal layer in regions between the array of pixels.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Iguchi-513 (US 2019/0385513 A1) in views of Valentine (US 2019/0306945 A1) and Yee (US 2020/0251050 A1) as applied to claims 15-16, 18, and 22 above, and further in views of Lee (US 2006/0175986 A1) and Devos (US 2005/0017922 A1).
Regarding claim 19, while Iguchi-513 in view of Valentine and Yee teaches the display device of claim 15, Iguchi-513, Valentine, and Yee do not teach
a first voltage regulator configured to output a first positive supply voltage to the timing control circuit; and
a second voltage regulator configured to output a second positive supply voltage to the anodes of the micro-LEDs of the array of pixels.
Lee, on the other hand, teaches an LED array driver circuit (LED array driving apparatus, Fig. 2, [0028]) utilizing a timing control circuit (pulse width modulation (PWM) driver 21, Fig. 2, [0028]-[0030]) for controlling the brightness of the LEDs ([0028]: via setting the duty ratio of the PWM driving signal). Lee further discloses that the timing control circuit (PWM driver 21, Fig. 2) includes a voltage regulator (constant voltage regulator 21a, Fig.2, [0030]) to be able convert the supply power (supply power Vcc, Fig. 2, [0030]) of the circuit to an appropriate predetermined constant voltage for setting the PWM signal amplitude ([0030]-[0032]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a voltage regulator, as taught by Lee, in the timing control circuit of the display device of Iguchi-513 in views of Valentine and Yee to set the PMW voltage amplitude VµLED (Valentine, Figs. 3B and 4: VµLED- is positive) to an appropriate predetermined according to the specifications of the current source 340 and common anode voltage. Thus, the combination of Iguchi-513, Valentine, Yee, and Lee meets the limitation that
a first voltage regulator configured to output a first positive supply voltage to the timing control circuit.
Lee, however, does not teach
a second voltage regulator configured to output a second positive supply voltage to the first common anode of the first array of micro-LEDs.
Devos, on the other hand, teaches a driver circuit for common-anode LED array displays (OLED circuit 116, Fig. 2, para.0023]) wherein a voltage regulator (voltage regulator 214 supplying positive +VOLED, Fig. 2, [0026]) configured to output a second positive supply voltage (+VOLED) to the first common anode (Fig. 2: +VOLED is connected to the anodes of OLEDs 212a-j ([0023])) of the first array of LEDs (OLED array 210, Fig. 2, [0023]). Devos further discloses that using a voltage regulator connected to the common anode of the LEDs would provide better control of the light emission ([0027]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use a second voltage regulator configured to output a second positive supply voltage to the first common anode of the first array of micro-LEDs in the display device of Iguchi-513 in views of Valentine, Yee, and Lee, as taught by Devos, to obtain the benefit of controlling the light emission of the pixels more precisely (Devos, [0027]).
Thus, Iguchi-513, Valentine, Yee, Lee, and Devos meets all the limitations of claim 19.
Claims 21 is rejected under 35 U.S.C. 103 as being unpatentable over Iguchi-513 (US 2019/0385513 A1) in views of Valentine (US 2019/0306945 A1) and Yee (US 2020/0251050 A1) as applied to claims 15-16, 18, and 22 above, and further in view of Pan (US 2019/0302917 A1).
Regarding claim 21, while Iguchi-513 in views of Valentine and Yee teaches the display device of claim 15,
Iguchi-513, Valentine, and Yee do not teach that the micro-LED includes a mesa structure that includes:
a reflector layer electrically coupled to the cathode of the micro-LED;
an n-type semiconductor layer coupled to the reflector layer;
an active region on the n-type semiconductor layer; and
at least a portion of a p-type semiconductor layer on the active region.
Pan, on the other hand, teaches a display device (integrated display system 500, Fig. 5A, [0185]) with the light emitting elements (LEDs 520, Fig. 5A, [0188]) which may be micro-LEDs ([0055])), wherein that each micro-LED (LED 662, Fig. 6F, [0246]: Fig. 6A-I show the manufacturing steps of the embodiment in Figs. 5A-B) includes a mesa structure (LEDs 662 form the mesa structures separated by the gaps 661 which are filled with a dielectric spacer 672, Figs. 6F and 6G, [0249]) that includes:
a reflector layer (conductive layers 504, Fig. 5B, [0200]: “… intermediate conductive layers 504 forms a highly-reflective mirror …”) electrically coupled ([0200]: “… for a corresponding LED 520 bonded with the intermediate conductive layer 504.”) to the cathode ([0191]: Pan discloses that the common electrode is at the top of the array as in the case of Iguchi-513 in views of Valentine and Yee, and therefore the anode of the LEDs shown in Fig. 5B are analogous to the cathode of Iguchi-513 in views of Valentine and Yee) of the micro-LED (LED 520, Fig. 5B);
an n-type semiconductor layer (n-electrode 526, Fig. 5B, [0188]: an n-GaN layer; p-electrode 524 and n-electrode 526 are flipped to associate the display device of Pan with the display device of Iguchi-513 in views of Valentine and Yee) coupled to the reflector layer (conductive layers 504, Fig. 5B);
an active region (multiple quantum well (MQW) semiconductor layers 522, Fig. 5B, [0188]) on the n-type semiconductor layer (n-electrode 526, Fig. 5B: p-electrode 524 and n-electrode 526 are flipped to associate the display device of Pan with the display device of Iguchi-513 in views of Valentine and Yee); and
at least a portion of a p-type semiconductor layer (p-electrode 524, Fig. 5B, [0188]: an p-GaN layer; p-electrode 524 and n-electrode 526 are flipped to associate the display device of Pan with the display device of Iguchi-513 in views of Valentine and Yee) on the active region (MQW semiconductor layers 522, Fig. 5B).
Pan further discloses that having the pixel drive circuits on a backplane separated from the LED array enables the use of standard semiconductor IC (integrated circuit) manufacturing equipment, facilities, and processes, resulting in reduced cost, and backplane integrated LED arrays enables fabrication of an ultra-high resolution display devices ([0054]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to put the pixel drive circuits on a backplane separated from the LED array would be motivated to arrange the LED arrays in the display device of Iguchi-513 in views of Valentine and Yee such that each micro-LED includes a mesa structure with a reflector layer electrically coupled to the cathode of the micro-LED, an n-type semiconductor layer coupled to the reflector layer, an active region on the n-type semiconductor layer, and at least a portion of a p-type semiconductor layer on the active region, as disclosed by Pan, which would provide the benefit obtaining a ultra-high resolution display device with reduced manufacturing costs (Pan, [0054]) and improved light output efficiency due to inclusion of the reflector layer at the bottom of the LED structures (Pan, [0200]).
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 11-12, and 15, canceled claims 10 and 20, and added claims 21-22 as new claims per response dated on 12/16/2025. Applicant's arguments with respect to claims have been fully considered.
Applicant argues in substance:
…, amended independent claim 1 recites "a timing control circuit configured to control the analog current drive circuit based on the pixel data, the timing control circuit including: a comparator configured to compare the pixel data with a counter value; and a pulse-width-modulation (PWM) latch configured to generate a PWM signal based on an output of the comparator" These aspects of amended claim 1 are neither taught nor suggested by the cited references, alone or in combination.
The primary reference, Valentine, discusses PWM control of micro-LEDs, but does not disclose "a comparator configured to compare the pixel data with a counter value" and "a pulse-width-modulation (PWM) latch configured to generate a PWM signal based on an output of the comparator," as recited in amended claim 1 (emphasis added).
In the rejection of previously-pending claim 10, the Examiner relied on the analog sample and hold module 315 to allegedly teach the claimed PMW latch and the comparator 310 to allegedly teach the claimed comparator. However, Valentine's mention of a comparator and a sample and hold module does not disclose the amended claim language of claim 1 in which "a comparator [is] configured to compare the pixel data with a counter value" and "a pulse-width-modulation (PWM) latch configured to generate a PWM signal based on an output of the comparator." Moreover, the various secondary references do not teach or suggest this aspect of amended claim 1.
The Examiner acknowledges that the amended claim 1 is formed by incorporating claim 10 of the initial application with claim 1. The Examiner found the arguments of the Applicant regarding claim 10 persuasive, in that Valentine's mention of a comparator and a sample and hold module does not disclose the amended claim language of claim 1. Therefore, the amended claim 1 overcame the rejection based on Valentine (US 2019/0306945 A1), Pan (US 2019/0302917 A1), and Morris (US 2020/0251049 A1) as previously set forth in the non-final office action mailed on 7/16/2025. However, amended claim 1 is now rejected under new grounds based on a new prior-art, Yee (US 2020/0251050 A1), in combination with Valentine, Pan and Morris in the current office action. Rejections are also made on claims 1-9 and 11-14, which are directly or indirectly depend on claim 1, based on this new prior-art in combination with the prior art of the non-office action.
Amended independent claim 15 has been amended in a similar/analogous manner and thus is patentable over the cited references for similar/analogous reasons. Dependent claims 2-9, 11-14, and 16-19 depend from independent claims 1 and 15 respectively, and thus are patentable over the cited references at least by virtue of their dependencies. Therefore, Applicant respectfully requests that the Examiner withdraw this rejection.
For the reason described for claim 1 above, amended claim 15 also overcame the rejection based on lguchi-513 (US 2019/0385513 A1) and Valentine (US 2019/0306945 A1) as previously set forth in the non-final office action. Again, as in the case of claim 1 above, claim 15 is also rejected in the current office action by combining the new prior art Yee (US 2020/0251050 A1) with Iguchi-513 and Valentine of the non-final office action. Claims 16-19 and new claims 21-22, which are all directly or indirectly dependent on claim 15, are also rejected by the combination of Yee and the prior art of the non-final office action.
For the purpose of compact prosecution, the Examiner notes, however, that incorporating limitations related to the pixel structure and material composition, and/or more detailed description of control circuitry might render independent claims 1 and 15 inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812