Prosecution Insights
Last updated: May 29, 2026
Application No. 18/163,209

METHODS AND SYSTEMS FOR CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCERS

Non-Final OA §102
Filed
Feb 01, 2023
Examiner
CAZAN, LIVIUS RADU
Art Unit
3729
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
GE Precision Healthcare LLC
OA Round
2 (Non-Final)
63%
Grant Probability
Moderate
2-3
OA Rounds
1m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 63% of resolved cases
63%
Career Allowance Rate
596 granted / 949 resolved
-7.2% vs TC avg
Strong +26% interview lift
Without
With
+25.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
38 currently pending
Career history
993
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
63.3%
+23.3% vs TC avg
§102
12.9%
-27.1% vs TC avg
§112
20.8%
-19.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 949 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rothberg (US20180257927A1). Rothberg discloses the claimed invention as follows (refer mainly to Fig. 3): Claim 1. A microelectromechanical systems device, comprising: a silicon wafer (400 in Fig. 4C, of which 308 and 312 are left in Fig. 3) with a first oxide coating (312, Figs. 3 and 4C); a cavity (306, Figs. 3 and 4C) in the first oxide coating having a substantially flat floor (see Fig. 4C) formed of a layer of the first oxide coating that is continuous with the first oxide coating at post regions (i.e., oxide regions extending upwardly, defining the cavity 306 therebetween; see Figs. 4B and 4C) of the MEMS device, the cavity etched to a first depth prior to deposition of a masking layer1; and a membrane (310, Figs. 3 and 4D) coupled to the silicon wafer and spaced away from the substantially flat floor of the cavity by a sum of an oxide layer (see “oxide layer” in last sentence of [0084]) coating the membrane and a second depth of the cavity, wherein the second depth is a sum of the first depth and a height of a second oxide coating formed at the post regions of the MEMS device after the masking layer is removed from the post regions (see footnote 1). Claim 2. The MEMS device of claim 1, wherein the MEMS device is a capacitive micromachined ultrasonic transducer. See [0004] and [0005]. Claim 3. The MEMS device of claim 1, wherein the first oxide coating continuously coats surfaces of the silicon wafer, including at the substantially flat floor of the cavity. See Fig. 4C and [0077] and [0079]. Claim 4. The MEMS device of claim 1, wherein the first depth is equal to or less than a thickness of the masking layer. See footnote 1. This limitation further defines the first depth. However, the first depth is recited in a process limitation, and the structure of the completed MEMS device does not actually require a first depth. Claim 5. The MEMS device of claim 1, wherein neither the first depth nor the second depth of the cavity extends into the silicon wafer. See Fig. 4C and [0079]. Claim 6. The MEMS device of claim 1, wherein the second depth of the cavity is equal to a thickness of the masking layer plus a field oxidation height at the post regions. See footnote 1. This limitation further defines the second depth. However, the thickness of the masking layer and a second oxide coating are recited in a process limitation in claim 1, and the structure of the completed MEMS device does not actually require a second depth depending on a thickness of a masking layer and a field oxidation height. Claim 7. The MEMS device of claim 1, wherein surfaces of the post regions are not etched. Cavity 306 is formed in oxide layer 312, without etching the upper surface of the oxide layer, corresponding to the top of the post regions. Further, this is a process limitation, which does not affect the structure of the completed MEMS device. Allowable Subject Matter Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim(s) 1-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIVIUS R CAZAN whose telephone number is (571)272-8032. The examiner can normally be reached Monday - Friday noon-8:30 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hong can be reached at 571-272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LIVIUS R. CAZAN/Primary Examiner, Art Unit 3729 1 The limitations in italics are product-by-process limitations, which in this case do not affect the structure of the product. See MPEP 2113.
Read full office action

Prosecution Timeline

Feb 01, 2023
Application Filed
Oct 01, 2025
Non-Final Rejection mailed — §102
Dec 05, 2025
Applicant Interview (Telephonic)
Jan 02, 2026
Response Filed
Mar 04, 2026
Final Rejection mailed — §102
Apr 30, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12641766
IC CHIP-MOUNTING DEVICE AND IC CHIP-MOUNTING METHOD
3y 11m to grant Granted May 26, 2026
Patent 12628271
ELECTRONIC COMPONENT
3y 2m to grant Granted May 12, 2026
Patent 12620526
METHOD FOR MANUFACTURING MULTILAYER COIL COMPONENT
4y 2m to grant Granted May 05, 2026
Patent 12620878
METHOD FOR STATOR ALIGNMENT TO THE MOTOR HOUSING
3y 8m to grant Granted May 05, 2026
Patent 12614958
STATOR ASSEMBLY APPARATUS AND STATOR ASSEMBLY METHOD
3y 5m to grant Granted Apr 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
63%
Grant Probability
88%
With Interview (+25.5%)
3y 5m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 949 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month