Office Action Predictor
Last updated: April 15, 2026
Application No. 18/163,417

HIGH-BANDWIDTH PACKAGE-ON-PACKAGE STRUCTURE

Non-Final OA §102§103
Filed
Feb 02, 2023
Examiner
DOAN, THERESA T
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mediatek INC.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
1y 10m
To Grant
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
791 granted / 896 resolved
+20.3% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
24 currently pending
Career history
920
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
42.1%
+2.1% vs TC avg
§102
38.4%
-1.6% vs TC avg
§112
3.3%
-36.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 896 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 6, 9, 11, 15 and 18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kang et al. (2022/0005793). Regarding claims 1, 11 and 18, Kang (Fig. 2) discloses a high-bandwidth package-on-package (HBPoP) structure, comprising: a first package structure 100 and a second package structure 140 stacked vertically, wherein the first package structure 100 comprises: a first silicon-based substrate or ceramic material 100 ([0038-0040]) comprising a first wiring structure 105 ([0042]); a semiconductor die 110 disposed over the first silicon-based substrate or ceramic material 100 and electrically coupled to the first wiring structure 105 ([0038]); a second silicon-based substrate 140 ([0078]) disposed over the semiconductor die 110 and comprising a second wiring structure 145 ([0079]); and a molding material 130 in contact with the first silicon-based layer or ceramic material 100 and the second silicon-based layer 140 and covering sidewalls of the semiconductor die 110 (Fig. 2 and [0038]). Regarding claims 6 and 9, Kang (Fig. 2) discloses the interposer or the second package substrate 140 is formed of pure silicon. ([0078]). Regarding claim 15, Kang (Fig. 2) discloses wherein a bottom surface of the first ceramic layer 100 and a top surface of the second ceramic layer 140 are exposed. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-5, 7-8, 10, 12-14, 16-17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (2022/0005793) in view of Chakravorty (2006/0012966). Regarding claim 4, Kang (Fig. 2) discloses all the claimed limitations except for the first package substrate is formed of pure silicon. Chakravorty (Fig. 2) discloses the first package substrate 60 is formed of pure silicon ([0027]) for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416. Accordingly, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the device of Kang by forming the first pure silicon package substrate for the intended use as a matter of design choice, as taught by Chakravorty (see Fig. 2, [0027]). Regarding claims 5, 7, 10, 13-14 and 17, Kang discloses all the claimed limitations except for a thickness of the first package substrate or the interposer/the second package substrate or the third ceramic layer is between about 30 μm and about 250 μm. However, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardner v. TEC Systems, Inc., 725 F. 2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to form a thickness of the first package substrate or the interposer/the second package substrate or the third ceramic layer is between about 30 μm and about 250 μm as claimed, because the dimensions are not critical since they can be optimized during routine experimentation, depending upon the device in a particular application. Regarding claim 16, Kang (Fig. 2) discloses further comprising a second package substrate 150 disposed over the interposer 140, wherein the second package substrate 150 comprises a third wiring structure 155 in a third ceramic layer ([0084-0085]). Kang discloses all the claimed limitations except for the third ceramic layer is formed of a low-temperature co-fired ceramic material, a high-temperature co-fired ceramic material, or a combination thereof. Chakravorty (Fig. 2) discloses the third ceramic layer 50 is formed of a high-temperature co-fired ceramic material ([0060]) for the intended use as a matter of design choice. Accordingly, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the device of Kang by forming the third ceramic layer is formed of a high-temperature co-fired ceramic material for the intended use as a matter of design choice, as taught by Chakravorty (see Fig. 2, [0060]). Regarding claims 2-3, 8 and 12, as discussed the combination above, Chakravorty (Fig. 2) discloses the first package substrate or the interposer/the second package substrate 50 is formed of a high-temperature co-fired ceramic material ([0060]). Regarding claim 19, Kang discloses all the claimed limitations except for the first silicon-based substrate and the second silicon-based substrate are formed of pure silicon. Chakravorty (Fig. 2) discloses the first package substrate 60 is formed of silicon or ceramic ([0027]) in order to enhance the reliability of a semiconductor device. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the device of Kang by forming the first silicon-based substrate and the second silicon-based substrate are formed of pure silicon for the intended use as a matter of design choice, as taught by Chakravorty (see Fig. 2, [0027]). Regarding claim 20, as discussed, the combination above, Kang (Fig. 2) discloses the second package structure 150 comprises a third wiring structure 155 in pure silicon. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THERESA T DOAN whose telephone number is (571)272-1704. The examiner can normally be reached on Monday, Tuesday, Wednesday and Thursday from 7:00AM - 3:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THERESA T DOAN/ Primary Examiner, Art Unit 2814
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Prosecution Timeline

Feb 02, 2023
Application Filed
Nov 10, 2025
Non-Final Rejection — §102, §103
Apr 01, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598750
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 07, 2026
Patent 12593718
MEMORY SYSTEM PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 31, 2026
Patent 12593636
MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
2y 5m to grant Granted Mar 31, 2026
Patent 12588511
SHIELDING ASSEMBLY FOR SEMICONDUCTOR PACKAGES
2y 5m to grant Granted Mar 24, 2026
Patent 12588527
DIELECTRIC INTERPOSER WITH ELECTRICAL-CONNECTION CUT-IN
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+5.1%)
1y 10m
Median Time to Grant
Low
PTA Risk
Based on 896 resolved cases by this examiner. Grant probability derived from career allow rate.

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