DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Jun. 3rd 2026 has been entered. Claims 1-14 and 20-25 remain pending in the application. Applicant’s amendments to the Claims and Specification (Title) have overcome each and every objection and 112 rejection previously set forth in the Non-Final Office Action mailed on Mar. 3rd 2026. Claims 1-7, 11-14 and 20-25 are examined in this office action. Claims 8-10 are withdrawn from further consideration.
Claim Objections
Claim 21 is objected to because of the following informalities:
In claim 21, line 13, “the common contact plug " should read “a common contact plug”.
In claim 21, line 15, “the lower surface " should read “a lower surface”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 21 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ching et al. (US 20190067444), hereinafter Ching.
Regarding claim 21, Ching teaches a semiconductor device (Abstract) comprising:
a first region (Annotated fig. 16C, 16B, region below left epitaxy layers 132; para. 0060) and a second region (region below right 132), each extending in a first horizontal direction (Annotated fig. 16C, A-A' direction);
a field region (fig. 16B, region below right dummy fin structures 116; para. 0043) defining the first and second regions (region below 132);
an insulating structure (right 116) extending parallel to the first and second regions (region below 132) on the field region (region below right 116);
a gate structure (Annotated fig. 16C, metal gate electrodes 148 marked with ‘1st' and ‘2nd'; para. 0078) extending, in a second horizontal direction (B-B' direction), to intersect the first and second regions (region below 132) and the insulating structure (right 116); and
source/drain regions (132 as source/drain regions; para. 0060) disposed on the first and second regions (region below 132) and on at least one side (two side) of the gate structure (148),
wherein the insulating structure (right 116) has a first portion (portion of 116 below 148) overlapping the gate structure (148) in a vertical direction (vertical direction), perpendicular to the first and second horizontal directions (A-A' and B-B' direction), and a second portion (portion not below 148) other than the first portion (116 below 148),
the insulating structure (right 116) is spaced apart from the source/drain regions (132 by oxide layer 134; para. 0061),
the common contact plug (source/drain contacts 152; para. 0082) extends on the insulating structure (right 116) between the source/drain regions (132), and
the lower surface of the common contact plug (152) is in contact with an upper surface of the second portion (upper surface of 116 not below 148) of the insulating structure (right 116).
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(Annotated fig. 16C)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 11-12, 14 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ching in view of Zang et al. (US 20200135723).
Regarding claim 1, Ching teaches a semiconductor device (Abstract) comprising:
active regions (fig. 16B, region below epitaxy layers 136; para. 0065) including a first active region (region below left 136) and a second active region (region below right 136) parallel to each other (Annotated fig. 16C, both parallel along A-A' direction) and respectively extending on a substrate (fig. 16B, substrate 102; para. 0036) in a first horizontal direction (Annotated fig. 16C, A-A' direction);
a field region (fig. 16B, region below left dummy fin structures 116; para. 0043) defining the active regions (region below 136) on the substrate (102);
a first insulating structure (left 116) extending in the first horizontal direction (A-A' direction) on the field region (region below left 116) between the first active region (region below left 136) and the second active region (region below right 136);
a gate structure (Annotated fig. 16C, metal gate electrodes 148 marked with ‘1st' and ‘2nd'; para. 0078) extending, in a second horizontal direction (B-B' direction), to intersect the active regions (region below 136) and the first insulating structure (left 116) on the substrate (102);
source/drain regions (136 as source/drain regions; para. 0065) disposed on at least one side (up and down side) of the gate structure (148), the source/drain regions (136) including a first source/drain region (left 136) disposed on the first active region (region below left 136) and a second source/drain region (right 136) on the second active region (region below right 136); and
a common contact plug (Annotated fig. 16C, source/drain contacts 152 marked with ‘common’; para. 0082) disposed on a first side (down side) of the gate structure (148) and electrically connected (fig. 16B, 152 connect 136) to the first and second source/drain regions (136) opposing each other in the second horizontal direction (B-B' direction), wherein the first insulating structure (left 116) includes a first portion (left 116 below 148) overlapping the gate structure (148) in a vertical direction (vertical direction), perpendicular to the first and second horizontal directions (A-A' and B-B' directions), and a second portion (left 116 outside 148) other than the first portion (left 116 below 148), and
at least a portion of the second portion of the first insulating structure (fig. 16B, left 116 outside 148) overlaps the common contact plug (152) in the vertical direction.
Ching fails to explicitly teach an uppermost surface of the first insulating structure is positioned at a height different from that of an uppermost surface of the gate structure.
However, Zang teaches an uppermost surface of the first insulating structure (Zang: fig. 10, uppermost surface of dielectric bar 500 without gate cut isolation 900; para. 0034, similar to left 116 not isolate gate of Ching) is positioned at a height different from that of an uppermost surface of the gate structure (Zang: uppermost surface of metal gate 1000; para. 0036, similar to 148 of Ching).
Zang and Ching are considered to be analogous to the claimed invention because they are in the same field of gate isolation structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an uppermost surface of the first insulating structure is positioned at a height different from that of an uppermost surface of the gate structure as taught by Zang.
Doing so would realize a gate isolation with an improved aspect ratio and more flexible for gate isolation position. (Zang: para. 0034).
Regarding claim 2, Ching in view of Zang teaches the semiconductor device of claim 1, wherein the gate structure (Ching: fig. 16C, 148 and more clearly in fig. 11A, here is poly gate electrode 120; para. 0051) is in contact with at least a portion of an upper surface of the first portion of the first insulating structure (Ching: upper surface of left 116 under 120), the gate structure (Ching: 120) is in contact with at least a portion of a side surface of the first portion of the first insulating structure (Ching: side surface of left 116 under 120), and
the common contact plug (Ching: fig. 16B, 152) is in contact with an upper surface of the second portion of the first insulating structure (Ching: upper surface of 116 outside 148).
Regarding claim 3, Ching in view of Zang teaches the semiconductor device of claim 1, wherein the uppermost surface of the first insulating structure (Zang: fig. 10, 500 without 900) is positioned on a level lower (Zang: lower level of 500) than that of the uppermost surface of the gate structure (Zang: 1000).
Regarding claim 4, Ching in view of Zang teaches the semiconductor device of claim 1, further comprising:
a second insulating structure (Ching: Annotated fig. 16C, middle 116) spaced apart from the first insulating structure (Ching: left 116) and extending parallel to the first insulating structure (Ching: left 116) on the field region (Ching: region below left 116); and
the gate structure (Ching: 148) includes first and second gate structures (Ching: 148 marked with 1st and 148 marked with 2nd) opposing each other in the second horizontal direction (Ching: B-B' direction).
Ching in view of Zang according to claim 1 fails to explicitly teach a gate isolation pattern extending in the first horizontal direction on the second insulating structure;
the second insulating structure are disposed between the first and second gate structures, and
the second insulating structure overlaps the gate isolation pattern in the vertical direction.
However, Zang teaches a gate isolation pattern (Zang: fig. 10, gate cut isolation 900; para. 0034) extending in the first horizontal direction (Zang: direction perpendicular to the paper, similar to A-A' direction of Ching) on the second insulating structure (Zang: middle dielectric bar 500; para. 0034, similar to 116 of Ching);
the second insulating structure (Zang: middle 500) are disposed between the first and second gate structures (Zang: metal gate 1000 on the left and right; para. 0036, similar to 148 of Ching), and
the second insulating structure (Zang: middle 500) overlaps the gate isolation pattern (Zang: 900) in the vertical direction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add gate isolation pattern as taught by Zang.
Doing so would realize a gate isolation with an improved aspect ratio and more flexible for gate isolation position. (Zang: para. 0034).
Regarding claim 5, Ching in view of Zang teaches the semiconductor device of claim 4, wherein an upper surface of the gate isolation pattern (Zang: fig. 10, upper surface of 900) is positioned on a level substantially the same (same level) as or higher than that of an upper surface of the gate structure (Zang: upper surface of 1000).
Regarding claim 6, Ching in view of Zang teaches the semiconductor device of claim 4, wherein the second insulating structure (Zang: fig. 10, middle 500) includes a material the same (Zang: from same material/layer; para. 0029) as that of the first insulating structure (Zang: 500 on the left), and has an upper surface (Zang: upper surface of middle 500) having a level substantially the same (Zang: same height) as that of an upper surface of the first insulating structure (Zang: upper surface of 500 on the left).
Regarding claim 11, Ching in view of Zang teaches the semiconductor device of claim 1, wherein the common contact plug (Ching: fig. 16B, 152) is in contact with an upper surface of the first source/drain region (Ching: upper surface of left 136), an upper surface of the second source/drain region (Ching: upper surface of right 136), and an upper surface of the first insulating structure (Ching: upper surface of left 116).
Regarding claim 12, Ching in view of Zang teaches the semiconductor device of claim 11, wherein the common contact plug (Ching: fig. 16B, 152) has a portion (Ching: portion above left 116) extending onto (indirectly on) a side surface of the first insulating structure (Ching: side surface of left 116).
Regarding claim 14, Ching in view of Zang teaches the semiconductor device of claim 1, wherein the first insulating structure (Ching: fig. 16B, left 116) includes at least one of SiN, SiON, SiCN, or SiOCN (Ching: SiCN, SiOCN; para. 0044).
Regarding claim 22, Ching teaches the semiconductor device of claim 21 including the insulating structure (right 116).
Ching fails to explicitly teach an uppermost surface of the insulating structure is positioned at a level lower than that of an upper surface of the common contact plug.
However, Zang teaches an uppermost surface of the insulating structure (Zang: fig. 10, uppermost surface of dielectric bar 500 without gate cut isolation 900; para. 0034, similar to right 116 not isolate gate of Ching) is positioned at a level lower than that of an upper surface of the common contact plug (Zang: uppermost surface of metal gate 1000; para. 0036, similar to 148 of Ching, which has the same uppermost surface of 152 of Ching)
Zang and Ching are considered to be analogous to the claimed invention because they are in the same field of gate isolation structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an uppermost surface of the insulating structure is positioned at a height different from that of an uppermost surface of the common contact plug as taught by Zang.
Doing so would realize a gate isolation with an improved aspect ratio and more flexible for gate isolation position. (Zang: para. 0034).
Regarding claim 23, Ching teaches the semiconductor device of claim 21 including the insulating structure (right 116).
Ching fails to explicitly teach an uppermost surface of the insulating structure is positioned at a height different from that of an uppermost surface of the gate structure.
However, Zang teaches an uppermost surface of the insulating structure (Zang: fig. 10, uppermost surface of dielectric bar 500 without gate cut isolation 900; para. 0034, similar to right 116 not isolate gate of Ching) is positioned at a height different from that of an uppermost surface of the gate structure (Zang: uppermost surface of metal gate 1000; para. 0036, similar to 148 of Ching).
Zang and Ching are considered to be analogous to the claimed invention because they are in the same field of gate isolation structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an uppermost surface of the insulating structure is positioned at a height different from that of an uppermost surface of the gate structure as taught by Zang.
Doing so would realize a gate isolation with an improved aspect ratio and more flexible for gate isolation position. (Zang: para. 0034).
Claims 7 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Ching in view of Zang as applied to claim 1 or 4 above, and further in view of Hsueh et al. (US 20200006334).
Regarding claim 7, Ching in view of Zang teaches the semiconductor device of claim 4, further comprising:
the first source/drain region (Ching: fig. 16B and Annotated fig. 16C, region below left 136) disposed on a second side (up side) opposing the first side (down side) of the gate structure (Ching: 148 with 1st, 2nd) in the first horizontal direction (Ching: A-A' direction); and
the second source/drain region (Ching: region below right 136) disposed on the second side (up side) of the gate structure (Ching: 148), wherein at least a portion of the second insulating structure (Ching: middle 116) overlaps a generic connect structure (Ching: connect structure marked with 'generic') in the vertical direction.
Ching in view of Zang fails to explicitly teach a first contact plug electrically connected to the first source/drain region;
a second contact plug electrically connected to the second source/drain region
at least a portion of the second insulating structure overlaps the first or second contact plugs in the vertical direction.
However, Hsueh teaches a first contact plug (Hsueh: fig. 18, left contact 112; para. 0055) electrically connected to the first source/drain region (Hsueh: left epitaxial source/drain regions 80; para. 0058, similar to 136 of Ching);
a second contact plug (Hsueh: contact 113; para. 0058) electrically connected to the second source/drain region (Hsueh: middle left 80);
at least a portion of the second insulating structure (Hsueh: dielectric material 140; para. 0058, similar to 116 of Ching) overlaps the first or second contact plugs (Hsueh: 140 overlaps 113) in the vertical direction.
Hsueh, Zang and Ching are considered to be analogous to the claimed invention because they are in the same field of gate isolation structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first contact plug and second contact plug as taught by Hsueh.
Doing so would realize contacts to connect source/drain regions and dielectric material to reduce the chance of undesirable electrical shorts between contact and gate (Hsueh: para. 0058).
Regarding claim 24, Ching in view of Zang teaches the semiconductor device of claim 1, wherein the gate structure (Ching: Annotated fig. 16C, 148) includes a gate electrode (Ching: metal gate electrodes 148; para. 0077) extending in the second horizontal direction (Ching: B-B' direction).
Ching in view of Zang fails to explicitly teach an upper surface of the common contact plug is positioned at a height different from that of an upper surface of the gate electrode.
However, Hsueh teaches an upper surface of the common contact plug (Hsueh: fig. 18, upper surface of contact 113 at second ILD 95; para. 0055, 0058, similar to 152 of Ching) is positioned at a height (Hsueh: 95 is higher than 90) different from that of an upper surface of the gate electrode (Hsueh: fig. 11A, upper surface of metal gates 97 at first interlayer dielectric (ILD) 90; para. 0035, 0038, similar to 148 of Ching).
Hsueh, Zang and Ching are considered to be analogous to the claimed invention because they are in the same field of gate isolation structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an upper surface of the common contact plug is positioned at a height different from that of an upper surface of the gate electrode as taught by Hsueh.
Doing so would realize contacts to connect source/drain regions and dielectric material to reduce the chance of undesirable electrical shorts between contact and gate (Hsueh: para. 0058).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ching in view of Zang as applied to claim 1 above, and further in view of Ju et al. (US 20210343713).
Regarding claim 13, Ching in view of Zang teaches the semiconductor device of claim 1 including the active regions (Ching: fig. 16B, region below 136).
Ching in view of Zang fails to explicitly teach a plurality of channel layers disposed to be spaced apart from each other in the vertical direction on the active regions, wherein the plurality of channel layers is at least partially in contact with the source/drain regions.
However, Ju teaches a plurality of channel layers (Ju: fig. 15, semiconductor layer 220 as channels; para. 0020) disposed to be spaced apart from each other (Ju: 220 are spaced apart) in the vertical direction on the active regions (Ju: transistor regions 202A/B; para. 0020, similar to region below 136 of Ching), wherein the plurality of channel layers (Ju: 220) is at least partially in contact with the source/drain regions (Ju: fig. 16, epitaxial source/drain features 310A/B; para. 0041, similar to 136 of Ching).
Ju, Zang and Ching are considered to be analogous to the claimed invention because they are in the same field of fin structure channel of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a plurality of channel layers as taught by Ju.
Doing so would realize a plurality of channel layers in a transistor region to increase packing density of transistors density (Ju: para. 0064).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ching in view of Zhou et al. (US 20200126998) and Zang.
Regarding claim 20, Ching teaches a semiconductor device (Abstract) comprising:
a first active region (fig. 16B, region below left epitaxy layers 136; para. 0065) and a second active region (region below right 136) parallel to each other (Annotated fig. 16C, both parallel along A-A' direction) and respectively extending on a substrate (fig. 16B, substrate 102; para. 0036) in a first horizontal direction (Annotated fig. 16C, A-A' direction);
first, second, and third field regions (fig. 16B and Annotated fig. 16C, regions below one further left, left, middle dummy fin structures 116; para. 0043) defining the first and second active regions (region below left and right 136) and spaced apart by the first and second active regions (region below left and right 136);
a first insulating structure (fig. 16B, left 116) extending in the first horizontal direction (A-A' direction) on the second field region (region below left 116) between the first active region (region below left 136) and the second active region (region below right 136);
a second insulating structure (Annotated fig. 16C, middle 116) extending parallel to the first insulating structure (left 116) on the first field region or the third field region (region below middle 116);
gate structures (Annotated fig. 16C, metal gate electrodes 148 marked with 1st and 2nd; para. 0078) including first and second gate structures (148 marked with 1st and 148 marked with 2nd) extending, in a second horizontal direction (B-B' direction), to intersect the first and second active regions (region below left and right 136) and the first and second insulating structures (left and middle 116) on the substrate (102), the first and second gate structures (148 marked with 1st and 2nd) opposing each other in the second horizontal direction (B-B' direction);
source/drain regions (136 as source/drain regions; para. 0065) including first source/drain regions (left 136) disposed on at least one side (up and down side) of the gate structures (148) and disposed on the first active region (region below left 136) and second source/drain regions (right 136) disposed on the second active region (region below right 136);
a common contact plug (Annotated fig. 16C, source/drain contacts 152 marked with common; para. 0082) electrically connected to the first source/drain regions (left 136) and the second source/drain regions (right 136); and
a gate isolation pattern (Annotated fig. 16C, extent/top portion of middle 116 between 148 marked with 1st and 2nd) disposed between the first and second gate structures (148 marked with 1st and 2nd) on the second insulating structure (middle 116), wherein each of the gate structures (148) includes a gate electrode (148) extending in the second horizontal direction (B-B' direction) and a gate spacer (spacer 126; para. 0053) disposed on at least one side surface (up and down side) of the gate electrode (148).
Ching fails to explicitly teach insulating liners extending in the first horizontal direction on side surfaces of each of the first and second insulating structures;
the insulating liners and the gate spacer include a same material.
However, Zhou teaches insulating liners (Zhou: fig. 13, first sidewall spacer 211; para. 0094) extending in the first horizontal direction (Zhou: direction perpendicular to the paper, similar to A-A' direction of Ching) on side surfaces of each of the first and second insulating structures (Zhou: side surfaces of interlayer dielectric layer 212; para. 0094, similar to 116 of Ching);
the insulating liners (Zhou: 211 made of SiN; para. 0091) and the gate spacer (Zhou: dummy gate sidewalls 205 made of SiN; para. 0047, similar to 126) include a same material (Zhou: same material SiN).
Zhou and Ching are considered to be analogous to the claimed invention because they are in the same field of gate isolation structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add insulating liners with same material as taught by Zhou into Ching.
Doing so would realize a liner to protect the interlayer dielectric layer structure and easier for manufacture with same material (Zhou: para. 0093). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In addition, Ching in view of Zhou fails to explicitly teach an uppermost surface of the first insulating structure is positioned at a height different from that of an uppermost surface of the gate structure.
However, Zang teaches an uppermost surface of the first insulating structure (Zang: fig. 10, uppermost surface of dielectric bar 500 without gate cut isolation 900; para. 0034, similar to left 116 not isolate gate of Ching) is positioned at a height different from that of an uppermost surface of the gate structure (Zang: fig. 10, uppermost surface of metal gate 1000; para. 0036, similar to 148 of Ching).
Zang, Zhou and Ching are considered to be analogous to the claimed invention because they are in the same field of gate isolation structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an uppermost surface of the first insulating structure is positioned at a height different from that of an uppermost surface of the gate structure as taught by Zang.
Doing so would realize a gate isolation with an improved aspect ratio and more flexible for gate isolation position. (Zang: para. 0034).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Ching in view of Zhou and Zang as applied to claim 20 above, and further in view of Hsueh.
Regarding claim 25, Ching in view of Zhou and Zang teaches the semiconductor device of claim 20 including the common contact plug (Ching: fig. 16B, 152).
Ching in view of Zhou and Zang fails to explicitly teach an upper surface of the common contact plug is positioned at a height different from that of an upper surface of the gate electrode.
However, Hsueh teaches an upper surface of the common contact plug (Hsueh: fig. 18, upper surface of contact 113 at second ILD 95; para. 0055, 0058, similar to 152 of Ching) is positioned at a height (Hsueh: 95 is higher than 90) different from that of an upper surface of the gate electrode (Hsueh: fig. 11A, upper surface of metal gates 97 at first interlayer dielectric (ILD) 90; para. 0035, 0038, similar to 148 of Ching).
Hsueh, Zang, Zhou and Ching are considered to be analogous to the claimed invention because they are in the same field of gate isolation structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an upper surface of the common contact plug is positioned at a height different from that of an upper surface of the gate electrode as taught by Hsueh.
Doing so would realize contacts to connect source/drain regions and dielectric material to reduce the chance of undesirable electrical shorts between contact and gate (Hsueh: para. 0058).
Response to Arguments
Applicant’s arguments with respect to claims 1-7, 11-14 and 15-25 of prior art rejections (35 USC 102/103) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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