Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 07/27/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered.
Claims 1, 6, 8, 12, and 18 are currently amended. Claims 2-5 are canceled herein. Claims 7, 11, and 15 were withdrawn by the Examiner. Claims 21-24 are new.
Accordingly, claims 1, 6-24 are pending in this application.
Response to Arguments
Examiner has withdrawn the allowable subject matter indicated in the previous Office action and likewise, this action has not been made final.
Regarding claims 1, 12 and 18, as described below, Zhang teaches wherein the stacked semiconductor nanostructures of the first dummy transistor 106NS are cut in a central region (e.g., in fig. 4B, a region between two the left and right stacks of the stacked semiconductor nanostructures 106NS), wherein the first gate metal 118 fills the central region (fig. 4B).
Furthermore, Zhang in view Paul’91 discloses all the new claims 21-24.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8-9, 12-14, 16-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhang et al. (US 11665877 B1; hereinafter “Zhang”).
In re claim 1, Zhang discloses in figs. 1-2, 4, an integrated circuit including:
a first inverter (Inverter 1) including a first N-type transistor (FET_2B) and a first P-type transistor (FET_2T) stacked vertically (figs. 1, 2A, 4A; Col. 4, 3rd paragraph and col. 5, last paragraph);
a second inverter (Inverter 2) including a second N-type transistor (FET_3B) and a second P-type transistor (FET_3T) stacked vertically (figs. 1, 2A, 4A; Col. 4, 3rd paragraph and col. 5, last paragraph); and
a first butt contact 18, 130 electrically connecting an output of the first inverter (Inverter 1) to an input of the second inverter (Inverter 2) (Cols. 6 and 10, last paragraphs),
wherein the first butt contact 18, 130 is at least partially within a first active region 11L associated with the first inverter (Inverter 1) (Col. 6, 3rd paragraph),
a first pass gate transistor FET_1B and a first dummy transistor FET_1T stacked vertically in the first active region 11L (see figs. 1, 2A and 4); and
a first gate metal 13A extending unbroken between the first dummy transistor FET_1T and either the second N-type transistor (FET_3B) or the second P-type transistor (FET_3T),
wherein the first butt contact 18, 130 contacts the first gate metal 13A at least partially within the first active region 11L,
wherein the first butt contact 18, 130 and the first gate metal 13A electrically connect the output of the first inverter (node A) to the input of the second inverter (node B),
wherein the first N-type transistor (FET_2B), the first P-type transistor (FET_2T), the first pass gate transistor (FET_1B) and the first dummy transistor (FET_1T) each include a respective set of stacked semiconductor nanostructures 102NS, 106NS, 102NS, 106NS corresponding to channel regions of the transistors (Col. 12, 1st paragraph), and
wherein the stacked semiconductor nanostructures of the first dummy transistor 106NS are cut in a central region (e.g., in fig. 4B, a region between two the left and right stacks of the stacked semiconductor nanostructures 106NS), wherein the first gate metal 118 fills the central region (fig. 4B).
In re claim 8, Zhang discloses in figs. 1-2, 4, the integrated circuit of claim 3, comprising a second butt contact 130, 18 (above 13B in fig. 2A) electrically connecting an input of the first inverter (i.e., input of FET_2B and FET_2T, as shown in fig. 1) to an output of the second inverter (node B),
wherein the second butt contact 130, 18 is at least partially within a second active region 11R associated with the second inverter (Inverter 2).
In re claim 9, Zhang discloses in figs. 1-2, 4, the integrated circuit of claim 8 comprising:
a second pass gate transistor FET_4B and a second dummy transistor FET_4T stacked vertically in the second active region 11R; and
a second gate metal 13B extending unbroken between the second dummy transistor FET_4T and either the first N-type transistor FET_2B or the first P-type transistor FET_2T,
wherein the second butt contact 130, 18 contacts the second gate metal 13B at least partially within the second active region 11R,
wherein the second butt contact 130, 18 and the second gate metal 13B electrically connect the input of the first inverter (i.e., input of FET_2B and FET_2T, as shown in fig. 1) to the output of the second inverter (node B),
wherein the first and second inverters (Inverters 1 and 2) and the first and second pass gate transistors (FET_1B, FET_4B) are an SRAM cell (col. 5, 3rd paragraph).
In re claim 12, Zhang discloses in figs. 1-2, 4, an integrated circuit, comprising:
a first N-type transistor (FET_2B) including a gate electrode 117 and a plurality of semiconductor nanostructures 102NS corresponding to channel regions of the first N-type transistor (figs. 1, 2A, 4A; Col. 4, 3rd paragraph and col. 12, 1st paragraph);
a first P-type transistor (FET_2T) stacked vertically with the first N-type transistor (FET_2B) and including a gate electrode 118 and a plurality of semiconductor nanostructures 106NS corresponding to channel regions of the first P-type transistor (figs. 1, 2A, 4A; Col. 4, 3rd paragraph and col. 12, 1st paragraph);
a first pass gate transistor FET_1B including a gate electrode 117 and a plurality of semiconductor nanostructures 102NS corresponding to channel regions of the first pass gate transistor,
wherein a source/drain region of the first pass gate transistor (e.g., node A), a source/drain region of the first N-type transistor (e.g., node A), and source/drain region of the first P-type transistor (e.g., node C) are all electrically connected (fig. 1);
a dummy transistor FET_1T stacked vertically with the first pass gate transistor FET_1B and including a gate electrode 118 (fig. 4A) and a plurality of semiconductor nanostructures 106NS, wherein the stacked semiconductor nanostructures of the first dummy transistor 106NS are cut in a central region (e.g., in fig. 4B, a region between two the left and right stacks of the stacked semiconductor nanostructures 106NS), wherein the first gate metal 118 fills the central region (fig. 4B); and
a butt contact 18, 130 electrically connected to the source/drain region of the first N-type transistor 15L and the gate electrode of the dummy transistor 118 and at least partially underlying or partially overlying the semiconductor nanostructures of the first pass gate transistor 102NS and at least partially overlying or underlying the source/drain region of the first N-type transistor 15L (Col. 6, 3rd paragraph).
In re claim 13, Zhang discloses in figs. 1-2, 4, the integrated circuit of claim 12, comprising:
a second N-type transistor (FET_3B) including a gate electrode 117 and a plurality of semiconductor nanostructures 102NS corresponding to channel regions of the second N-type transistor (figs. 1, 2A, 4A; Col. 4, 3rd paragraph and col. 5, last paragraph); and
a second P-type transistor (FET_3T) stacked vertically with the second N-type transistor (FET_3B) and including a gate electrode 118 and a plurality of semiconductor nanostructures 106NS corresponding to channel regions of the second P-type transistors,
wherein the gate electrode of dummy transistor 118 (same as 13A) is integral with the gate electrode of the second P-type transistor 118 (same as 13A).
In re claim 14, Zhang discloses in figs. 1-2, 4, the integrated circuit of claim 13, comprising: a first inverter (Inverter 1) including the first N-type transistor (FET_2B) and the first P-type transistor (FET_2T); and a second inverter (Inverter 2) cross-coupled with the first inverter and including the second N-type transistor (FET_3B) and the second P-type transistor (FET_3T) (fig. 1).
In re claim 16, Zhang discloses in figs. 1-2, 4, the integrated circuit of claim 13,
wherein the first P-type transistor (FET_2T) is above the first N-type transistor (FET_2B) and the first dummy transistor (FET_1T) is above the first pass gate transistor (FET_1B).
In re claim 17, Zhang discloses in figs. 1-2, 4, the integrated circuit of claim 13, wherein the gate electrode of the second N-type transistor 117, the gate electrode of the second P-type transistor 118, and the gate electrode of the dummy transistor 118 collectively form an L shape (a cross-section across the gate structure 13A would be similar to the B-B’ cross-section across gate structure 13B, see figs. 2A and 4B. Therefore, the gate electrode of the second N-type transistor 117, the gate electrode of the second P-type transistor 118, and the gate electrode of the dummy transistor 118 collectively form an L shape).
In re claim 18, Zhang discloses in figs. 1-2, 4, a method, comprising:
forming, in a first active region 11L of an integrated circuit, a first inverter (Inverter 1) including a first N- type transistor (FET_2B) stacked vertically with a first P-type transistor (FET_2T) (col. 6, 4th paragraph);
forming, in a second active region 11R of the integrated circuit, a second inverter (Inverter 2) cross- coupled with the first inverter (Inverter 1) and including a second N-type transistor (FET_3B) stacked vertically with a second P-type transistor (FET_3T);
forming, in the first active region 11L, a first pass gate transistor (FET_1B) stacked vertically with a first dummy transistor (FET_1T); and
forming a first butt contact 18, 130 in contact with a gate metal of the dummy transistor 118 (or 13A) at the first active region 11L and electrically connecting an output of the first inverter (node A) to an input of the second inverter (node B) (col. 4, last paragraph),
wherein the gate metal of the first dummy transistor 13A extends from the first active region 11L to either the second N-type transistor or the second P-type transistor (FET_3T),
wherein the stacked semiconductor nanostructures of the first dummy transistor 106NS are cut in a central region (e.g., in fig. 4B, a region between two the left and right stacks of the stacked semiconductor nanostructures 106NS), wherein the first gate metal 118 fills the central region (fig. 4B).
In re claim 19, Zhang discloses in figs. 1-2, 4, the method of claim 18, comprising electrically isolating a gate metal of the pass gate transistor 117 from the gate metal of the dummy transistor 118 with a dielectric layer 104 vertically separating the gate metal of the first pass gate transistor from the gate metal of the first dummy transistor (fig. 4A; col. 8, 2nd paragraph).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, 20-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, as applied to claims 3 and 19 above, respectively and further in view of Paul et al. (US 20230345691 A1; hereinafter “Paul’91”).
In re claim 6, Zhang discloses in figs. 1-2, 4, the integrated circuit of claim 3 outlined above.
Zhang does not expressly disclose wherein the first butt contact is positioned below both the first gate metal and a second gate metal.
In the same field of endeavor, Paul’91 discloses in figs. 1-9, an integrated circuit, wherein a first butt contact 723 is positioned below both a first gate metal 521 and a second gate metal 541 (¶31,39).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Paul’91 into the SRAM layout of Zhang and form the butt contact below both the first gate metal and a second gate metal to reduce cell area without requiring a fundamental change in the fabrication processes (¶2-3 of Paul’91).
In re claim 20, Zhang discloses in figs. 1-2, 4, the method of claim 18, comprising:
forming the first N-type transistor (FET_2B), the second N-type transistor (FET_3B), the first P-type transistor (FET_2T), and the second P-type transistor (FET_3T) during front end processing of the integrated circuit with the integrated circuit.
Zhang does not expressly disclose flipping the integrated circuit after forming the first N-type transistor, the second N-type transistor, the first P-type transistor, and the second P-type transistor; and forming the first butt contact during back end processing after flipping the integrated circuit.
In the same field of endeavor, Paul’91 discloses in figs. 1-9, a method of forming an integrated circuit, flipping the integrated circuit after forming a first N-type transistor 210, a second N-type transistor 420, a first P-type transistor 310, and a second P-type transistor 320 (¶28) (figs. 6-9; ¶41-42); and
forming the first butt contact 871, 852, 862 during back end processing after flipping the integrated circuit (fig. 8; ¶46).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Paul’91 into method of Zhang to reduce cell area without requiring a fundamental change in the fabrication processes (¶2-3 of Paul’91).
In re claim 21, Zhang as modified by Paul’91 discloses the method of claim 20 outlined above.
Paul’91 further discloses, in figs. 1-9, the method further comprising replacing semiconductor substrate materials 100 with dielectric materials 160 during the back end processing after flipping the integrated circuit (fig. 8; ¶44).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Paul’91 into method of Zhang to pad up the thickness of the backside dielectric layer within which backside contacts and power supply lines for the SRAM device may be formed (¶44 of Paul’91).
In re claim 22, Zhang as modified by Paul’91 discloses the method of claim 20 outlined above.
Zhang further discloses the method further comprising electrically isolating a gate metal of the first pass gate transistor 117 from the gate metal of the first dummy transistor 118 with a dielectric layer 144 vertically separating the gate metal of the first pass gate transistor 117 from the gate metal of the first dummy transistor 118 (fig. 4B; C. 11, 3rd para.).
In re claim 23, Zhang as modified by Paul’91 discloses the method of claim 20 outlined above.
Zhang further discloses wherein the gate metal 13A of the first dummy transistor FET_1T extends unbroken to a gate electrode of the second P-type transistor FET_3T (fig. 2A; C. 6, 4th para.).
In re claim 24, Zhang as modified by Paul’91 discloses the method of claim 20 outlined above.
Zhang further discloses, in figs. 1-2, 4, the method comprising forming a second butt contact 18, 130 electrically connecting an input of the first inverter (Inverter 1 comprising FET_2T, FET_2B) to an output D of the second inverter (Inverter 2 comprising FET_3T, FET_3B),
wherein the second butt contact 18, 130 is at least partially within the second active region 11R (fig. 2A).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, as applied to claim 1 above, and further in view of Hsu et al. (US 20200058564 A1; hereinafter “Hsu”).
In re claim 10, Zhang discloses in figs. 1-2, 4, the integrated circuit of claim 1 outlined above.
Zhang does not expressly disclose wherein the first butt contact is entirely within the first active region.
In the same field of endeavor, Hsu discloses in figs. 1-2, wherein a first butt contact 244 is entirely within a first active region 202 associated with a first inverter (PU2/PD2) (¶24).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Hsu into the SRAM layout of Zhang to increase the contact area of the butt contact with the diffusion region in the active area and reduce contact resistance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NILUFA RAHIM/Primary Examiner, Art Unit 2893
