DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 02/10/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 02/10/2026 in reply to the non-final rejection mailed on 11/26/2025, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claims 11-13 are canceled. Accordingly, pending in this Office action are claims 1-7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20170011976) in view of Gangoso (US 20090045827).
Park (see, e.g., para.0134) states the embodiment of fig. 9 is similar to the embodiment of figs. 7-8 with the exception of the arrangement and connections shown in the top view. Certain elements will be referenced from both the top view embodiment of fig. 9 and the cross-sectional view embodiment of figs. 7-8 and are interchangeable with one another.
Regarding Claim 1, Park (see, fig. 7, fig. 8, fig. 9) shows a package structure, comprising:
an isolation layer 250 (see, e.g., para.0122) having a plurality of via holes 252 (see, e.g., para.0122),
wherein the isolation layer covers a surface of an interconnect layer 220 & 245a (see, e.g., para.0119),
the via holes expose parts of the interconnect layer (see, e.g., fig. 8),
and the interconnect layer is disposed on a surface of a semiconductor functional structure 210 (see, e.g., para.0115);
N first pads 320b (interchangeable with 220, see, e.g., para.0120, para.0139),
wherein each of the N first pads is formed by the interconnect layer exposed by one of the via holes (220 of the interconnect layer in holes 252, see, e.g., fig. 7),
the N is a positive integer greater than 1;
N redistribution layers 230 (interchangeable with 330, see, e.g., para.0122, para.0135),
wherein each N redistribution layer covers the isolation layer and is electrically connected with a corresponding one of the N first pads (see, e.g., para.0128),
some of the N first pads are arranged side by side along a first direction (y direction) near a first edge of the semiconductor functional structure (see, e.g., annotated figure 1),
other of the N first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure (see, e.g., annotated figure 1),
the first edge and the second edge are two opposite edges of the semiconductor functional structure;
a first insulating layer 255 (see, e.g., para.0123) covering the N redistribution layers and exposing parts of each of the N redistribution layers;
and second pads 260 (interchangeable with 360b) and third pads 270 (interchangeable with 370),
wherein the exposed parts of each of the N redistribution layers form one of the second pads and one of the third pads (see, e.g., para.0124),
a center point of each of the second pads 360b is offset from a center point of the corresponding each of the first pads 320b in a same direction (x direction) and by a same distance (see, e.g., fig. 9, annotated figure 2),
a relative position between one of the second pads 360b and one of the third pads 370 for some of the N redistribution layers is different from a relative position between one of the second pads and one of the third pads for other N redistribution layers (see, fig. 9, e.g., annotated figure 2);
the first pads and the second pads are used for probe card testing (see, e.g., para.0124)
and the third pads are used for leading out bonding wires (pad for connection, see, e.g., para.0135)
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Park, however, fails to show
testing the semiconductor functional structure at different operating speeds,
Gangoso (see, e.g., fig. 1, fig. 6, para.0037-0038), in a similar device to Park, teaches testing a semiconductor functional structure 20 through high and low speeds would prevent using excess materials and labor costs for a defective device.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the testing a semiconductor functional structure 20 through high and low speeds of Gangoso in the device of Park to prevent using excess materials and labor costs for a defective device.
Regarding Claim 2, Park, in view of Gangoso, shows the package structure of claim 1,
wherein the second pad 360b and the third pad 370 comprised in each of the N redistribution layers are arranged side by side along a second direction (x direction, see, e.g., annotated figure 3),
the second direction is perpendicular to the first direction (see, e.g., annotated figure 3).
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Regarding Claim 3, Park, in view of Gangoso, shows the package structure of claim 2,
wherein an orthographic projection of a center point of the second pad 360b on a plane where the interconnect layer is located is offset by a first distance (see, e.g., annotated figure 4) along the second direction (x direction) with respect to the center point of the corresponding one of the N first pad 320b.
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Regarding Claim 4, Park, in view of Gangoso, shows the package structure of claim 3,
wherein an orthographic projection of each of the N redistribution layers 330 (230) on the plane where the interconnect layer is located is of a strip shape (the geometrical shape of 330 is considered a strip since the limitation is broad, see, e.g., fig. 9).
Regarding Claim 5, Park, in view of Gangoso, shows the package structure of claim 4,
wherein first ends of the some of the N first pads 220 (320b) near the first edge and second ends of the some of the N redistribution layers 230 (330) near the first edge are substantially flush along a third direction (z direction, see, e.g., annotated figure 5) perpendicular to both the first direction and the second direction;
and wherein third ends of the other N first pads near the second edge and fourth ends of the other N redistribution layers near the second edge are substantially flush along the third direction.
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Regarding Claim 6, Park (see, e.g., annotated figure 6), in view of Gangoso, shows the package structure of claim 5,
wherein in the some of the N redistribution layers,
the second pads 260 (360b) are located near the second ends (of 230/330) and the third pads 270 (370) are located away from the second ends (of 230/330);
and wherein in the other N redistribution layers,
the second pads 260 (360b) are located near the fourth ends (of 230/330) and the third pads 270 (370) are located away from the fourth ends (of 230/330).
Regarding the limitation, “located away,” under broadest reasonable interpretation Examiner interprets located away as any location that isn’t the same location. Regarding the limitation, “located near,” under broadest reasonable interpretation Examiner interprets located near in proximity to the desired location. The current claim language is broad and the position of the second and third pads are interpreted as such.
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Regarding Claim 7, Park (see, e.g., fig. 9), in view of Gangoso, shows the package structure of claim 6,
wherein the each N redistribution layer 230 (330) further comprises a first region 231 (directly above 220/320b) for conductively connecting with the corresponding one of the first pads (see, e.g., para.0121);
and wherein in the some of the N redistribution layers,
the second pads 360b (260) and the third pads 370 (270) are located at one side (right side) of first regions (see, e.g., fig. 9);
and in the other N redistribution layers,
the second pads and the third pads respectively located at two sides (left and right side) of the first regions (see, e.g., fig. 9).
Response to Arguments
Applicant’s arguments, see pages 7-8, filed 02/10/2026, with respect to the drawings objection and the rejections under 35 U.S.C. 112 have been fully considered and are persuasive. The drawings objection and the rejections under 35 U.S.C. 112 of claims 1 & 11-13 have been withdrawn.
Applicant’s arguments, see pages 8-9, with respect to the rejections of claims 1-7 & 11-13 under 35 U.S.C. 102(a)(1) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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