DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 02/03/2023. Claims 1-20 are currently pending, of which claims 1-14 are currently rejected. Claims 15-17 are objected. Claims 18-20 are allowed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “A computing circuit, disposed in a memory device and electrically coupled to a memory cell of the memory device" and “a weight decoder, configured to obtain a compressed weight from the memory cell” as claimed in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “A computing circuit, disposed in a memory device and electrically coupled to a memory cell of the memory device”. It is unclear how a memory device can be electrically coupled to a memory cell within the same memory device.
Claims 2-10 inherit the same deficiency by reason of dependence, and are rejected for the same reasons as claim 1.
Additionally, Claims 2-10 recite “The memory test circuit of claim 1”. Claim 1 does not recite a memory test circuit. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Patent Application Publication No.: US 20230131308 A1), hereinafter “Lee”, in view of Lamb et al. (U.S. Patent Application Publication No.: US 20190087713 A1), in view of Lu et al. (U.S. Patent No.: US 10943652 B2), hereinafter “Lu”, further in view of Hoang et al. (U.S. Patent No.: US 12079733 B2), hereinafter “Hoang”.
Regarding Claim 1, Lee teaches:
A computing circuit (Fig. 5), disposed in a memory device (Fig. 5, e.g., shows array of SRAM cells 512 (memory device)) and electrically coupled to a memory cell of the memory device (Fig. 5, e.g., shows memory cells 512 coupled to multipliers 514), wherein the computing circuit comprises:
…
a multiplier, … and configured to generate a partial-product by multiplying an input signal with the … weight (Fig. 5, e.g., shows multipliers 514; ¶0041, e.g., each multiplier receives weight bar value and input bar value to generate a product-product);
an adder tree, coupled to the multiplier and configured to generate a partial-sum by performing an addition operation based on the partial-product (Fig. 5, e.g., shows Adder Tree 520 coupled to multipliers 514; ¶0042, e.g., adder tree generates a partial sum from values received from multipliers); and
an accumulator, coupled to the adder tree and configured to generate an accumulated sum by performing an accumulation operation based on the partial-sum and output an output signal based on the accumulated sum (Fig. 5, e.g., shows accumulator 530 coupled to the adder tree 520; ¶0042, e.g., partial-sum accumulator 530 accumulates partials sums and outputs a final result),
…
Lee does not teach:
a weight decoder, configured to obtain a compressed weight from the memory cell and generate a decoded weight based on the compressed weight;
a multiplier, coupled to the weight decoder and configured to generate a partial-product by multiplying an input signal with the decoded weight;
…
wherein the accumulated sum is left shifted based on a shift signal.
However, Lamb teaches compressing sparse weight vectors to be used for MAC operations. Lamb explains “the controller 720 may compress the set of sparse weight vectors 420 to produce a compressed set of sparse weight vectors. In one aspect, the controller 720 may compress the set of sparse weight vectors 420 by removing the zero-weight elements 422a-b.” (Lamb: ¶0109)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the stored weights taught by Lee to be compressed weight vectors as taught by Lamb. One would have been motivated to combine these references because both references disclose performing multiply-accumulate operations using inputs and weights, and Lamb enhances the model of Lee because the compression of weights is implemented “to address issues commensurate with the consumption of computational (e.g., system bandwidth, processor capability, etc.) and/or power (e.g., battery, power supply, etc.) resources by neural networks” (Lamb: ¶0011). Combination would cause for the memory array taught by Lee to receive compressed weights, as taught by Lamb.
Lee in view of Lamb do not teach:
a weight decoder, configured to obtain a compressed weight from the memory cell and generate a decoded weight based on the compressed weight;
a multiplier, coupled to the weight decoder and configured to generate a partial-product by multiplying an input signal with the decoded weight;
…
wherein the accumulated sum is left shifted based on a shift signal.
However, Lu teaches:
a weight decoder, configured to obtain a … weight from the [address counter] and generate a decoded weight based on the … weight (Fig. 2, e.g., shows Row Pulse Decoder receives data from address counter; Column 7, Lines 15-28, e.g., decoder 212 activates wordlines (decoded weights) if a one is applied to the decoder input (weight));
Additionally, Lee suggests using decoders as input-output circuits in the CIM macro. Lee explains “The CIM macro 110 may also include other circuit elements, such as decoders, or other input-output (I/O) circuits for transferring data between storage cells in corresponding CIM memory array(s) 210 and external circuits outside of the CIM macro 110” (Lee: ¶0027).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the CIM macro taught by Lee in view of Lamb to include a decoder as taught by Lu. Combination would cause for the decoder taught by Lu to be used to read and write weight data to update weights stored in storage cells 512 taught by Lee. See Lee ¶0027. Hence, the decoder would obtain compressed weight data to generate decoded weights. One would have been motivated to combine these references because both references disclose using decoders in in-memory computing systems, and Lu enhances the model of Lee in view of Lamb by it allows for the decoder to “activate the wordlines in a sequential order” (Lu: Column 7, Lines 15-28).
Lee in view of Lamb in view of Lu do not teach:
wherein the accumulated sum is left shifted based on a shift signal.
However, Hoang teaches:
wherein the accumulated sum is left shifted based on a shift signal (Column 19, Lines 29-33, e.g., Partial Product Multi-mode accumulate Adder PPMA 1361 includes a multi-mode left shifter 1721 that receives the mode-control signals and a left shift control signal LSh (shift signal)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the accumulator 530 as taught by Lee in in view of Lamb in view of Lu to include the multi-mode left shifter 1721 taught by Hoang . One would have been motivated to combine these references because both references disclose using accumulators to accumulate partial products, and Hoang enhances the model of Lee in in view of Lamb in view of Lu by allowing for the accumulator to operate in different precision modes. See Hoang: Column 20 Lines 5-37.
Regarding Claim 2, Lee in view of Lamb in view of Lu in view of Hoang teach:
The memory test circuit according to claim 1, wherein
the accumulator is configured to left shift the accumulated sum of a previous clock cycle based on the shift signal to generate a left-shifted accumulated sum of the previous clock cycle (Hoang: Column 19, Lines 29-33, e.g., Partial Product Multi-mode accumulate Adder PPMA 1361 includes a multi-mode left shifter 1721; Fig. 17, e.g., shows multi-mode left shifter feeding back data to cascaded adders; Column 19 Lines 63-67, e.g., cascade adders run accumulation cycles (clock cycle)), and
the accumulator is configured to accumulate the left-shifted accumulated sum of the previous clock cycle with the partial-sum of a current clock cycle to generate the accumulated sum of the current clock cycle (Hoang: Fig. 17, e.g., shows multi-mode left shifter feeding back data to cascaded adders; Column 19 Lines 63-67, e.g., cascade adders run accumulation cycles (clock cycle); Column 19 Lines 21-29, e.g., Partial Product Multi-mode accumulate Adder PPMA sums up partial products PP into a partial sumPS).
The motivation to combine provided with respect to claim 1 applies equally to claim 2.
Regarding Claim 3, Lee in view of Lamb in view of Lu in view of Hoang teach:
The memory test circuit according to claim 1, wherein
the weight decoder is configured to decode the compressed weight during a plurality of clock cycles to generate the decoded weight (Lu: Column 7 Lines 15-17, e.g., decoder 212 is used to activate the wordlines in a sequential order (plurality of clock cycles); Lamb: ¶0109, e.g., controller compresses weights by removing zero-weight elements), wherein a number of the plurality clock cycles is same as a number of bits of the compressed weight (Lu: Column 7 Lines 19-21, e.g., decoder activates wordline based on each received input).
The motivation to combine provided with respect to claim 1 applies equally to claim 3.
Regarding Claim 7, Lee in view of Lamb in view of Lu in view of Hoang teach the memory test circuit according to claim 1. Lee in view of Lamb in view of Lu in view of Hoang do not teach:
wherein
the input signal is obtained wordwise at one clock cycle.
However, Hoang further teaches receiving data as word data to be used in non-volatile memory array. Hoang explains “With respect to the number of bits for the input or activation values, for 8-bit values k=0-7 and there are 4 input columns of along the 4 word lines as illustrated in FIG. 13” (Hoang: Column 17 Lines 8-11). See Hoang: Fig. 13 showing input word lines 1311-0 – 1311-3.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the CIM memory array taught by Lee in view of Lamb in view of Lu in view of Hoang to receive input data as word data to be used in the CIM array as taught by Hoang. One would have been motivated to combine these references because both references disclose inputting data to memory arrays, and Hoang enhances the model of Lee in view of Lamb in view of Lu in view of Hoang by allowing for the memory array to process larger data values.
Regarding Claims 11-13, they are method claims practiced by the apparatus of claims 1-3. They are rejected for the same reasons as claims 1-3.
Claim 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lamb in view of Lu in view of Hoang, further in view of Keating (U.S. Patent No.: US 5150321 A), hereinafter “Keating”.
Regarding Claim 4, Lee in view of Lamb in view of Lu in view of Hoang teach:
The memory test circuit according to claim 1, wherein
the weight decoder is configured to obtain the decoded weight bitwise … , respectively, at each clock cycle of a plurality of clock cycles (Lu: Column 7 Lines 15-17, e.g., decoder 212 is used to activate the wordlines in a sequential order (plurality of clock cycles); Lamb: ¶0109, e.g., controller compresses weights by removing zero-weight elements), and
the weight decoder is configured to convert an undetermined bit of the decoded weight to a determined bit based on each bit of the compressed weight, respectively, at the each clock cycle of the plurality of clock cycles (Lu: Fig. 2, e.g., shows Row Pulse Decoder receives data (undetermined bit) from address counter; Column 7, Lines 15-28, e.g., decoder 212 activates wordlines (decoded weights) if a one is applied to the decoder input (weight)).
Lee in view of Lamb in view of Lu in view of Hoang do not specifically teach the order of which the input data is sequentially inputted to the row pulse decoder.
However, Keating teaches a decoder that receives bitwise data serially from MSB to LSB to convert the unsigned redundant binary number into a conventional binary number. Keating explains “a decoding circuit serially converts, from a MSB to a LSB, the unsigned redundant binary number into a conventional binary number” (Keating: Column 2 Lines 15-18).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the row pulse decoder taught by Lee in view of Lamb in view of Lu in view of Hoang to receive bitwise data from MSB to LSB as taught by Keating. One would have been motivated to combine these references because both references disclose decoding of bit data for binary multiplication, and Keating enhances the model of Lee in view of Lamb in view of Lu in view of Hoang by allowing for bit data to be sequentially inputted to a decoder in a specific order.
Regarding Claim 14, it is a method claim practiced by the apparatus of claim 4. It is rejected for the same reasons as claim 4.
Allowable Subject Matter
Claims 5-6, and 8-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Lee teaches a CIM macro for performing multiply-accumulate operations. The CIM macro receives input data and weight data, and further suggests using decoders as input/output circuits. See Lee: Fig. 5, ¶0027, and ¶0039-0044. Lee does not teach or suggest using compressed weight data that includes a prefix, a run-length, and a postfix, where the prefix indicates a MSB of an original weight, the run-length indicates a number of bits right after the MSB of the original weight having the same value as the MSB, and the postfix indicates the data of the original weight that is not represented by the prefix and the run-length, nor does Lee teach or suggest using a weight decoder that is configured to determine the undetermined bit of the decoded weight as zero after a last clock cycle of decoding or to have a same value as the MSB after a last clock cycle of decoding. Instead, Lee teaches using a decoder as input/output circuits, and where the weights are stored in storage cells (not compressed).
Lu teaches an array for performing multiply-accumulate (MAC) operations. Lu further teaches using a row pulse decoder for receiving input data, and activating wordlines in a sequential order based on the input data. See Lu Fig. 2, and Column 7 Lines 4-28. Lu does not teach or suggest using compressed weight data that includes a prefix, a run-length, and a postfix, where the prefix indicates a MSB of an original weight, the run-length indicates a number of bits right after the MSB of the original weight having the same value as the MSB, and the postfix indicates the data of the original weight that is not represented by the prefix and the run-length, nor does Lu teach or suggest using a weight decoder that is configured to determine the undetermined bit of the decoded weight as zero after a last clock cycle of decoding or to have a same value as the MSB after a last clock cycle of decoding. Instead, Lu teaches using a row pulse decoder to activate wordlines in a sequential order, but does not disclose the decoder being configured to determine the undetermined bit of the decoded weight as zero after a last clock cycle of decoding or to have a same value as the MSB after a last clock cycle of decoding. Further, Lu is silent about compressing weight data.
Lamb teaches compressing sparse weight vectors for multiply accumulate operations. Compression of sparse weight vector data includes removing zero-weight elements to vertically compress vectors for compact multiplication by eight MAC elements. See Lamb ¶0079 and Fig. 4E. Lamb does not teach or suggest using compressed weight data that includes a prefix, a run-length, and a postfix, where the prefix indicates a MSB of an original weight, the run-length indicates a number of bits right after the MSB of the original weight having the same value as the MSB, and the postfix indicates the data of the original weight that is not represented by the prefix and the run-length, nor does Lamb teach or suggest using a weight decoder that is configured to determine the undetermined bit of the decoded weight as zero after a last clock cycle of decoding or to have a same value as the MSB after a last clock cycle of decoding. Instead, Lamb teaches compressing weight vector data by removing zero-weight elements, and is silent about using a decoder to process compressed weight data.
Chang et al. (U.S. Patent Application Publication No.: US 20210223852 A1), hereinafter “Chang” – teaches a method for compressing weight parameters and inputting them to a decoding module. Compressing the weight parameter involves truncating the 7th and 6th bits of the weight parameter, and adding a coding bit at the LSB. See Figs. 4-5 and ¶0046-0048. Chang does not teach or suggest using compressed weight data that includes a prefix, a run-length, and a postfix, where the prefix indicates a MSB of an original weight, the run-length indicates a number of bits right after the MSB of the original weight having the same value as the MSB, and the postfix indicates the data of the original weight that is not represented by the prefix and the run-length. Instead, Chang only truncates the 7th and 6th bit positions of the weight parameter, and does not include a run-length indicating the original weight having the same value as the MSB.
Conclusion
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182 (571)272-0474
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