Prosecution Insights
Last updated: October 25, 2026
Application No. 18/163,889

SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF

Final Rejection §103
Filed
Feb 03, 2023
Priority
Dec 26, 2022 — TW 111149960
Examiner
SEHAR, FAKEHA
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hon Hai Precision Industry Co., Ltd.
OA Round
4 (Final)
83%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
86 granted / 104 resolved
+14.7% vs TC avg
Strong +19% interview lift
Without
With
+19.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
37 currently pending
Career history
154
Total Applications
across all art units

Statute-Specific Performance

§103
49.2%
+9.2% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
38.3%
-1.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 104 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment This Office Action is in response to Applicant’s Amendment filed on August 18, 2026. Claim 1 has been amended. No new claims have been added. Claims 7 and 13-20 have been canceled. Currently, claims 1-6 and 8-12 are pending. Applicant’s amendment to claim 1 successfully overcomes the 112(a) rejection of claim 1 and dependent claims set forth in the previous Office Action. Response to Arguments Applicant’s arguments with respect to claim 1 have been considered but are moot as applied to the newly added claim limitation because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Liang (US 2022/0181488 A1) in view of Son (US 2015/0206874 A1), Yasutake (US 2008/0179629 A1) and Yu et al. (CN 103000499 A; hereafter Yu). Regarding claim 1, Liang teaches a semiconductor device (see e.g., Figure 1H), comprising: a substrate (see e.g., substrate 110, Para [0033], Figure 1H) comprises a shallow trench isolation (STI) (see e.g., an isolation structure 112 arranged in the substrate 110, Para [0039], Figure 1H), a first recess and a second recess adjacent to the STI (see e.g. recesses R2 and R1 adjacent to the isolation structure 112, Para [0051], Figures ID and 1H); a first epitaxial structure located in the first recess of the substrate (see e.g., first epitaxial structure, including the epitaxially formed silicon germanium material and the silicon cover layer 160, located in the recess R2 of the substrate 110, Para [0058], Figure 1H); a second epitaxial structure located in the second recess (see e.g., second epitaxial structure located in the recess R1 including the epitaxially formed silicon germanium material and the cover layer 160, Para [0058], Figure 1H), Liang is silent regarding the method of forming the silicon cover layer 160 and therefore, does not preclude the possibility that the cover layer is formed by an epitaxial process. Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to form the silicon cover layer 160 epitaxially as there is no indication of any criticality in the manner of its formation. a gate structure located on the substrate (see e.g., a gate structure 120 located on the substrate 110, Para [0066], Figure 1H), wherein the first recess and the second recess are on opposite sides of the gate structure (see e.g., the recesses R1 and R2 are on opposite sides of the gate structure 120), Liang does not explicitly teach “wherein a volume of the second epitaxial structure is greater than a volume of the first epitaxial structure; … the second recess is deeper than the first recess”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). In a similar field of endeavor Son teaches wherein a volume of the second epitaxial structure is greater than a volume of the first epitaxial structure; … the second recess is deeper than the first recess (see e.g., the source/drain region 150 is formed deeper than the source/drain region 140 as a result the volume of the material in the source/drain region 150 would be greater, Para [0100], Figure 4). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Son’s teaches wherein a volume of the second epitaxial structure is greater than a volume of the first epitaxial structure; … the second recess is deeper than the first recess in the device of Liang in order to optimize device performance as an asymmetric transistor provides better transistor performance. Liang does not explicitly teach “a transition layer interfacing with a bottom surface of the second epitaxial structure, wherein a bottom surface of the first epitaxial structure is free of the transition layer;” In a similar field of endeavor Yasutake addresses the problem of increased junction leakage current caused by deep silicide penetration along gaps formed between shallow trench isolation (STI) 4 and the epitaxially grown SiGe. To solve this, Yasutake teaches forming a SiGe layer 3 via Ge ion implantation into a Si substrate, creating an ion implantation region 3a (which acts as a transition layer) and an epitaxially grown region 3b. Yasutake specifically teaches that the ion-implanted SiGe layer 3a acts as a barrier, preventing the source/drain silicide layer 6 from directly contacting the silicon substrate, thereby preventing unstable ternary compound (NiSiGe) formation that drives deep, undesired silicide penetration. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to modify Liang by applying the ion-implanted transition layer taught by Yasutake selectively below the second epitaxial structure (adjacent to the STI) while keeping the first epitaxial structure free of said layer in order to prevent silicide from penetrating too deeply into the substrate near the isolation region specifically addressing the leakage issues Yasutake identifies. Liang does not explicitly teach “wherein a bottom surface of the transition layer is higher than a bottom surface of the STI;” In a similar field of endeavor Yun teaches wherein a bottom surface of the transition layer is higher than a bottom surface of the STI (see e.g., a silicon substrate 200 having STI regions 207 and source/drain recesses 201 formed in the substrate adjacent to a gate structure. A SiGe seed layer 204 is located at the bottom of the source/drain recess 201 over which a SiGe:B layer 306 is epitaxially grown. The Ge content of the SiGe seed layer 204 is lower than the subsequently grown SiGe:B layer 306 such that the lattice constant of the seed layer 204 is closer to that of the silicon substrate 200. The SiGe seed layer 204 thereby functions as a buffer or transition layer and facilitates formation of a high quality SiGe:B epitaxial layer. As shown in Figure 10 the bottom surface of the SiGe seed layer 204 is higher than the bottom surface of the STI region 207). Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Yun’s teachings of wherein a bottom surface of the transition layer is higher than a bottom surface of the STI in the device of Liang because the relative depth of the transition layer within the source/drain recess constitutes a predictable design choice in configuring the epitaxial source/drain structure. A SiGe seed/transition layer may be formed in a relatively shallow source/drain recess while the STI extends to a greater depth while performing its intended function as a lattice transition buffer for the subsequently grown SiGe epitaxial material. Regarding claim 2, Liang, as modified by Son, Yasutake and Yun, teaches the limitations of claim 1 as mentioned above. Liang further teaches PNG media_image1.png 690 768 media_image1.png Greyscale Modified Figure 1H, Liang wherein a sidewall of the first recesses has a concave portion (see e.g., as shown in modified Figure 1H, the sidewall of recess R2 has a concave portion). Regarding claim 3, Liang, as modified by Son, Yasutake and Yun, teaches the limitations of claim 2 as mentioned above. Liang further teaches wherein the first epitaxial structures has a convex portion, and the convex portion couples with the concave portion of the sidewall (see e.g., as shown in modified Figure 1H the first epitaxial structure has a convex portion coupled with the concave portion of the sidewall of recess R2). Regarding claim 4, Liang, as modified by Son, Yasutake and Yun, teaches the limitations of claim 1 as mentioned above. Liang further teaches wherein a sidewall of the second recess facing the STI has a concave portion (see e.g., as shown in modified Figure 1H, the sidewall of recess R1 facing the STI has a concave portion). Regarding claim 5, Liang, as modified by Son, Yasutake and Yun, teaches the limitations of claim 4 as mentioned above. Liang further teaches wherein the second epitaxial structure has a convex portion, and the convex portion couples with the concave portion of the sidewall of the second recess (see e.g., as shown in modified Figure 1H the second epitaxial structure has a convex portion coupled with the concave portion of the sidewall of recess R1). Regarding claim 10, Liang, as modified by Son, Yasutake and Yun, teaches the limitations of claim 1 as mentioned above. Liang does not explicitly teach “wherein a material of the transition layer comprises germanium”. In a similar field of endeavor Yasutake teaches wherein a material of the transition layer comprises germanium (see e.g., ion implanted SiGe layer 3a formed by implanting Ge ions into the Si substrate 2, Para [0024], Figure 1). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Yasutake’s teachings of wherein a material of the transition layer comprises germanium in the device of Liang in order to prevent silicide from penetrating too deeply into the substrate near the isolation region. Regarding claim 11, Liang, as modified by Son, Yasutake and Yun, teaches the limitations of claim 1 as mentioned above. Liang does not explicitly teach “wherein the second epitaxial structure has a top surface with an arc-shape”. However, the Applicant has not presented persuasive evidence that the claimed “arc-shaped top surface” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without a arc-shaped top surface). Also, the Applicant has not shown that “wherein arc-shaped top surface” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Examiner would like to note that MPEP §2144.04.IV(B) guideline, where change of shape is a Legal Precedent as Source of Supporting Rationale. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant. Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to have a top surface with an arc-shaped as a matter of choice as there is no persuasive evidence that the particular configuration is significant. Regarding claim 12, Liang, as modified by Son, Yasutake and Yun, teaches the limitations of claim 11 as mentioned above. Liang further teaches wherein the top surface of the second epitaxial structure extends from the STI to the gate structure (see e.g., the top surface of the epitaxial structure that is, the top surface of cover layer 160 extends from the isolation structure 112 to the gate structure 12, Figure 1H). Claims 6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Liang (US 2022/0181488 A1) in view of Son (US 2015/0206874 A1), Yasutake (US 2008/0179629 A1) and Yun et al. (CN 103000499 A; hereafter Yun) and further in view of Kwok et al. (US 2015/0236157 A1; hereafter Kwok). Regarding claim 6, Liang, as modified by Son, Yasutake and Yun, teaches the limitations of claim 1 as mentioned above. Liang further teaches wherein the first epitaxial structures comprises: a first epitaxial layer located at a bottom portion of the first recesses (see e.g., recess R2 has a silicon germanium layer located at a bottom portion of the recess, Para [0058], Figure 1H); and a second epitaxial layer (see e.g., silicon cover layer 160, Para [0061], Figure 1H). Liang does not explicitly teach “a doped layer located on the first epitaxial layer; and a second epitaxial layer located on the doped layer”. In a similar field of endeavor Kwok teaches a doped layer (see e.g., boron doped SiGe region 110, Para [0014], Figure 1) located on the first epitaxial layer (see e.g., doped SiGe region 110 located on undoped SiGe region 112, Para [0014], Figure 1); and a second epitaxial layer located on the doped layer (see e.g., silicon cap layer 114 located on doped SiGe region 110, Para [0023], Figure 1) Therefore, it would have been obvious to one skilled in art at the time the invention was effectively field to implement Kwok’s teachings of a doped layer located on the first epitaxial layer; and a second epitaxial layer located on the doped layer in the device of Liang to limit short channel effects. Regarding claim 8, Liang, as modified by Son, Yasutake and Yun, teaches the limitations of claim 1 as mentioned above. Liang further teaches wherein the second epitaxial structure comprises: a first epitaxial layer (see e.g., recess R1 has a silicon germanium layer located at a bottom portion of the recess, Para [0058], Figure 1H); and a second epitaxial layer (see e.g., silicon cover layer 160, Para [0061], Figure 1H). Liang does not explicitly teach “a first epitaxial layer located on the transition layer” In a similar field of endeavor Yasutake teaches a first epitaxial layer located on the transition layer (see e.g., SiGe layer 3, having an epitaxial SiGe layer 3b grown by epitaxial process on an ion implanted region 3a formed by implanting a Ge ion into the Si substrate 2, Para [0024], Figure 1). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Yasutake’s teachings of a first epitaxial layer located on the transition layer in the device of Liang to prevent silicide from penetrating too deeply into the substrate near the isolation region. Liang does not explicitly teaches “a doped layer located on the first epitaxial layer; a second epitaxial layer located on the doped layer”. In a similar field of endeavor Kwok teaches a doped layer (see e.g., boron doped SiGe region 110, Para [0014], Figure 1) located on the first epitaxial layer (see e.g., doped SiGe region 110 located on undoped SiGe region 112, Para [0014], Figure 1); and a second epitaxial layer located on the doped layer (see e.g., silicon cap layer 114 located on doped SiGe region 110, Para [0023], Figure 1) Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Kwok’s teachings of a doped layer located on the first epitaxial layer; and a second epitaxial layer located on the doped layer in the device of Liang to limit short channel effects. Regarding claim 9, Liang, as modified by Son, Yasutake, Yun and Kwok, teaches the limitations of claim 8 as mentioned above. Liang further teaches wherein a material of the first epitaxial layer comprises silicon germanium (see e.g., the material of the epitaxial layer in the S/D region 152 is SiGe, Para [0058], Figure 1H), and a material of the second epitaxial layer comprises silicon and without germanium (see e.g., the cover layer 160 includes silicon, Para [0061], Figure 1H). Liang does not explicitly teach “a material of the doped layer comprises silicon germanium and boron,” In a similar field of endeavor Kwok teaches a material of the doped layer comprises silicon germanium and boron (see e.g., boron doped SiGe region 110, Para [0014], Figure 1), Therefore, it would have been obvious to one skilled in art at the time the invention was effectively field to implement Kwok’s teachings of a material of the doped layer comprises silicon germanium and boron in the device of Liang to limit short channel effects. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAKEHA SEHAR whose telephone number is (571)272-4033. The examiner can normally be reached Monday-Thursday 7:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAKEHA SEHAR/ Examiner, Art Unit 2893 /YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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Prosecution Timeline

Show 2 earlier events
Oct 23, 2025
Response Filed
Dec 19, 2025
Final Rejection mailed — §103
Mar 09, 2026
Response after Non-Final Action
Apr 20, 2026
Request for Continued Examination
Apr 24, 2026
Response after Non-Final Action
Jun 10, 2026
Non-Final Rejection mailed — §103
Aug 18, 2026
Response Filed
Sep 30, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+19.3%)
3y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 104 resolved cases by this examiner. Grant probability derived from career allowance rate.

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