Prosecution Insights
Last updated: April 17, 2026
Application No. 18/164,122

METHODS AND DEVICES FOR DEFEATING BUFFER OVERFLOW PROBLEMS IN MULTI-CORE PROCESSORS

Final Rejection §112
Filed
Feb 03, 2023
Examiner
VICARY, KEITH E
Art Unit
2183
Tech Center
2100 — Computer Architecture & Software
Assignee
unknown
OA Round
4 (Final)
58%
Grant Probability
Moderate
5-6
OA Rounds
3y 8m
To Grant
99%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allow Rate
393 granted / 683 resolved
+2.5% vs TC avg
Strong +41% interview lift
Without
With
+41.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
41 currently pending
Career history
724
Total Applications
across all art units

Statute-Specific Performance

§101
8.7%
-31.3% vs TC avg
§103
34.0%
-6.0% vs TC avg
§102
12.0%
-28.0% vs TC avg
§112
37.6%
-2.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 683 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1, 4-7, 9-10, 15, 18-22, and 27-30 are pending in this office action and presented for examination. Claims 1, 4-5, 7, 9, 15, 18-19, 21-22, and 27-30 are newly amended, and claims 2-3, 8, and 16-17 are newly cancelled, by the response received December 15, 2025. In claim 15, line 5, there may be two spaces between “and” and “a predictive branch controller”. Examiner notes there may be other instances of two spaces between words (e.g., two spaces between “receiving” and “decrypted” in claim 4, line 3). Claim Objections Claims 7, 9-10, and 21-22 are objected to because of the following informalities. Appropriate correction is required. Claim 7 recites the limitation “the plurality of level one caches is” in lines 1-2. Claim 4, upon which claim 7 is indirectly dependent, recites the limitation “the plurality of level one caches are” in lines 1-2. However, the use of “is” or “are” in the aforementioned context should be consistent for grammatical clarity. Claims 9-10 are objected to for failing to alleviate the objection of claim 7 above. Claim 21 recites the limitation “the plurality of level one caches is” in lines 1-2. Claim 18, upon which claim 21 is indirectly dependent, recites the limitation “the plurality of level one caches are” in lines 1-2. However, the use of “is” or “are” in the aforementioned context should be consistent for grammatical clarity. Claim 22 is objected to for failing to alleviate the objection of claim 21 above. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1, 4-7, 9-10, 15, 18-22, and 27-30 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites the limitation “a predictive branch controller” in line 8. However, the original disclosure does not appear to provide support for this limitation. Note that a claim may lack written description support when a broad genus claim is presented but the original disclosure only describes a narrow species with no evidence that the genus is contemplated. In the instant case, the original disclosure (e.g., Applicant-cited paragraphs [0117], [0118], [0135], and [0136], and FIG. 6) only describes a narrow species (“cache & predictive branch controller”) with no evidence that the genus (“a predictive branch controller”) is contemplated. For example, while the inventor, at the time the application was filed, may have had possession of an invention that entailed a “cache & predictive branch controller”, Examiner submits that the original disclosure, at the time the application was filed, does not reflect the inventor having possession of an invention that entailed or needed only a “predictive branch controller” but not necessarily a “cache & predictive branch controller”. Note that the limitation “predictive branch controller” is also recited in claim 1, line 12; claim 28, line 2; claim 28, line 3; and claim 28, line 5. Claim 1 recites the limitation “each decryption circuit of the plurality of decryption circuits is configured to accept and decrypt a single data transfer on a sequential basis to a target processor core of the plurality of processor cores under direction the predictive branch controller” in lines 10-12. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [000101], [000131], as well as Applicant-cited paragraphs [0117], [0118], [0135], and [0136], and FIG. 6) does not appear to provide support for each decryption circuit of the plurality of decryption circuits being configured to accept and decrypt a single data transfer on a sequential basis “to a target processor core of the plurality of processor cores” “under direction the predictive branch controller”. Claims 4-7, 9-10, and 27-28 are rejected for failing to alleviate the rejections of claim 1 above. Claim 15 recites the limitation “a predictive branch controller” in line 5. However, the original disclosure does not appear to provide support for this limitation. Note that a claim may lack written description support when a broad genus claim is presented but the original disclosure only describes a narrow species with no evidence that the genus is contemplated. In the instant case, the original disclosure (e.g., Applicant-cited paragraphs [0117], [0118], [0135], and [0136], and FIG. 6) only describes a narrow species (“cache & predictive branch controller”) with no evidence that the genus (“a predictive branch controller”) is contemplated. For example, while the inventor, at the time the application was filed, may have had possession of an invention that entailed a “cache & predictive branch controller”, Examiner submits that the original disclosure, at the time the application was filed, does not reflect the inventor having possession of an invention that entailed or needed only a “predictive branch controller” but not necessarily a “cache & predictive branch controller”. Note that the limitation “predictive branch controller” is also recited in claim 15, line 12; claim 30, line 2; claim 30, line 3; and claim 30, line 5. Claim 15 recites the limitation “providing to each decryption circuit of the plurality of decryption circuits a single data transfer on a sequential basis to a target processor core of the plurality of processor cores under direction the predictive branch controller” in lines 10-12. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [000101], [000131], as well as Applicant-cited paragraphs [0117], [0118], [0135], and [0136], and FIG. 6) does not appear to provide support for providing to each decryption circuit of the plurality of decryption circuits a single data transfer on a sequential basis “to a target processor core of the plurality of processor cores” “under direction the predictive branch controller”. Claims 18-22 and 29-30 are rejected for failing to alleviate the rejections of claim 15 above. Claim 22 recites the limitation “the encryption circuit is electrically coupled between the external memory interface and the plurality of processor cores” in lines 3-4. Claim 15, upon which claim 22 is indirectly dependent, recites the limitation “a plurality of decryption circuits electrically coupled between the external memory interface and the plurality of level one caches” in lines 3-5. However, the original disclosure does not appear to provide support for this collective subject matter. For example, the original disclosure (e.g., paragraphs [00056], [00062], [00085], [000100], and [000107]) does not appear to provide support for an embodiment wherein a plurality of decryption circuits are electrically coupled between the external memory interface and the plurality of level one caches and the encryption circuit is electrically coupled elsewhere between the external memory interface and the plurality of processor cores (e.g., between the plurality of level one caches and the plurality of processor cores), which is a scenario encompassed by the claim language. Claim 28 recites the limitation “The multicore processor IC of claim 1 further comprising a predictive branch controller” in lines 1-2. Claim 1, upon which claim 28 is dependent, recites the limitation “the multicore processor IC comprising: … a predictive branch controller” in lines 2-8. However, the original disclosure does not appear to provide support for this collective subject matter. For example, the original disclosure (e.g., Applicant-cited paragraphs [0117], [0118], [0135], and [0136], and FIG. 6) does not appear to provide support for the multicore processor IC comprising two predictive branch controllers. Claim 30 recites the limitation “The method of claim 15, wherein: the multicore processor IC further comprises a predictive branch controller” in lines 1-2. Claim 15, upon which claim 30 is dependent, recites the limitation “a multicore processor integrated circuit (IC) comprising … a predictive branch controller” in lines 1-5. However, the original disclosure does not appear to provide support for this collective subject matter. For example, the original disclosure (e.g., Applicant-cited paragraphs [0117], [0118], [0135], and [0136], and FIG. 6) does not appear to provide support for the multicore processor IC comprising two predictive branch controllers. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1, 4-7, 9-10, 15, 18-22, and 27-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “the plurality of process cores” in line 8. However, there is insufficient antecedent basis for this limitation in the claims. Claim 1 recites the limitation “direction the predictive branch controller” in line 12. However, it is indefinite as to what is being grammatically conveyed by the above language. Claims 4-7, 9-10, and 27-28 are rejected for failing to alleviate the rejections of claim 1 above. Claim 15 recites the limitation “the plurality of process cores” in line 5. However, there is insufficient antecedent basis for this limitation in the claims. Claim 15 recites the limitation “direction the predictive branch controller” in line 12. However, it is indefinite as to what is being grammatically conveyed by the above language. Claim 15 recites the limitation “providing to each decryption circuit of the plurality of decryption circuits a single data transfer on a sequential basis to a target processor core of the plurality of processor cores under direction the predictive branch controller” in lines 10-12. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether the single data transfer is being provided to each decryption circuit or to a target processor core. Claims 18-22 and 29-30 are rejected for failing to alleviate the rejections of claim 15 above. Claim 28 recites the limitation “a predictive branch controller” in lines 1-2. However, it is indefinite as to whether this predictive branch controller is the same as, or different from, “a predictive branch controller” as recited in claim 1, line 8. Claim 28 recites the limitation “the predictive branch controller” in line 3. However, it is indefinite as to whether this limitation has antecedent basis to “a predictive branch controller” as recited in claim 1, line 8, or “a predictive branch controller” as recited in claim 28, lines 1-2. Note that this limitation is also recited in claim 28, line 5. Claim 28 recites the limitation “the predictive branch controller is distinct from the plurality of processor cores” in line 3. Claim 1, upon which claim 28 is dependent, recites the limitation “a predictive branch controller positioned external to the plurality of process cores” in line 8. However, it is indefinite as to whether being “distinct from” is the same as, or different than, being “external to”. Claim 30 recites the limitation “a predictive branch controller” in line 2. However, it is indefinite as to whether this predictive branch controller is the same as, or different from, “a predictive branch controller” as recited in claim 15, line 5. Claim 30 recites the limitation “the predictive branch controller” in line 3. However, it is indefinite as to whether this limitation has antecedent basis to “a predictive branch controller” as recited in claim 15, line 5, or “a predictive branch controller” as recited in claim 30, line 2. Note that this limitation is also recited in claim 30, line 5. Claim 30 recites the limitation “the predictive branch controller is distinct from the plurality of processor cores” in line 3. Claim 15, upon which claim 30 is dependent, recites the limitation “a predictive branch controller positioned external to the plurality of process cores” in line 5. However, it is indefinite as to whether being “distinct from” is the same as, or different than, being “external to”. The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claims 7 and 21 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim 7 recites the limitation “The multicore processor IC of claim 5, wherein the plurality of level one caches is further configured to receive the un-decrypted instructions from the external memory interface” in lines 1-3. Claim 4, upon which claim 7 is indirectly dependent, recites the limitation “the plurality of level one caches are configured for: … receiving un-decrypted instructions from the external memory interface” in lines 1-6. Therefore, claim 7 fails to further limit the subject matter of the claim upon which it depends. Claim 21 recites the limitation “The method of claim 19, wherein the plurality of level one caches is further configured to receive the un-decrypted instructions from the external memory interface” in lines 1-3. Claim 18, upon which claim 21 is indirectly dependent, recites the limitation “the plurality of level one caches are configured for: … receiving un-decrypted instructions from the external memory interface” in lines 1-6. Therefore, claim 21 fails to further limit the subject matter of the claim upon which it depends. Response to Arguments Applicant on page 11 argues: “Paragraph [00136], line 3, has been corrected as required. No new matter has been added.” In view of the aforementioned correction, the previously presented objection to the specification is withdrawn. Applicant on page 15 argues: “As such, amended claim 1 is allowable under 35 USC § 112. In view of the amendments to claim 1 (reproduced on pages 11-12 of the remarks), the previously presented rejections of claim 1 under 35 USC § 112 are withdrawn. However, the amendments to claim 1 appears to catalyze additional issues under 35 USC § 112 — see the Claim Rejections - 35 USC § 112 section above. Applicant on page 15 argues: “Claim 3 has been canceled rendering its rejection under 35 USC § 112 moot.” In view of the aforementioned cancellation of claim 3, the rejection of claim 3 under 35 USC § 112 is withdrawn. Applicant on page 15 argues: “Claim 15 has been amended in a similar fashion to claim 1 to remove selection circuitry comprising a hardware latch. As such, amended claim 15 is also allowable under 35 USC § 112.” In view of the amendments to claim 15, the previously presented rejection of claim 15 under 35 USC § 112 is withdrawn. However, the amendments to claim 15 appears to catalyze additional issues under 35 USC § 112 — see the Claim Rejections - 35 USC § 112 section above. Applicant on page 15 argues: “Claim 17 has been canceled rendering its rejection under 35 USC § 112 moot.” In view of the aforementioned cancellation of claim 17, the rejection of claim 17 under 35 USC§ 112 is withdrawn. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH E VICARY whose telephone number is (571)270-1314. The examiner can normally be reached Monday to Friday, 9:00 AM to 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571)270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEITH E VICARY/Primary Examiner, Art Unit 2183
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Prosecution Timeline

Feb 03, 2023
Application Filed
Jun 06, 2024
Non-Final Rejection — §112
Dec 10, 2024
Response Filed
Dec 30, 2024
Final Rejection — §112
Apr 09, 2025
Applicant Interview (Telephonic)
Apr 09, 2025
Examiner Interview Summary
May 05, 2025
Request for Continued Examination
May 09, 2025
Response after Non-Final Action
Jun 02, 2025
Non-Final Rejection — §112
Oct 06, 2025
Response Filed
Oct 06, 2025
Response after Non-Final Action
Dec 15, 2025
Response Filed
Jan 14, 2026
Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
58%
Grant Probability
99%
With Interview (+41.2%)
3y 8m
Median Time to Grant
High
PTA Risk
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