DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 02/09/2026 has been entered. Claim 9 was canceled by Applicant.
Claims 10-14 are withdrawn. Claims 1-8 and 10-14 are pending.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 02/09/2026, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with a new reference, US 20190027600 A1 to Jang, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ker et al. (US 20080151446 A1, hereinafter Ker, of the record) in view of Jang et al. (US 20190027600 A1, hereinafter Jang).
Re: Independent Claim 1, Ker discloses an Electro-Static Discharge (ESD) protection circuit (Fig. 16B), comprising:
a p-type substrate (p-substrate in [0077], Fig. 16B);
a p-type well (p-well, Fig. 16B) formed on the p-type substrate (p-substrate);
a first Negative channel Metal Oxide Semiconductor (NMOS) transistor (1620 gate of a NMOS transistor connected to a ground voltage trace 1602 in [0078, 0079], Fig. 16B) and a second NMOS transistor (1621 gate of a NMOS transistor connected to a voltage VDD in [0078, 0079], Fig. 16B) formed in the p-type well (p-well), wherein a drain (1612-D a half of N+ doped regions 1612 corresponding to a drain of 1620 in [0082], Fig. 16B-Annotated) of the first NMOS transistor (1620) is connected to a source (1612-S a half of N+ doped regions 1612 corresponding to a source of 1621 in [0082], Fig. 16B-Annotated) of the second NMOS transistor (1621); and
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Ker’s Figure 16B-Annotated.
Ker does not expressly disclose a Lightly Doped Drain (LDD) region formed only in proximity to a source of the first NMOS transistor (1620).
However, in the same semiconductor device field of endeavor, Jang discloses a Lightly Doped Drain (LDD) region (142 N-type asymmetric LDD in [0044], Fig. 1A) formed only in proximity to a source (source/drain region 152, Fig. 1A) of the first NMOS transistor (NMOS device, in [0044], Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jang’s feature of a Lightly Doped Drain (LDD) region formed only in proximity to a source of the first NMOS transistor to Ker’s device for reducing the electric field and restrains the generation of hot carriers, which is beneficial in terms of reliability ([0044], Jang).
Re: Claim 2, Ker modified by Jang discloses the ESD protection circuit of claim 1, further comprising a first p+ doped region (1604 a first doped region in [0077], Fig. 16B Ker) and a second p+ doped region (1630 a second doped region in [0077], Fig. 16B Ker) that are formed in the p-type well (p-well Fig. 16B Ker), wherein the first p+ doped region (1604 Ker) is disposed in proximity to the source (1611 Ker) of the first NMOS transistor (1620 Ker), and the second p+ doped region (1630 Ker) is disposed in proximity to a drain (1613 a N+ doped regions corresponding to a drain of 1621 in [0078], Fig. 16B Ker) of the second NMOS transistor (1621 Ker).
Claim(s) 3-8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ker in view of Jang and further in view of Grad et al. (US 20200219867 A1, hereinafter Grad, of the record).
Re: Claim 3, Ker modified by Jang discloses the ESD protection circuit of claim 2, further comprising a target parasitic Bipolar Junction Transistor (BJT) (a lateral parasitic bipolar junction transistor (BJT) in [0008], Fig. 16B, Ker) formed in the p-type well (p-well, Ker),
Ker modified by Jang does not expressly disclose wherein a base of the target parasitic BJT is connected to one end of a parasitic resistor, and the other end of the parasitic resistor is connected to the second p+ doped region; an emitter of the target parasitic BJT is connected to the drain of the second NMOS transistor; and a collector of the target parasitic BJT is connected to the source of the first NMOS transistor.
However, in the same semiconductor device field of endeavor, Grad discloses wherein a base of the target parasitic BJT (BJT Fig. 3-Annotated) is connected to one end of a parasitic resistor (319 a resistor in [0021], Fig. 3), and the other end of the parasitic resistor (a base of a parasitic bipolar transistor connected to a resistor 319 in [0021], Fig. 3) is connected to the second p+ doped region (314 a P+ region in [0019], Fig. 3); an emitter of the target parasitic BJT is connected to the drain of the second NMOS transistor (an emitter formed by the N+ source region of the ESD bypass transistor N3, connected to a drain region 313 of N3 in [0021], Fig. 3); and a collector of the target parasitic BJT is connected to the source of the first NMOS transistor (a collector formed by the N+ drain region of the output driver transistor N1, connected to a source region 311 of N1 in [0021], Fig. 3).
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Grad’s Figure 3-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Grad’s feature wherein a base of the target parasitic BJT is connected to one end of a parasitic resistor, and the other end of the parasitic resistor is connected to the second p+ doped region; an emitter of the target parasitic BJT is connected to the drain of the second NMOS transistor; and a collector of the target parasitic BJT is connected to the source of the first NMOS transistor to Ker’s device to protect the circuit underneath and will limit the gate-drain voltage of the I/O-facing driver transistor ([0010], Grad).
Re: Claim 4, Ker modified by Jang and Grad discloses the ESD protection circuit of claim 3, wherein a Shallow Trench Isolation (STI) structure (trench between 1611 and 1604 formed by a field oxide layer in [0080], Fig. 16B) is formed between the first p+ doped region (1604, Ker) and the source (1611, Ker) of the first NMOS transistor (1620, Ker); and a second STI structure (trench between 1613 and 1630 formed by a field oxide layer in [0080], Fig. 16B) is formed between the second p+ doped region (1630, Ker) and the drain (1613, Ker) of the second NMOS transistor (1621, Ker).
Re: Claim 5, Ker modified by Jang and Grad discloses the ESD protection circuit of claim 4, wherein a resistance of the parasitic resistor (resistor 319 in [0021], Grad, Fig. 3) is associated with a length of a path (as well know the resistance of a resistor is associated to length of the cable or path) between the drain (313, Grad, Fig. 3) of the second NMOS transistor (N3, Grad, Fig. 3) and the second p+ doped region (314, Grad, Fig. 3).
Re: Claim 6, Ker modified by Jang and Grad discloses the ESD protection circuit of claim 5,
Ker modified by Jang and Grad does not expressly disclose wherein the length of the path is associated with a depth of the second STI structure.
However, in the same semiconductor device field of endeavor, Grad discloses wherein the length of the path is associated with a depth (wherein the depth of the trench 304 increase the length of the path is increased as well, Fig. 3) of the second STI structure (304 isolation region in [0021], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Grad’s feature wherein the length of the path is associated with a depth of the second STI structure to Ker’s device to protect the circuit underneath and will limit the gate-drain voltage of the I/O-facing driver transistor ([0010], Grad).
Re: Claim 7, Ker modified by Jang and Grad discloses the ESD protection circuit of claim 6, wherein: when the depth of the second STI structure (304, Grad) increases, the length of the path increases; and when the depth of the second STI structure (304, Grad) decreases, the length of the path decreases (wherein the depth of the trench 304 increase the length of the path is increased as well, Fig. 3, Grad).
Re: Claim 8, Ker modified by Jang and Grad discloses ESD protection circuit of claim 3, wherein the ESD protection circuit is provided with a first power supply terminal (1602 a ground voltage trace in [0077,0079], Fig. 16B, Ker), a second power supply terminal (1601 a first conductive path in [0079], Fig. 16B, Ker) and a third power supply terminal (VDD a system voltage in [0079], Fig. 16B, Ker), wherein a gate of the first NMOS transistor (1620, Ker), the source (1611, Ker) of the first NMOS transistor (1620, Ker), the first p+ doped region (1604 connected to ground voltage, Fig. 16B, Ker) and the second p+ doped region (1630 connected to the bases of the internal parasitic transistor, then connected to 1602 in [0084], Fig. 16B, Ker) are all connected (Fig. 16B, Ker) to the first power supply terminal (1602, Ker); the drain (1613, Ker) of the second NMOS transistor (1621, Ker) is connected to the second power supply terminal (1601, Ker); and a gate of the second NMOS transistor (1621, Ker) is connected to the third power supply terminal (VDD, Ker).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ouyang et al. (US 9105477 B2) teaches “ESD PROTECTION STRUCTURE AND ESD PROTECTION CIRCUIT”. This document is related to an electrostatic discharge (ESD) protection structure and an ESD protection circuit. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. A second doped base region located in the fourth region of the first P-type well region is P-type doped and connected to the external trigger-voltage adjustment circuit.
Habasaki (US 20100193869 A1) teaches “SEMICONDUCTOR DEVICE HAVING ELECTRO-STATIC DISCHARGE PROTECTION ELEMENT”. This document is related to a semiconductor device including a semiconductor substrate of a first conductivity-type, a buried diffusion layer of a second conductivity-type formed in the semiconductor substrate, a first well of the second conductivity-type having a bottom portion in contact with a top portion of the buried diffusion layer, the first well having an annular shape in a planar view, and a second well of the first conductivity-type formed to be surrounded by the first well. The semiconductor device further includes a diffusion region formed between a first portion of the second well and a second portion of the second well, the diffusion region having an impurity concentration lower than that of the second well, so that a depletion layer formed in the diffusion region can be provided, a transistor formed on the second well to function as an ESD (electro-static discharge) protection element, and an external terminal connected to a drain of the transistor.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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