DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 10/25/2025. Claims 1-15 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 05/17/2023.
Oath/Declaration
The oath or declaration filed on 03/30/2023 is acceptable.
Election/Restrictions
Applicant’s election of invention I, species. V, (Fig. [5]): claims 1-7 in the reply filed on 10/25/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)). The election is without traverse because the response is incomplete.
This office action considers claims 1-15 pending for prosecution, wherein claims 8-15 are withdrawn from further consideration, and 1-7 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2003/0230786 A1; hereafter Kim).
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Regarding claim 1. Kim discloses a semiconductor device (Fig [1-2]), comprising:
a substrate (Fig [1-2], substrate 100, Para [ 0032]), comprising a first surface and a second surface opposite to each other (Fig 1, substrate 100, upper/lower surface, Para [ 0032]);
a gate (Fig [1-2], gate structures 150 Para [ 0032]), located on the first surface of the substrate (Fig 1, substrate 100, Para [ 0032]);
a source region and a drain region (Fig 1, source/drain junctions 105, Para [ 0033]), the source region (source/drain junctions 105, Para [ 0033]) being located in the substrate (Fig 1, substrate 100, Para [ 0032]) on one side of the gate (gate structures 150 Para [ 0032]), and the drain region (source/drain junctions 105, Para [ 0033]) being located in the substrate (Fig 1, substrate 100, Para [ 0032]) on another side of the gate (Fig 1, gate structures 150); and at least one anti-punchthrough structure (Fig 1, junction isolation insulating layers 125, construed as anti- punchthrough structure, based on the insulating material, Para [ 0035]), located in the substrate (Fig 1, substrate 100, Para [ 0032]) and comprising a third surface and a fourth surface opposite to each other (Fig 1, junction isolation insulating layers 125, upper/lower surface), wherein the third surface (Fig 1, junction isolation insulating layers 125, upper surface) is adjacent to the first surface and lower than the first surface (Fig 1, upper surface of substrate 100, Para [ 0032]), and the anti-punchthrough structure (Fig 1, junction isolation insulating layers 125) is located between the source region and the drain region (source/drain junctions 105, Para [ 0033]).
Regarding claim 3. Kim discloses the semiconductor device of claim 1, Kim further discloses wherein the anti-punchthrough structure is T-shaped (Para [ 0035] discloses “The junction isolation insulating layers 125 are buried in the silicon substrate 100 and are vertically arranged under the gate structures 150 in the active region to form a T-shape with the channel regions”); and a width of the third surface of the anti-punchthrough structure is greater than a width of the fourth surface (T-shaped junction isolation insulating layers 125) .
Regarding claim 7. Kim discloses the semiconductor device of claim 1, Kim further discloses wherein a material of the anti-punchthrough structure comprises an insulation material (Fig 1, junction isolation insulating layers 125, construed as anti- punchthrough structure, Para [ 0035]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2003/0230786 A1; hereafter Kim).
Regarding claim 2. Kim discloses the semiconductor device of claim 1, Kim further discloses wherein the anti-punchthrough structure (Fig 1, junction isolation insulating layers 125, construed as anti- punchthrough structure, Para [ 0035]) is located below the gate (Fig 1, gate structures 150).
But Kim does not disclose explicitly a distance between the anti-punchthrough structure and the source region being equal to a distance between the anti-punchthrough structure and the drain region.
However, Kim discloses “The junction isolation insulating layer 125 are preferably below substantially the central region of the gate structures 150 and are formed of an insulating layer to isolate the source and drain junctions 105 in a lateral direction”, Para [0011] and Fig [1-2] shows junction isolation insulating layers 125 are substantially equal distance formed between source/ drain regions 105. Therefore, it is obvious that, the distance between junction isolation insulating layers 125 and source, and between junction isolation insulating layers 125 and drain can be same.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify KIM equal distance between junction isolation insulating layers 125 and source and drain region in order to isolates source and drain junction to prevent lateral diffusion or junction expansion in the channel area.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2003/0230786 A1; hereafter Kim) as applied claims above and further in view of Moll et al (US 2016/0268431 A1; hereafter Moll).
Regarding claim 6. Kim discloses the semiconductor device of claim 1, But Kim does not disclose explicitly wherein a distance between the third surface of the anti-punchthrough structure and the first surface of the substrate is greater than 50 angstroms.
In a similar field of endeavor, Moll discloses wherein a distance between the third surface of the anti-punchthrough structure and the first surface of the substrate is greater than 50 angstroms (claim 7discloses “a buried insulating material region disposed in said active region under said gate structure at a depth in a range from about 10-20 nm in said active region”. Therefore, the depth can be greater than 50 angstroms).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Kim in light of Moll teaching “wherein a distance between the third surface of the anti-punchthrough structure and the first surface of the substrate is greater than 50 angstroms (claim 7discloses “a buried insulating material region disposed in said active region under said gate structure at a depth in a range from about 10-20 nm in said active region”. Therefore, the depth can be greater than 50 angstroms)” for further advantage such isolates source and drain region to prevent lateral diffusion or junction expansion in the channel area.
Allowable Subject Matter
Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 4. wherein the semiconductor device comprises two anti-punchthrough structures, each of the two anti-punchthrough structures is located below the gate, wherein a distance between the anti-punchthrough structure adjacent to the source region and the source region is equal to a distance between the anti-punchthrough structure adjacent to the drain region and the drain region.
Regarding claim 5. wherein the semiconductor device comprises a plurality of anti-punchthrough structures, the plurality of anti-punchthrough structures are symmetrically distributed with respect to a central axis of the gate, wherein distances between the anti-punchthrough structures and the first surface successively increase in a direction from the central axis to the source region or the drain region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898