DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-7 and 10-20 are pending in the application and are currently being examined. Claims 1, 4, and 7 have been amended. Claims 8 and 9 have been canceled. Claims 10-20 have been withdrawn per the 10/24/2025 restriction election. No new claims have been added.
Response to Arguments
Applicant's arguments filed 3/23/2026 have been fully considered but they are not persuasive.
Regarding Applicant argument that Yang teaches a dummy structure that cannot be connected electrically to any conductive component, Examiner respectfully disagrees. Yang discloses that the channels 160 may be formed similar to 150. When 160 is formed like 150, 160 is no longer a dummy channel structure, but a channel structure. As such, the channel 160 would no longer be merely a structural pillar, but a channel used in device operation.
While Yang does state in [0060] that these similarly formed channel structures do not have the top portions containing channel contact structures, the element referenced is in the annotated Fig. 3G below. The structural reason to exclude the specific top portion channel contact structure is simply due to the fact that that particular top channel layer (121) does not exist in the entire staircase region of Yang.
The exclusion of the top portion channel contact structure does not preclude electrical contact in lower levels, such as the lower channel contact structure corresponding to layer 126 in Yang and a conductive pillar as in the combined device of Yang in view of Luo in reference to dependent claim 9 in the non-final of 2/5/2026.
With the channel structures 160 penetrating into lower levels of the device compared to channel structures 150, the channel structures are modified to contain a conductive pillar as in Luo in order for electrical communication with lower devices, as in the rejection of claim 9 in the non-final of 2/5/2026, and restated in the rejection to follow. The rejection below will include more annotated figures to further clarify the argument.
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Regarding the currently pending rejection of claims 1-9 under 35 U.S.C 112, amendments to claims 1, 4, and 7 overcome the rejection, and said rejection is withdrawn.
Regarding the currently pending objection to the specification, amendments to the title and noted paragraphs are sufficient to remedy issues, and the objections are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2022/0406805 A1, hereafter Yang) in view of Luo et al. (US 2022/0406719 A1, hereafter Luo).
Regarding claim 1, in Fig. 3H Yang discloses a semiconductor structure for a three-dimensional (3D) memory, comprising:
a substrate (110, [0054]), having a memory array region and a staircase region (see annotated Fig. 3H);
an insulating layer (bottommost layer 131, [0054]), disposed on the substrate (110);
a stacked structure (120A, [0054]), dispose on the insulating layer (bottommost layer 131), wherein the stacked structure (120A) comprises a plurality of first dielectric layers (131, [0054]) separated from each other, and the stacked structure (120A) in the staircase region has a staircase profile;
a vertical channel structure (150, [0059]), disposed in the stacked structure (120A) in the memory array region, and penetrating through the stacked structure (120A),
wherein there is a vertical hole (see annotated Fig. 3B) in the stacked structure (120A) and the insulating layer (bottommost layer 131) in the staircase region, and a third dielectric layer (160, [0060]) is filled in the vertical hole. Dummy channel 160 is described as similar to channel structures 150 [0060]. channel structures 150 have a filler material 153 made of silicon oxide [0059], making it a dielectric in the vertical hole.
While Yang fails to explicitly disclose a device structure layer disposed between the substrate (110, [0054]) and the insulating layer (bottommost layer 131, [0054]), the substrate is described as a multi-layered substrate [0055]. One of ordinary skill in the art could call the topmost layer 111 as the device structure layer (see annotated Fig. 3H). The vertical hole (see annotated Fig. 3B) exposes the device structure layer (topmost layer 111 has side surfaces exposed by the hole).
Yang fails to teach a conductive pillar disposed in the third dielectric layer and electrically connected to the device structure layer.
However, in Fig. 1E Luo teaches a similar device in which the staircase region (105, [0032]) has third dielectric regions (liners material 148, [0056]) with a conductive pillar disposed into it (first material 146, a conductive material, [0058]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the third dielectric layer of Yang to include the conductive material of Luo in order to allow for electrical communication below the device as Luo states in [0056].
Note that the conductive pillar of Yang in view of Luo is in electrical contact with the channel in layer 126 of Yang through the conductive channel layer 152 and the layer 110 of Yang.
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Regarding claim 2, Yang in view of Liou discloses the semiconductor structure for a 3D memory of claim 1. Yang further teaches in Fig. 3H the first dielectric layer (131, [0054]) comprises an oxide layer. Dielectric layer 131 can be formed of silicon oxide [0056].
Regarding claim 3, Yang in view Liou discloses the semiconductor structure for a 3D memory of claim 1. Yang further teaches in Fig. 3H the third dielectric layer (160, [0060]) comprises an oxide layer. As stated in claim 1, channel 160 is described as similar to channel structures 150 [0060], which has a filler material 153 made of silicon oxide [0059].
Regarding claim 4, Yang in view of Liou discloses the semiconductor structure for a 3D memory of claim 1. Yang further teaches in Fig. 3H the stacked structure (120A, [0054]) in the memory array region (see annotated Fig. 3H) has a vertical channel hole, and the vertical channel structure is disposed in the vertical channel hole. Referring to Figs. 3A and 3B, as the stacked structure 120A is formed before the channel structures 150, a channel hole would have to be formed first and the channel structure be disposed in it.
Regarding claim 6, Yang in view of Liou discloses the semiconductor structure for a 3D memory of claim 1. Yang further teaches in Fig. 3H the stacked structure (120A, [0054]) further comprises a plurality of gate layers (137, which includes 134, 135, and 136, [0065]), and the gate layers (137) and the first dielectric layers (131, [0054]) are stacked alternately.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Luo in view of Yeh et al. (US 2022/0199639 A1, hereafter Yeh).
Regarding claim 5, Yang in view of Luo discloses the semiconductor structure for a 3D memory of claim 4. Yang further teaches in Fig. 3H the vertical channel structure (150, [0059]) comprises:
a channel layer (152, [0052]), disposed on a sidewall of the vertical channel hole;
a dielectric pillar (core filling layer 153, [0059]), filled in the vertical channel hole.
a source pillar and a drain pillar, disposed in the dielectric pillar and separated from each other.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Luo in view of Noguchi et al. (US 2021/0257500 A1, hereafter Noguchi) and Chen (US 2017/00477289 A1).
Regarding claim 7, Yang in view of Luo discloses the semiconductor structure for a 3D memory of claim 1. Yang fails to explicitly disclose a ground layer disposed between the stacked structure and the insulating layer, wherein the vertical channel structure penetrates through the ground layer.
However, Yang teaches the substrate can be a multi-layered substrate [0055]. Noguchi teaches a memory device similar to Yang in Fig. 3 in which the substrate 11 [0023] has a ground structure (12, [0023]) between the stacked structure (15, [0023]) and the insulating layer (12a, [0024]). Chen teaches a similar memory device in which the addition of the ground increases the amount of memory blocks in the device, thereby increasing the storage space of the device [0022]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yang to include a ground layer as depicted in Noguchi in order to increase storage space in the memory device.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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