Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The office now relies on new reference Takahashi (US 8426311 B2), rather than Choi, for the claimed first and second plating layers and the relationship between the protection layer and the plating layers as described below, introducing the new ground of rejection necessitated by amendments.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 11 and 13-15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 3, 11 and 13-15 recites the limitation “…the plating layer…”. There is insufficient antecedent basis for this limitation in the claims. Since claim 1 now recites “…a first plating layer and a second plating layer…”, but does not recite a singular “plating layer”. Therefore, it is unclear whether
Claims 3, 11 and 13-15 recite “…the plating layer…”. It is unclear if the claims 3, 11 and 13-15 refer to the first plating layer, the second plating layer, both the first and second plating layers collectively, or another plating layer. For the purpose of examination, this limitation is interpretated as first plating layer or second plating layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 11-15, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 5386087 A) in view of Takahashi (US 8426311 B2).
Re: Independent Claim 1 (Currently amended), Lee discloses a module board comprising:
a substrate comprising a surface (Lee, printed circuit board 2 (substrate) comprises a laminated board 4 (surface));
a wire pattern on the substrate surface (Lee, Fig 1, Printed circuit pattern layer 6 with circuit pattern 12); a protection layer on the substrate surface (solder mask layer 8 is protection layer) and configured to expose an edge region of the substrate surface (Lee, Fig 1, solder mask layer 8 has U-shaped recess 14 opened at edge 4a); and
a plurality of tab terminals on the edge region of the substrate surface in adjacent, spaced apart relationship (Lee, Fig 1-5, Column 3, lines 31-38, solder pads 10/connection land portion 18a arranged along one edge 4a and formed continuously with the circuit pattern; since tab terminal is an edge terminal pad used to make external connection, in Lee that structure is the solder pad 10 with its connection land portion 18a), wherein the plurality of tab terminals are connected to the wire pattern (column 1, lines 48-50, plurality of connection land portions formed continuous with the circuit pattern),
wherein each tab terminal has a width that is larger than a width of a portion of the wire pattern to which each tab terminal is connected (Lee, Fig. 1, pad 10 is visibly wider than the trace 12), wherein each tab terminal comprises a pattern layer (Lee, Fig 1, pads 10 are part of the printed circuit pattern layer 6), wherein the protection layer is on a portion of the pattern layer at a region where each tab terminal is connected to the wire pattern (solder mask 8 is on pattern layer 6 at region where pad 10 (edges 10b-10d) is connected to trace 12),
wherein a plating layer is on a remaining portion of the pattern layer (Lee, column 3, lines 42-43, "the surface of solder pad 10 is tin plated" and Fig.1, column 3, lines 62-65, "the surface of the solder pad 10 defining the bottom of the U-shaped opening 14 provides an exposed surface not covered with the solder mask layer 8". Accordingly, Lee discloses a plating layer (tin plating) on the remaining, unmasked portion of the pattern layer (pad 10) while the mask 8 covers the rest. Thus, this portion of pattern layer is covered by platin layer).
Regarding the limitation “wherein a first plating layer and a second plating layer disposed on the first plating layer are on a remaining portion of the pattern layer, wherein the protection layer abuts the second plating layer, and wherein the first plating layer is spaced apart from the protection layer”, Lee teaches, in column 3, lines 42-43, "the surface of solder pad 10 is tin plated" and Fig.1, column 3, lines 62-65, "the surface of the solder pad 10 defining the bottom of the U-shaped opening 14 provides an exposed surface not covered with the solder mask layer 8". Accordingly, Lee discloses a plating layer (tin plating) on the remaining, unmasked portion of the pattern layer (pad 10) while the mask 8 covers the rest.
However, Lee is silent regarding wherein a first plating layer and a second plating layer disposed on the first plating layer are on a remaining portion of the pattern layer, wherein the protection layer abuts the second plating layer, and wherein the first plating layer is spaced apart from the protection layer.
However, Takahashi, in Fig. 15, teaches a plated conductive pad structure including a protective film 322 having an opening exposing an electrode pad 310, a first plating film 400 (first plating layer) formed on the electrode pad 310, and an outer plating film 440 (second plating layer) formed on the first plating film 400. Takahashi teaches, in Fig. 15, Protective film 322 is abutting outer plating film 440, while the central portion of first plating film 400 is laterally spaced apart from the protective film 322.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s exposed plated solder pad 10 by using Takahashi’s multilayer pad plating structure, including first plating film 400 as the claimed first plating layer and outer plating film 440 as the claimed second plating layer, in order to provide a known multilayer plated connection surface suitable for reliable electrical connection to a solder bump, wire, or external connection member.
Re: Claim 3 (Original), Lee and Takahashi disclose all the limitations of claim 1 on which this claim depends. Lee further discloses,
wherein a boundary between the protection layer and the plating layer extends in a width direction of each of the plurality of tab terminals (Lee, Fig 1 and Fig 2, Lee discloses a PCB in which the solder mask 8 (protection layer) forms a U-shaped opening 14 at the board edge 4a. In this structure, the mask's inner wall 16 covers the connecting side-edges 10b-10d of each pad 10, while the edge side 10a of the pad remains exposed and plated. The boundary between the protection layer (mask 8) and the plated pad surface is therefore the edge of opening 14 that runs across the pad from side edge 10c to side edge 10d, i.e., parallel to the board edge 4a- which is the width direction of the tab terminal).
Re: Claim 11, Lee and Takahashi disclose all the limitations of claim 1 on which this claim depends.
Lee further teaches, wherein the pattern layer comprises copper (Lee, column 3, lines 31-32, pattern layer is formed of a conductive metal, usually copper).
Takahashi further teaches the plating layer comprises at least one of nickel and gold (Takahashi, in column 7 lines 24-35, teaches plating film 400 is comprises nickel and 440 comprise gold).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the nickel and/or gold-plated layer finish of Takahashi on the edge-terminal pads of Lee to obtain the well-known conductivity and corrosion/wear benefits of copper wiring and Ni/Au finishes for contact.
Re: Independent Claim 12 (Currently amended), Lee discloses a module board comprising:
a substrate comprising a surface (Lee, printed circuit board 2 comprises a laminated board 4);
a wire pattern on the substrate surface (Lee, Fig 1, Printed circuit pattern layer 6 with circuit pattern 12);
a protection layer on the wire pattern (Lee, solder mask layer 8 is protection layer covering the circuit pattern layer 6, including circuit pattern 12); and
a plurality of tab terminals on an edge region of the substrate surface in adjacent, spaced apart relationship (Lee, Fig 1-5, Column 3, lines 31-38, solder pads 10/connection land portion 18a arranged along one edge 4a and formed continuously with the circuit pattern; since tab terminal is an edge terminal pad used to make external connection, in Lee that structure is the solder pad 10 with its connection land portion 18a), wherein the plurality of tab terminals are connected to the wire pattern (column 1, lines 48-50, plurality of connection land portions formed continuous with the circuit pattern), wherein each tab terminal has a width that is larger than a width of a portion of the wire pattern to which each tab terminal is connected (Fig. 1, pad 10 is visibly wider than the trace 12), wherein the protection layer is on a portion of each tab terminal at a region where each tab terminal is connected to the wire pattern (Lee, Fig.1, U-shaped opening 14 at the edge leaves only the edge-side of each pad exposed; the inner wall 16 of the solder mask covers the three connection side edges 10b-10d of the solder pad 10, i.e., the mask is on a portion of the pad at the pad-to-trace junction).
Regarding the limitation, wherein a first plating layer and a second plating layer disposed on the first plating layer are on a remaining portion of each tab terminal, and wherein the protection layer abuts the second plating layer, Lee teaches, Fig 1, column 3, lines 42-43, that the surface of the solder pad 10 is tin-plated, and also that the surface of the solder pad defining the bottom of the U-shaped opening 14 is an exposed surface not covered with the solder mask layer 8. Thus, the remaining (unmasked) portion of each pad carries the plating layer.
Lee is silent regarding wherein a first plating layer and a second plating layer disposed on the first plating layer are on a remaining portion of each tab terminal, and wherein the protection layer abuts the second plating layer.
However, Takahashi, in Fig. 15, teaches a plated conductive pad structure including a protective film 322 having an opening exposing an electrode pad 310, a first plating film 400 (first plating layer) formed on the electrode pad 310, and an outer plating film 440 (second plating layer) formed on the first plating film 400. Takahashi teaches, in Fig. 15, Protective film 322 is abutting outer plating film 440.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s remaining (unmasked) portion of each pad exposed solder pad 10 by using Takahashi’s multilayer pad plating structure, including first plating film 400 as the claimed first plating layer and outer plating film 440 as the claimed second plating layer, in order to provide a known multilayer plated connection surface suitable for reliable electrical connection to a solder bump, wire, or external connection member.
Re: Claim 13 (Original), Lee and Takahashi disclose all the limitations of claim 12 on which this claim depends. Lee further discloses,
wherein each tab terminal comprises a pattern layer (Fig 1, pads 10 are part of the printed circuit pattern layer 6), and wherein the plating layer is on a portion of the pattern layer (Fig.1, column 3, lines 62-65, "the surface of the solder pad 10 defining the bottom of the U-shaped opening 14 provides an exposed surface not covered with the solder mask layer 8". Accordingly, Lee discloses a plating layer (tin plating) on the remaining, unmasked portion of the pattern layer (pad 10) while the mask 8 covers the rest).
Re: Claim 14 (Original), Lee and Takahashi disclose all the limitations of claim 13 on which this claim depends. Lee further discloses,
wherein the pattern layer is completely covered by the protection layer and the plating layer (solder mask 8 (protection layer) is on pattern layer 6 at region where pad 10 (edges 10b-10d) is connected to trace 12. Also, in column 3, lines 42-43, Lee teaches "the surface of solder pad 10 is tin plated" and in Fig.1, column 3, lines 62-65, Lee teaches "the surface of the solder pad 10 defining the bottom of the U-shaped opening 14 provides an exposed surface not covered with the solder mask layer 8". Accordingly, Lee discloses a plating layer (tin plating) on the remaining, unmasked portion of the pattern layer (pad 10) while the mask 8 covers the rest. Thus, this portion of pattern layer is covered by platin layer).
Re: Claim 15 (Original), Lee and Takahashi disclose all the limitations of claim 14 on which this claim depends. Lee further discloses,
wherein a boundary between the protection layer and the plating layer extends in a width direction of each of the plurality of tab terminals (Lee, Fig 1 and Fig 2, Lee discloses a PCB in which the solder mask 8 (protection layer) forms a U-shaped opening 14 at the board edge 4a. In this structure, the mask's inner wall 16 covers the connecting side-edges 10b-10d of each pad 10, while the edge side 10a of the pad remains exposed and plated. The boundary between the protection layer (mask 8) and the plated pad surface is therefore the edge of opening 14 that runs across the pad from side edge 10c to side edge 10d, i.e., parallel to the board edge 4a- which is the width direction of the tab terminal).
Re: Claim 21 (New), Lee and Takahashi disclose all the limitations of claim 1 on which this claim depends.
Takahashi further teaches
wherein the protection layer abuts the second plating layer at an interface such that gas is substantially prevented from penetrating the interface (Takahashi teaches, in Fig. 15, protective layer 322 abuts outer/second plating film 440 at the boundary of the exposed pad opening, while first plating film 400 is spaced apart from protective film 322 by outer/second plating film 440. Because the protective film 322 and outer plate film 440 directly abut each other at the interface, the interface is closed by solid material rather than defining an open gap. Therefore, it is obvious that gas is substantially prevented form penetrating the interface.)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BIPANA ADHIKARI DAWADI/
Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
Prosecution Insights