DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/164,776, application filed on 02/06/2023. Claims 1-20 are currently pending in this application.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
4. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US PG Pub No. 2021/0367350) in view of SUTONO et al. (US PG Pub No. 2022/0311114).
5. With respect to claims 1, 10 and 20, Zhao teaches:
An electrical circuit component for an RF/EM circuit (see radio-frequency RF circuit, para 19; see RF circuit connected to an antenna, para 19; see double-strip line disposed on substrate of an RF circuit, para 36), comprising
a double-sided parallel-strip line (DSPSL) (double-sided parallel strip line, Abstract; para 7-9, 35-38)
wherein the DSPSL includes a pair of parallel-strip lines of conducting plate disposed back-to-back on opposite sides of a substrate.
Zhao appears to be silent regarding:
the DSPSL having a balanced line arranged to reject external noise from connected circuit components when fed to other electrical circuits during operation of the RF/EM circuit.
However, SUTONO teaches:
the DSPSL having a balanced line arranged to reject external noise from connected circuit components when fed to other electrical circuits during operation of the RF/EM circuit (balance for coupling, to overcome noise coupling imbalance, para 37; noise cancellation achieved using two differential split lines, para 30; managing aggressor noise from neighboring components, para 24; see noise coupling issues to connected devices, para 25; receiving noise from top/bottom levels, para 36; cumulative noise issues, para 38).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated SUTONO’s balanced noise cancellation feature(s) into the invention of Zhao for at least the following reason(s): SUTONO’s noise attenuation/cancellation features provide an advantage in a circuit involving DSL/RF technology similar to the technologies described in both Zhao and SUTONO.
6. With respect to claims 2 and 11, Zhao teaches:
wherein the DSPSL is provided as a computer-implemented circuit component for use on an electrical circuit design platform (DSPSL designed with characteristics for antenna, para 10; antenna implemented by designing characteristics in DSPSL, para 14; see compact design of product, reducing costs with design, para 64).
7. With respect to claims 3 and 12, Zhao teaches:
wherein the DSPSL is arranged to operate together with other active and passive components in the RF/EM circuit, wherein the RF/EM circuit is a simulated electrical circuit (see simulation of RF/antenna circuit, para 54; see components of RF/EM circuit, para 17-19, 50-53).
8. With respect to claims 4 and 13, Zhao teaches:
wherein the RF/EM circuit includes an in-phase power divider, an out-of-phase power divider, a bandpass filter, a rat-race hybrid circuit, and a DC biasing network, a push-pull amplifier and an oscillator (adjusting a phase of antenna, dividing energy to transmitted to paths to/within antenna, para 37-42).
9. With respect to claims 5 and 14, SUTONO teaches:
wherein the RF/EM circuit includes a balanced circuit (balance for coupling, to overcome noise coupling imbalance, para 37; noise cancellation achieved using two differential split lines, para 30; managing aggressor noise from neighboring components, para 24; see noise coupling issues to connected devices, para 25; receiving noise from top/bottom levels, para 36; cumulative noise issues, para 38).
the pair of parallel-strip lines are electrically connected by a via across the substrate (see via connections for strip lines, para 32, 35, 38, 40-43).
10. With respect to claims 6 and 15, SUTONO teaches:
wherein the DSPSL comprises a virtual ground plane between the DSPSL (see ground layer 755, Fig 7B, showing ground layer between DSPSL, para 48-50).
11. With respect to claims 7 and 16, Zhao teaches:
wherein the DSPSL comprises no physical ground planes (ground plate is optional, suggesting that design can exist with no physical ground plane, para 18, 52-55).
12. With respect to claims 8 and 17, SUTONO teaches:
wherein the virtual ground plane is defined at a mid-point of a dielectric separation between the pair of parallel-strip lines of conducting plate (see ground layer at mid-point between pair of strip lines, 755, Fig 7B, showing ground layer between DSPSL, para 48-50).
13. With respect to claims 9 and 18, Zhao teaches:
wherein the DSPSL further comprising an inserted conductor plane at a mid-point of a dielectric separation between the pair of parallel-strip lines of conducting plate (see conductor plate, located at mid point of separation layer between strip lines, para 38).
14. With respect to claim 19, Zhao teaches:
the step of simulating a circuit performance of the RF/EM circuit including the DSPSL on the electrical circuit design platform without using an electromagnetic (EM) simulator (see simulation of RF/antenna circuit, para 54; see components of RF/EM circuit, para 17-19, 50-53).
Conclusion
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851