DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5, 7-9, and 12-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1 and 12, the limitation “a width of the mold layer is smaller in the area adjacent to the lower metal layer than in the area adjacent to the first surface of the wiring structure, and smaller in the area adjacent to the upper metal layer than in the area adjacent to the second surface of the interposer,” as recited in claim 1 and similarly in claim 12, does not appear to have support in the originally filed disclosure. Specifically, there is no discussion of any width of the mold layer.
Note the dependent claims do not cure the deficiencies of the claims on which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 7-9, and 12-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 12, the limitation “a width of the mold layer is smaller in the area adjacent to the lower metal layer than in the area adjacent to the first surface of the wiring structure, and smaller in the area adjacent to the upper metal layer than in the area adjacent to the second surface of the interposer,” as recited in claim 1 and similarly in claim 12, is unclear as to what is required by the claim. Specifically, it is unclear as to if it requires a with of a portion of the mold layer or the mold layer overall. Fig. 5 appears to shows an overall width of the mold layer 190 which is the same at all vertical positions. While there are portions which might be narrower than other portions at the claimed positions, it cannot be ascertained which portions those might be or if it is merely a portion required by the claim.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5, 8-9, and 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meyer et al. (US 2019/0206833; herein “Meyer”) in view of Yao et al. (US 2020/0312803; herein “Yao”).
Regarding claim 1, Meyer discloses in Fig. 2A and related text a semiconductor package comprising:
a wiring structure (230, see [0033]) including a first insulating layer (see [0033]) and a first wiring pad (232 at upper surface, see [0033]), wherein the first wiring pad is in the first insulating layer;
a semiconductor chip (210, see [0032]) on a first surface of the wiring structure;
an interposer (250, see [0034]) having a second surface facing the first surface of the wiring structure on the semiconductor chip, wherein the interposer includes a second insulating layer (see [0036]) and a second wiring pad (227, see [0035]), and the second wiring pad is in the second insulating layer;
a first connecting structure (225, see [0033]) and the first connecting structure connects the first wiring pad and the second wiring pad; and
a mold layer (215, see [0032]) between the first surface of the wiring structure and the second surface of the interposer.
Meyer does not disclose
the first connecting structure including a first metal layer and a second metal layer surrounding the first metal layer, wherein the first metal layer includes a lower metal layer adjacent to the wiring structure and an upper metal layer adjacent to the interposer;
wherein a width of the second metal layer is greater in an area adjacent to the lower metal layer than in an area adjacent to the first surface of the wiring structure, and greater in an area adjacent to the upper metal layer than in an area adjacent to the second surface of the interposer, and
a width of the mold layer is smaller in the area adjacent to the lower metal layer than in the area adjacent to the first surface of the wiring structure, and smaller in the area adjacent to the upper metal layer than in the area adjacent to the second surface of the interposer.
In the same field of endeavor, Yao teaches in Fig. 1A, 3A, 4, 5 and related text a semiconductor package having a first connecting structure (106a/b/c, see [0031]),
the first connecting structure including a first metal layer (108a/b, see [0031]) and a second metal layer (105, see [0031]) surrounding the first metal layer, wherein the first metal layer includes a lower metal layer (108b) adjacent to the wiring (104, see [0031]) structure and an upper metal layer (1089a) adjacent to the interposer (102, see [0031]);
wherein a width of the second metal layer is greater in an area adjacent to the lower metal layer than in an area adjacent to the first surface of the wiring structure, and greater in an area adjacent to the upper metal layer than in an area adjacent to the second surface of the interposer (e.g. greater width at 342/442 than at either bond pad, see Figs. 4-5; see also [0038] at least; note that the area at 342/442 is interpreted as “adjacent” to each of the lower and upper metal layers, “adjacent” being interpreted as “Close to; lying near”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Meyer by having the first connecting structure including a first metal layer and a second metal layer surrounding the first metal layer, wherein the first metal layer includes a lower metal layer adjacent to the wiring structure and an upper metal layer adjacent to the interposer, as shown by Yao, in order to achieve a high aspect ratio connector with a tight pitch (see Yao, abstract at least). Note that the limitation “a width of the mold layer is smaller in the area adjacent to the lower metal layer than in the area adjacent to the first surface of the wiring structure, and smaller in the area adjacent to the upper metal layer than in the area adjacent to the second surface of the interposer” is taught by the combination of the widths of the metal layers, as shown by Yao, and the mold layer being in direct contact with the first connecting structure and therefore having a converse shape, as shown by Meyer.
Additionally, it would have been an obvious matter of design choice to have the widths as claimed, since such a modification would have involved a mere change in the shape, size and/or proportion of a component (see Yao [0022], [0034], [0038] which discusses the obviousness of changing the upper and lower metal layers to change the shape of the connecting structure). Changes in shape, size and/or proportion are each generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04.
Regarding claim 2, Meyer further discloses wherein the first connecting structure (225) is outside the semiconductor chip, and the first connecting structure is configured to support the wiring structure and the interposer.
Regarding claim 3, Meyer further discloses wherein the mold layer (215) covers an upper surface of the semiconductor chip (210).
Regarding claim 4, Meyer further discloses wherein a thickness of the first connecting structure (225) is the same as a thickness of the mold layer (215).
Regarding claim 5, the combined device shows wherein the upper metal layer and the lower metal layer are spaced apart from each other (Yao: 108a and 108b spaced apart).
Regarding claim 8, the combined device shows wherein the first connecting structure does not include insulating material (Yao: e.g. 108a/b are copper and 105 is solder, see [0032] and [0031]).
Regarding claim 9, Meyer further discloses
the wiring structure further includes a third wiring pad (a second 232 connected to a second 225) spaced apart from the first wiring pad, and the third wiring pad is in the first insulating layer, and
the interposer further includes a fourth wiring pad (a second 227 connected to the second 225) spaced apart from the second wiring pad, and the fourth wiring pad is in the second insulating layer.
Regarding claim 12, Meyer discloses in Fig. 2A and related text a semiconductor package comprising:
a first semiconductor package (e.g. package of chip 210, see [0032); and
a second semiconductor package (e.g. package of chip 220, see [0036] and [0037])placed on the first semiconductor package,
wherein the first semiconductor package includes a wiring structure (230, see [0033]) including (see [0033]) and a first wiring pad (232 at upper surface, see [0033]), the first wiring pad in the first insulating layer,
a semiconductor chip (210) on a first surface of the wiring structure,
an interposer (250, see [0034]) having a first surface facing the semiconductor chip, the interposer including a second insulating layer (see [0036]) and a second wiring pad (227, see [0035]) in the second insulating layer,
a connecting structure (225, see [0033]) between the wiring structure and the interposer, and
a mold layer (215, see [0032]) integrally covering the connecting structure and an upper surface of the semiconductor chip.
Yao teaches the remaining claimed limitations in substantially the same manner and for substantially the same reasons as applied to claim 1 above.
Regarding claim 13, the combined device shows the plurality of core layers include a first core layer (Yao: 108b) and a second core layer (108a) stacked on the first core layer, the first core layer is adjacent to the first surface of the wiring structure (104), the second core layer is adjacent to the first surface of the interposer (102), and the metal layer (105) connects the first wiring pad and the second wiring pad (pads in 102 and 104).
Regarding claim 14, Meyer further discloses wherein the connecting structure (225) is outside the semiconductor chip (210), and the connecting structure is configured to support the wiring structure (230) and the interposer (250).
Regarding claim 15, Meyer further discloses wherein a thickness of the connecting structure (225) is the same as a thickness of the mold layer (215).
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meyer in view of Yao, as applied to claims 1 and 12 above, and further in view of Lin et al. (US 2020/0058633; herein “Lin”)
Regarding claims 7 and 16, Meyer further discloses wherein the first metal layer [each of the plurality of core layers] includes copper (Cu) (see [0032]), but does not explicitly disclose the second metal layer [the metal layer] includes tin (Sn).
In the same field of endeavor, Lin teaches in Fig. 1 and related text the first metal layer [each of the plurality of core layers] includes copper (Cu) and the second metal layer [the metal layer] includes tin (Sn) (Cu cored Cu/Sn balls, see [0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Meyer and Lin by having the first metal layer [each of the plurality of core layers] include copper (Cu) and the second metal layer [the metal layer] include tin (Sn), as taught by Lin, because it has been held that the selection of a known material based on its suitability for its intended use supports a prima facie obviousness. See MPEP 2144.07.
Response to Arguments
Applicant's arguments filed 10/20/2025 have been fully considered but they are not persuasive.
Applicant argues (page 10-11) that Meyer and Yao would not be combined because they are incompatible fabrication processes. Specifically, applicant argues that the method of Meyer relies on an initial molding step form a seal around ball 428 and filling of an opening to achieve an effective connection to the substrate, which is incompatible with the structure of Yao and the thermal process of Yao.
In response, the examiner disagrees. Specifically, the method of making is not germane to the product. The modification of Meyer with the structural difference of Yao does not render the device inoperable, and therefore the combination of the structural features are not incompatible. Additionally, while Meyer teaches a method that is different than a method of Yao, it is entirely within the skill of the ordinary artisan to properly modify the method or the materials of Meyer (e.g. bonding 310 to 330 first, forming the connecting structure, and then applying the mold layer) to arrive at a device with the benefits of the connecting structure of Yao. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Applicant argues (page 11-12) that Meyer and Yao would not be combined because Meyer teaches away from use of solder bumps with the benefit of reduced package thickness, “which is the opposite of Yao’s objective.”
In response, the examiner disagrees. Specifically, Meyer discusses the elimination of solder-based interconnections shown as 126 in Fig. 1. In the current rejection, the combination does not add an additional solder-based interconnection between the packages, but rather replaces through mold via structure 225 of Meyer with the structure of Yao. The teachings of Yao related to height are specific to aspect ratio and increasing pitch (see [0018], [0020], [0022]) and not a discussion of increasing overall height of the connection. In other words, it is not a goal of Yao to increase overall height, but rather to achieve an increased ratio of height to pitch in light of “continued reduction in end product size,” “reduced size system in package components,” and “small package volume at low-cost,” (see [0003]).
Applicant’s remaining arguments have been fully considered but are moot in view of the new grounds of rejection presented above. In particular, it is noted that additional figures of Yao are newly relied upon to teach the newly added limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896 11/26/2025